From 5f3dc9dd5b9f1004ae8cf014f88cb13225b986f1 Mon Sep 17 00:00:00 2001 From: Fischer Moseley Date: Thu, 9 Feb 2023 15:10:09 -0500 Subject: [PATCH] fix width issue --- README.md | 2 +- examples/counter/ila.yaml | 2 +- examples/counter/src/debug.sv | 12 +++++------ examples/counter/src/top_level.sv | 2 +- manta.py | 33 ++++++++++++++++--------------- 5 files changed, 26 insertions(+), 25 deletions(-) diff --git a/README.md b/README.md index c9b5c1c..daae783 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ Manta is a tool for debugging FPGA designs over UART. It has two modes for doing this, downlink and uplink. The downlink mode feels similar to a logic analyzer, in that Manta provides a waveform view of a configurable set of signals, which get captured when some trigger condition is met. The uplink mode allows a host machine to remotely set values of registers on the FPGA via a python interface. This permits rapid prototyping of logic in Python, and a means of incrementally migrating it to HDL. A more detailed description of each mode is below. -Manta is written in Python, and generates SystemVerilog HDL. It's cross-platform, and its only dependency is pySerial. The SystemVerilog templates are included in the Python source, so only a single python file must be included in your project. +Manta is written in Python, and generates SystemVerilog HDL. It's cross-platform, and its only dependencies are pySerial and pyYAML. The SystemVerilog templates are included in the Python source, so only a single python file must be included in your project. ## Downlink Manta's downlink mode works by taking a JSON file describing the ILA configuration, and autogenerating a debug core with SystemVerilog. This gets included in the rest of the project's HDL, and is synthesized and flashed on the FPGA. It can then be controlled by a host machine connected over a serial port. The host can arm the core, and then when a trigger condition is met, the debug output is wired back to the host, where it's saved as a waveform file. This can then be opened and inspected in a waveform viewer like GTKWave. diff --git a/examples/counter/ila.yaml b/examples/counter/ila.yaml index 64ddc4c..63d351e 100644 --- a/examples/counter/ila.yaml +++ b/examples/counter/ila.yaml @@ -7,7 +7,7 @@ downlink: larry: 1 curly: 1 moe: 1 - shemp: 3 + shemp: 4 triggers: - larry && curly && ~moe diff --git a/examples/counter/src/debug.sv b/examples/counter/src/debug.sv index f620eb0..c92873b 100644 --- a/examples/counter/src/debug.sv +++ b/examples/counter/src/debug.sv @@ -86,7 +86,7 @@ module fifo ( `timescale 1ns / 1ps /* -This ILA was autogenerated on 05/02/2023 10:10:20 by fischerm +This ILA was autogenerated on 09 Feb 2023 at 15:05:46 by fischerm If this breaks or if you've got dank formal verification memes, please contact fischerm [at] mit.edu. @@ -105,16 +105,16 @@ module ila ( /* Begin autogenerated probe definitions */ input wire larry, - input wire curly, - input wire moe, - input wire [2:0] shemp, + input wire curly, + input wire moe, + input wire [3:0] shemp, /* End autogenerated probe definitions */ input wire rxd, output logic txd); /* Begin autogenerated parameters */ - localparam SAMPLE_WIDTH = 6; + localparam SAMPLE_WIDTH = 7; localparam SAMPLE_DEPTH = 4096; localparam DATA_WIDTH = 8; @@ -125,7 +125,7 @@ module ila ( assign trigger = (larry && curly && ~moe); logic [SAMPLE_WIDTH - 1 : 0] concat; - assign concat = {larry, curly, moe, shemp};; + assign concat = {larry, curly, moe, shemp}; /* End autogenerated parameters */ diff --git a/examples/counter/src/top_level.sv b/examples/counter/src/top_level.sv index d9be0b8..8900345 100644 --- a/examples/counter/src/top_level.sv +++ b/examples/counter/src/top_level.sv @@ -24,7 +24,7 @@ module top_level ( .larry(count[0]), .curly(count[1]), .moe(count[2]), - .shemp(count[5:3]), + .shemp(count[3:0]), .rxd(uart_txd_in), .txd(uart_rxd_out)); diff --git a/manta.py b/manta.py index 78d3371..1363e4c 100644 --- a/manta.py +++ b/manta.py @@ -120,7 +120,7 @@ def gen_downlink_core(config): dl = config["downlink"] # add timestamp - timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S") + timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S") buf = buf.replace("@TIMESTAMP", timestamp) # add user @@ -135,7 +135,7 @@ def gen_downlink_core(config): # add concat concat = [name for name in dl["probes"]] concat = ", ".join(concat) - concat = "{" + concat + "};" + concat = "{" + concat + "}" buf = buf.replace("@CONCAT", concat) # add probes @@ -147,7 +147,7 @@ def gen_downlink_core(config): else: probe_verilog.append(f"input wire [{width-1}:0] {name},") - probe_verilog = "\n\t".join(probe_verilog) + probe_verilog = "\n\t\t".join(probe_verilog) buf = buf.replace("@PROBES", probe_verilog) # add sample width @@ -276,20 +276,19 @@ def part_select(data, width): def make_widths(config): # {probe0, probe1, probe2} # [12, 1, 3] should produce - # [ (11,0) , (12, 12), (15,13) ] + # [ (15, 4) (3, 3) (2,0) ] widths = list(config["downlink"]["probes"].values()) - parts = [] - for i, width in enumerate(widths): - if i == 0: - parts.append((width - 1, 0)) - - else: - parts.append(((parts[i - 1][1] + width), (parts[i - 1][1] + 1))) - - # reversing this list is a little bit of a hack, should fix/document - return parts[::-1] + # easiest to make by summing them and incrementally subtracting + s = sum(widths) + slices = [] + for width in widths: + slices.append( (s-1, s-width) ) + s = s - width + + assert s == 0, 'Probe sizes are weird, cannot slice bits properly' + return slices def export_waveform(config, data, path): @@ -299,7 +298,9 @@ def export_waveform(config, data, path): from vcd import VCDWriter vcd_file = open(path, "w") - timestamp = datetime.now().strftime("%d/%m/%Y %H:%M:%S") + + # Use the datetime format that iVerilog uses + timestamp = datetime.now().strftime("%a %b %w %H:%M:%S %Y") with VCDWriter( vcd_file, timescale="10 ns", date=timestamp, version="manta" @@ -307,7 +308,7 @@ def export_waveform(config, data, path): # add probes to vcd file vcd_probes = [] for name, width in config["downlink"]["probes"].items(): - probe = writer.register_var("ila", name, "wire", size=width) + probe = writer.register_var("manta", name, "wire", size=width) vcd_probes.append(probe) # calculate bit widths for part selecting