diff --git a/.github/workflows/run_all_tests.yml b/.github/workflows/cross_platform_tests.yml
similarity index 100%
rename from .github/workflows/run_all_tests.yml
rename to .github/workflows/cross_platform_tests.yml
diff --git a/.github/workflows/formal_verification.yml b/.github/workflows/formal_verification.yml
new file mode 100644
index 0000000..e69de29
diff --git a/.github/workflows/functional_simulations.yml b/.github/workflows/functional_simulations.yml
new file mode 100644
index 0000000..a3edd63
--- /dev/null
+++ b/.github/workflows/functional_simulations.yml
@@ -0,0 +1,10 @@
+name: functional_simulations
+on: [push]
+jobs:
+  uart:
+    runs-on: ubuntu-latest
+    uses: actions/checkout@v3
+    uses: install-iverilog-apt
+    steps:
+      - run: iverilog -g2012 -o sim.out test/uart_tb.sv src/uart_tx.sv src/uart_rx.sv
+      - run: vvp sim.out
\ No newline at end of file
diff --git a/README.md b/README.md
index f9b8f16..841f06c 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,8 @@
 ![](assets/manta.png)
 
-![Functional Simulation](https://github.com/fischermoseley/manta/actions/workflows/run_all_tests.yml/badge.svg)
-![Formal Verification](https://github.com/fischermoseley/manta/actions/workflows/run_all_tests.yml/badge.svg)
+![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg)
+![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg)
+![cross_platform_tests](https://github.com/fischermoseley/manta/actions/workflows/cross_platform_tests.yml/badge.svg)
 
 Manta is a tool for debugging FPGA designs over UART. It has two modes for doing this, downlink and uplink. The downlink mode feels similar to a logic analyzer, in that Manta provides a waveform view of a configurable set of signals, which get captured when some trigger condition is met. The uplink mode allows a host machine to remotely set values of registers on the FPGA via a python interface. This permits rapid prototyping of logic in Python, and a means of incrementally migrating it to HDL. A more detailed description of each mode is below.