From 5454ed37e964003257e1eefba742a356d71b52b0 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Tue, 28 Feb 2023 19:11:58 -0500 Subject: [PATCH] add bus_tb, has nearly all of manta end-to-end --- src/manta/bridge_rx.v | 1 - src/manta/lut_mem.v | 37 ++--- test/bus.gtkw | 78 +++++++++ test/bus_tb.sv | 267 +++++++++++++++++++++--------- lut_mem.gtkw => test/lut_mem.gtkw | 16 +- test/lut_mem_tb.sv | 2 +- 6 files changed, 286 insertions(+), 115 deletions(-) create mode 100644 test/bus.gtkw rename lut_mem.gtkw => test/lut_mem.gtkw (79%) diff --git a/src/manta/bridge_rx.v b/src/manta/bridge_rx.v index f978e18..4e6c8f8 100644 --- a/src/manta/bridge_rx.v +++ b/src/manta/bridge_rx.v @@ -3,7 +3,6 @@ module bridge_rx( input wire clk, - input wire rst, input wire[7:0] axiid, input wire axiiv, diff --git a/src/manta/lut_mem.v b/src/manta/lut_mem.v index 74dcb3d..c0e596a 100644 --- a/src/manta/lut_mem.v +++ b/src/manta/lut_mem.v @@ -19,43 +19,26 @@ module lut_mem( output reg valid_o ); - parameter DEPTH = 8; parameter BASE_ADDR = 0; reg [DEPTH-1:0][15:0] mem; -reg [15:0] addr_ppln; -reg [15:0] wdata_ppln; -reg [15:0] rdata_ppln; -reg rw_ppln; -reg valid_ppln; - always @(posedge clk) begin - - // pipeline stage 1 - addr_ppln <= addr_i; - wdata_ppln <= wdata_i; - rdata_ppln <= rdata_i; - rw_ppln <= rw_i; - valid_ppln <= valid_i; - - // pipeline stage 2 - addr_o <= addr_ppln; - wdata_o <= wdata_ppln; - rdata_o <= rdata_ppln; - rw_o <= rw_ppln; - valid_o <= valid_ppln; + addr_o <= addr_i; + wdata_o <= wdata_i; + rdata_o <= rdata_i; + rw_o <= rw_i; + valid_o <= valid_i; + rdata_o <= rdata_i; if(valid_i) begin - // write to memory + // check if address is valid if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin - - // write to mem + + // read/write if (rw_i) mem[addr_i - BASE_ADDR] <= wdata_i; - - // read from mem - else rdata_ppln <= mem[addr_i - BASE_ADDR]; + else rdata_o <= mem[addr_i - BASE_ADDR]; end end end diff --git a/test/bus.gtkw b/test/bus.gtkw new file mode 100644 index 0000000..cc8211a --- /dev/null +++ b/test/bus.gtkw @@ -0,0 +1,78 @@ +[*] +[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI +[*] Tue Feb 28 23:56:47 2023 +[*] +[dumpfile] "/Users/fischerm/fpga/manta/bus.vcd" +[dumpfile_mtime] "Tue Feb 28 23:52:25 2023" +[dumpfile_size] 6844 +[savefile] "/Users/fischerm/fpga/manta/bus.gtkw" +[timestart] 18600000000000 +[size] 1710 994 +[pos] -1 -1 +*-46.201744 327700000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] bus_tb. +[sst_width] 353 +[signals_width] 276 +[sst_expanded] 1 +[sst_vpaned_height] 296 +@28 +bus_tb.clk +bus_tb.rst +@420 +bus_tb.test_num +@200 +- +- +-tb --> bridge_rx +@820 +bus_tb.tb_brx_axid[7:0] +@28 +bus_tb.tb_brx_axiv +@200 +- +- +-bridge_rx --> mem_1 +@22 +bus_tb.brx_mem_1_addr[15:0] +bus_tb.brx_mem_1_rdata[15:0] +bus_tb.brx_mem_1_wdata[15:0] +@28 +bus_tb.brx_mem_1_rw +bus_tb.brx_mem_1_valid +@200 +- +- +-mem_1 --> mem_2 +@22 +bus_tb.mem_1_mem_2_addr[15:0] +bus_tb.mem_1_mem_2_rdata[15:0] +bus_tb.mem_1_mem_2_wdata[15:0] +@28 +bus_tb.mem_1_mem_2_rw +bus_tb.mem_1_mem_2_valid +@200 +- +- +-mem_2 --> mem_3 +@22 +bus_tb.mem_2_mem_3_addr[15:0] +bus_tb.mem_2_mem_3_rdata[15:0] +@28 +bus_tb.mem_2_mem_3_rw +bus_tb.mem_2_mem_3_valid +@22 +bus_tb.mem_2_mem_3_wdata[15:0] +@200 +- +- +-mem_3 --> tb +@22 +bus_tb.mem_3_tb_addr[15:0] +bus_tb.mem_3_tb_rdata[15:0] +@23 +bus_tb.mem_3_tb_wdata[15:0] +@28 +bus_tb.mem_3_tb_rw +bus_tb.mem_3_tb_valid +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/test/bus_tb.sv b/test/bus_tb.sv index 534fa9d..51f761a 100644 --- a/test/bus_tb.sv +++ b/test/bus_tb.sv @@ -1,106 +1,215 @@ `default_nettype none -`timescale 1ns/1ps + +`define CP 10 +`define HCP 5 + +`define SEND_MESSAGE(MESSAGE) \ + tb_brx_axiv = 1; \ + for(int i=0; i < $size(MESSAGE); i++) begin \ + tb_brx_axid = MESSAGE[i]; \ + #`CP; \ + end \ + tb_brx_axiv = 0; \ module bus_tb; -// https://www.youtube.com/watch?v=WCOAr-96bGc + // https://www.youtube.com/watch?v=WCOAr-96bGc -//boilerplate -logic clk; -logic rst; + //boilerplate + logic clk; + logic rst; + integer test_num; + string message; -// uart inputs and outputs -logic rxd; -logic [7:0] uart_rx_axiod; -logic uart_rx_axiov; + // tb --> bridge_rx signals + logic [7:0] tb_brx_axid; + logic tb_brx_axiv; -logic txd; -logic [7:0] uart_tx_axiid; -logic uart_tx_axiiv; -logic uart_tx_axiir; + bridge_rx brx ( + .clk(clk), + .axiid(tb_brx_axid), + .axiiv(tb_brx_axiv), + .req_addr(brx_mem_1_addr), + .req_data(brx_mem_1_wdata), + .req_rw(brx_mem_1_rw), + .req_valid(brx_mem_1_valid), + .req_ready(1'b1)); -// the parameter will all get filled out in manta's big instantiator thing hehehee -parameter ADDR_WIDTH = 0; // $clog2( how much memory we need rounded up to the nearest 8 ) -parameter DATA_WIDTH = 0; + // bridge_rx --> mem_1 signals + logic [15:0] brx_mem_1_addr; + logic [15:0] brx_mem_1_wdata; + logic [15:0] brx_mem_1_rdata; + logic brx_mem_1_rw; + logic brx_mem_1_valid; -// request bus, gets connected to uart_rx (through a FSM) -logic [ADDR_WIDTH-1:0] req_addr; -logic [DATA_WIDTH-1:0] req_data; -logic req_rw; -logic req_valid; -logic req_ready; + assign brx_mem_1_rdata = 0; -// response bus, get connected to uart_tx (through a FSM, but the data's there in spirit) -logic res_valid; -logic res_ready; -logic res_data; + lut_mem #( + .DEPTH(8), + .BASE_ADDR(0) + ) mem_1 ( + .clk(clk), + .addr_i(brx_mem_1_addr), + .wdata_i(brx_mem_1_wdata), + .rdata_i(brx_mem_1_rdata), + .rw_i(brx_mem_1_rw), + .valid_i(brx_mem_1_valid), -uart_rx #( - .DATA_WDITH(8), - .CLK_FREQ_HZ(100_000_000), - .BAUDRATE(115200)) - uart_rx_uut ( - .clk(clk), - .rst(rst), - .rxd(rxd), + .addr_o(mem_1_mem_2_addr), + .wdata_o(mem_1_mem_2_wdata), + .rdata_o(mem_1_mem_2_rdata), + .rw_o(mem_1_mem_2_rw), + .valid_o(mem_1_mem_2_valid)); - .axiod(uart_rx_axiod), - .axiov(uart_rx_axiov)); + // mem_1 --> mem_2 signals + logic [15:0] mem_1_mem_2_addr; + logic [15:0] mem_1_mem_2_wdata; + logic [15:0] mem_1_mem_2_rdata; + logic mem_1_mem_2_rw; + logic mem_1_mem_2_valid; -uart_tx #( - .DATA_WDITH(8), - .CLK_FREQ_HZ(100_000_000), - .BAUDRATE(115200)) - uart_tx_uut ( - .clk(clk), - .rst(rst), - .txd(txd), + lut_mem #( + .DEPTH(8), + .BASE_ADDR(8) + ) mem_2 ( + .clk(clk), + .addr_i(mem_1_mem_2_addr), + .wdata_i(mem_1_mem_2_wdata), + .rdata_i(mem_1_mem_2_rdata), + .rw_i(mem_1_mem_2_rw), + .valid_i(mem_1_mem_2_valid), - .axiid(uart_tx_axiid), - .axiiv(uart_tx_axiiv), - .axiir(uart_tx_axiir)); + .addr_o(mem_2_mem_3_addr), + .wdata_o(mem_2_mem_3_wdata), + .rdata_o(mem_2_mem_3_rdata), + .rw_o(mem_2_mem_3_rw), + .valid_o(mem_2_mem_3_valid)); -bridge_rx bridge_rx_uut( - .clk(clk), - .rst(rst), + // mem_2 --> mem_3 signals + logic [15:0] mem_2_mem_3_addr; + logic [15:0] mem_2_mem_3_wdata; + logic [15:0] mem_2_mem_3_rdata; + logic mem_2_mem_3_rw; + logic mem_2_mem_3_valid; - // connect to uart_rx - .axiid(uart_rx_axiod), - .axiiv(uart_rx_axiov), + lut_mem #( + .DEPTH(8), + .BASE_ADDR(16) + ) mem_3 ( + .clk(clk), + .addr_i(mem_2_mem_3_addr), + .wdata_i(mem_2_mem_3_wdata), + .rdata_i(mem_2_mem_3_rdata), + .rw_i(mem_2_mem_3_rw), + .valid_i(mem_2_mem_3_valid), + + .addr_o(mem_3_btx_addr), + .wdata_o(mem_3_btx_wdata), + .rdata_o(mem_3_btx_rdata), + .rw_o(mem_3_btx_rw), + .valid_o(mem_3_btx_valid)); + + // mem_3 --> bridge_tx signals + logic [15:0] mem_3_btx_addr; + logic [15:0] mem_3_btx_wdata; + logic [15:0] mem_3_btx_rdata; + logic mem_3_btx_rw; + logic mem_3_btx_valid; - .req_addr(req_addr), - .req_data(req_data), - .req_rw(req_rw), - .req_valid(req_valid), - .req_ready(req_ready)); + bridge_tx btx ( + .clk(clk), + .axiod(btx_utx_axid), + .axiov(btx_utx_axiv), + .axior(btx_utx_axir), -bridge_tx bridge_tx_uut( - .clk(clk), - .rst(rst), + .res_data(mem_3_btx_rdata), + .res_valid(mem_3_btx_valid), + .res_ready()); - // connect to uart_tx - .axiod(uart_tx_axiid), - .axiov(uart_tx_axiiv), - .axior(uart_tx_axiir), - - .res_valid(res_valid), - .res_ready(res_ready), - .res_data(res_data)); + // bridge_tx --> uart_tx signals + logic [7:0] btx_utx_axid; + logic btx_utx_axiv; + logic btx_utx_axir; -always begin - #5; - clk = !clk; -end + uart_tx #( + .DATA_WIDTH(8), + .CLK_FREQ_HZ(100_000_000), + .BAUDRATE(10_000_000) + ) utx ( + .clk(clk), + .rst(rst), -initial begin - $dumpfile("bus.vcd"); - $dumpvars(0, bus_tb); + .axiid(btx_utx_axid), + .axiiv(btx_utx_axiv), + .axiir(btx_utx_axir), + .txd(utx_tb_txd)); + // utx --> tb signals + logic utx_tb_txd; -end + always begin + #`HCP + clk = !clk; + end + initial begin + $dumpfile("bus.vcd"); + $dumpvars(0, bus_tb); + // setup and reset + clk = 0; + rst = 0; + tb_brx_axid = 0; + tb_brx_axiv = 0; + test_num = 0; + #`CP + rst = 1; + #`CP + rst = 0; + #`HCP + + // throw some nonzero data in the memories just so we know that we're pulling from the right ones + mem_1.mem[0] = 16'h0000; + mem_1.mem[1] = 16'h0001; + mem_1.mem[2] = 16'h0002; + mem_1.mem[3] = 16'h0003; + mem_1.mem[4] = 16'h0004; + mem_1.mem[5] = 16'h0005; + mem_1.mem[6] = 16'h0006; + mem_1.mem[7] = 16'h0007; + + mem_2.mem[0] = 16'h0008; + mem_2.mem[1] = 16'h0009; + mem_2.mem[2] = 16'h000A; + mem_2.mem[3] = 16'h000B; + mem_2.mem[4] = 16'h000C; + mem_2.mem[5] = 16'h000D; + mem_2.mem[6] = 16'h000E; + mem_2.mem[7] = 16'h000F; + + mem_3.mem[0] = 16'h0010; + mem_3.mem[1] = 16'h0011; + mem_3.mem[2] = 16'h0012; + mem_3.mem[3] = 16'h0013; + mem_3.mem[4] = 16'h0014; + mem_3.mem[5] = 16'h0015; + mem_3.mem[6] = 16'h0016; + mem_3.mem[7] = 16'h0017; + #(10*`CP); + + /* ==== Test 1 Begin ==== */ + $display("\n=== test 1: read from 0x0001 for baseline functionality ==="); + test_num = 1; + + #(10*`CP); + /* ==== Test 1 End ==== */ + + message = {"M12345678", 8'h0D, 8'h0A}; + `SEND_MESSAGE(message) + + #(1000*`CP) + + $finish(); + end endmodule - - `default_nettype wire \ No newline at end of file diff --git a/lut_mem.gtkw b/test/lut_mem.gtkw similarity index 79% rename from lut_mem.gtkw rename to test/lut_mem.gtkw index c684be5..b7a4bf5 100644 --- a/lut_mem.gtkw +++ b/test/lut_mem.gtkw @@ -1,26 +1,28 @@ [*] [*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI -[*] Tue Feb 28 22:40:21 2023 +[*] Tue Feb 28 23:16:04 2023 [*] [dumpfile] "/Users/fischerm/fpga/manta/lut_mem.vcd" -[dumpfile_mtime] "Tue Feb 28 22:39:27 2023" -[dumpfile_size] 5116 +[dumpfile_mtime] "Tue Feb 28 23:14:40 2023" +[dumpfile_size] 5873 [savefile] "/Users/fischerm/fpga/manta/lut_mem.gtkw" -[timestart] 0 +[timestart] 96500000000000 [size] 1710 994 [pos] -1 -1 -*-45.675117 63700000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-46.420933 115000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] lut_mem_tb. [sst_width] 193 -[signals_width] 308 +[signals_width] 517 [sst_expanded] 1 [sst_vpaned_height] 305 @28 lut_mem_tb.clk +@420 +lut_mem_tb.test_num @200 - -tb --> mem_1 -@28 +@29 lut_mem_tb.tb_mem_1_valid @22 lut_mem_tb.tb_mem_1_addr[15:0] diff --git a/test/lut_mem_tb.sv b/test/lut_mem_tb.sv index 95e13db..2179bb6 100644 --- a/test/lut_mem_tb.sv +++ b/test/lut_mem_tb.sv @@ -192,7 +192,7 @@ module lut_mem_tb; $display("\n=== test 4: read from 0x0012 for baseline functionality ==="); test_num = 4; - tb_mem_1_addr = 16'h0012; + tb_mem_1_addr = 16'h000A; tb_mem_1_valid = 1; tb_mem_1_rw = 0; #`CP;