From 523b5673bcaf683ce11a2099a8e64455a3ffba5b Mon Sep 17 00:00:00 2001
From: Fischer Moseley <fischerm@peach.local>
Date: Thu, 9 Feb 2023 15:31:32 -0500
Subject: [PATCH] rename ila tests

---
 test/{ila_tb.sv => manta_tb.sv} | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
 rename test/{ila_tb.sv => manta_tb.sv} (82%)

diff --git a/test/ila_tb.sv b/test/manta_tb.sv
similarity index 82%
rename from test/ila_tb.sv
rename to test/manta_tb.sv
index 6d55862..34e9729 100644
--- a/test/ila_tb.sv
+++ b/test/manta_tb.sv
@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns / 1ps
 
-module ila_tb();
+module manta_tb();
     logic clk;
     logic rst;
     logic rxd;
@@ -13,9 +13,9 @@ module ila_tb();
     assign probe1 = count[1];
     assign probe2 = count[2];
 
-    // ILA
-    // later make this a `ILA that gets loaded from a svh file that the python script generates
-    ila #(.FIFO_DEPTH(64)) ila(
+    // manta
+    // later make this a `MANTA that gets loaded from a svh file that the python script generates
+    manta #(.FIFO_DEPTH(64)) manta(
         .clk(clk),
         .rst(rst),
         .probe0(probe0),
@@ -40,8 +40,8 @@ module ila_tb();
     logic [9:0] uart_data;
 
   	initial begin
-    	$dumpfile("ila.vcd");
-    	$dumpvars(0, ila_tb);
+    	$dumpfile("manta.vcd");
+    	$dumpvars(0, manta_tb);
 		clk = 0;
 		rst = 1;
         rxd = 1;