From 4ae061ffdc322f0ba4a6ef44af1dac0eab2ad731 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Thu, 7 Mar 2024 09:21:40 -0800 Subject: [PATCH] add missing .gitignore --- .../.gitignore | 2 + .../divider.sv | 193 ++++++++++++++++++ .../top_level.sv | 54 +++++ 3 files changed, 249 insertions(+) create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv create mode 100644 examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore new file mode 100644 index 0000000..f6ca93a --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/.gitignore @@ -0,0 +1,2 @@ +!top_level.sv +!divider.sv \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv new file mode 100644 index 0000000..623cce7 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/divider.sv @@ -0,0 +1,193 @@ +`default_nettype wire + +// file: divider.sv +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// popopopopopopopopopopop +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// __ethclk__50.00000______0.000______50.0______151.636_____98.575 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary_________100.000____________0.010 + +`timescale 1ps/1ps + +module divider + + (// Clock in ports + // Clock out ports + output ethclk, + input clk + ); + // Input buffering + //------------------------------------ +wire clk_divider; +wire clk_in2_divider; + IBUF clkin1_ibufg + (.O (clk_divider), + .I (clk)); + + + + + // Clocking PRIMITIVE + //------------------------------------ + + // Instantiation of the MMCM PRIMITIVE + // * Unused inputs are tied off + // * Unused outputs are labeled unused + + wire ethclk_divider; + wire clk_out2_divider; + wire clk_out3_divider; + wire clk_out4_divider; + wire clk_out5_divider; + wire clk_out6_divider; + wire clk_out7_divider; + + wire [15:0] do_unused; + wire drdy_unused; + wire psdone_unused; + wire locked_int; + wire clkfbout_divider; + wire clkfbout_buf_divider; + wire clkfboutb_unused; + wire clkout0b_unused; + wire clkout1_unused; + wire clkout1b_unused; + wire clkout2_unused; + wire clkout2b_unused; + wire clkout3_unused; + wire clkout3b_unused; + wire clkout4_unused; + wire clkout5_unused; + wire clkout6_unused; + wire clkfbstopped_unused; + wire clkinstopped_unused; + + MMCME2_ADV + #(.BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (1), + .CLKFBOUT_MULT_F (10.000), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (20.000), + .CLKOUT0_PHASE (0.000), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (10.000)) + mmcm_adv_inst + // Output clocks + ( + .CLKFBOUT (clkfbout_divider), + .CLKFBOUTB (clkfboutb_unused), + .CLKOUT0 (ethclk_divider), + .CLKOUT0B (clkout0b_unused), + .CLKOUT1 (clkout1_unused), + .CLKOUT1B (clkout1b_unused), + .CLKOUT2 (clkout2_unused), + .CLKOUT2B (clkout2b_unused), + .CLKOUT3 (clkout3_unused), + .CLKOUT3B (clkout3b_unused), + .CLKOUT4 (clkout4_unused), + .CLKOUT5 (clkout5_unused), + .CLKOUT6 (clkout6_unused), + // Input clock control + .CLKFBIN (clkfbout_buf_divider), + .CLKIN1 (clk_divider), + .CLKIN2 (1'b0), + // Tied to always select the primary input clock + .CLKINSEL (1'b1), + // Ports for dynamic reconfiguration + .DADDR (7'h0), + .DCLK (1'b0), + .DEN (1'b0), + .DI (16'h0), + .DO (do_unused), + .DRDY (drdy_unused), + .DWE (1'b0), + // Ports for dynamic phase shift + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (psdone_unused), + // Other control and status signals + .LOCKED (locked_int), + .CLKINSTOPPED (clkinstopped_unused), + .CLKFBSTOPPED (clkfbstopped_unused), + .PWRDWN (1'b0), + .RST (1'b0)); + +// Clock Monitor clock assigning +//-------------------------------------- + // Output buffering + //----------------------------------- + + BUFG clkf_buf + (.O (clkfbout_buf_divider), + .I (clkfbout_divider)); + + BUFG clkout1_buf + (.O (ethclk), + .I (ethclk_divider)); + +endmodule + +`default_nettype none \ No newline at end of file diff --git a/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv new file mode 100644 index 0000000..c38deb8 --- /dev/null +++ b/examples/verilog/nexys_a7/logic_analyzer_io_core_ethernet/top_level.sv @@ -0,0 +1,54 @@ +module top_level ( + input wire clk_100mhz, + output logic eth_refclk, + input wire btnc, + + output logic [15:0] led, + input wire [15:0] sw, + + input wire eth_crsdv, + output logic eth_mdc, + output logic eth_mdio, + output logic eth_rstn, + input wire [1:0] eth_rxd, + output logic [1:0] eth_txd, + output logic eth_txen +); + +logic ethclk; +assign eth_refclk = ethclk; +divider div (.clk(clk_100mhz), .ethclk(ethclk)); + + logic probe0; + logic [3:0] probe1; + logic [7:0] probe2; + logic [15:0] probe3; + + always @(posedge ethclk) begin + probe0 <= probe0 + 1; + probe1 <= probe1 + 1; + probe2 <= probe2 + 1; + probe3 <= probe3 + 1; + end + +manta manta_inst( + .clk(ethclk), + .rst(btnc), + .rmii_clocks_ref_clk(ethclk), + .rmii_crs_dv(eth_crsdv), + .rmii_mdc(eth_mdc), + .rmii_mdio(eth_mdio), + .rmii_rst_n(eth_rstn), + .rmii_rx_data(eth_rxd), + .rmii_tx_data(eth_txd), + .rmii_tx_en(eth_txen), + + .probe0(probe0), + .probe1(probe1), + .probe2(probe2), + .probe3(probe3), + + .led(led), + .sw(sw)); + +endmodule \ No newline at end of file