diff --git a/examples/nexys_a7/bram_core/manta.yaml b/examples/nexys_a7/bram_core/manta.yaml new file mode 100644 index 0000000..5427118 --- /dev/null +++ b/examples/nexys_a7/bram_core/manta.yaml @@ -0,0 +1,10 @@ +--- +cores: + my_lut_ram: + type: lut_ram + size: 64 + +uart: + port: "auto" + baudrate: 115200 + clock_freq: 100000000 \ No newline at end of file diff --git a/examples/nexys_a7/bram_core/read_write_test.py b/examples/nexys_a7/bram_core/read_write_test.py new file mode 100644 index 0000000..837dd12 --- /dev/null +++ b/examples/nexys_a7/bram_core/read_write_test.py @@ -0,0 +1,12 @@ +from manta import Manta +from random import randint + +m = Manta('manta.yaml') + +for addr in range(m.my_lut_ram.size): + write_data = randint(0, (2**16)-1) + m.my_lut_ram.write(addr, write_data) + + read_data = m.my_lut_ram.read(addr) + print(f"test addr: {addr} with data: {write_data}") + print(f" -> correct data received on readback?: {write_data == read_data}") \ No newline at end of file diff --git a/examples/nexys_a7/bram_core/src/bram_core.v b/examples/nexys_a7/bram_core/src/bram_core.v new file mode 100644 index 0000000..0057166 --- /dev/null +++ b/examples/nexys_a7/bram_core/src/bram_core.v @@ -0,0 +1,168 @@ +`default_nettype none +`timescale 1ns/1ps + +module bram_core ( + input wire clk, + + // input port + input wire [15:0] addr_i, + input wire [15:0] wdata_i, + input wire [15:0] rdata_i, + input wire rw_i, + input wire valid_i, + + // output port + output reg [15:0] addr_o, + output reg [15:0] wdata_o, + output reg [15:0] rdata_o, + output reg rw_o, + output reg valid_o, + + // BRAM itself + input wire bram_clk, + input wire [ADDR_WIDTH-1:0] addr, + input wire [BRAM_WIDTH-1:0] din, + output reg [BRAM_WIDTH-1:0] dout, + input wire we); + + parameter BASE_ADDR = 0; + + + // for now, let's pretend that this bram has a width of 33, and a depth of 256 + // parameter BRAM_WIDTH = 0; + // parameter BRAM_DEPTH = 0; + parameter BRAM_WIDTH = 18; + parameter BRAM_DEPTH = 256; + localparam ADDR_WIDTH = $clog2(BRAM_DEPTH); + + // Bus-Controlled side of BRAMs + reg [ADDR_WIDTH-1:0] addra_0 = 0; + reg [15:0] dina_0 = 0; + reg [15:0] douta_0; + reg wea_0 = 0; + + reg [ADDR_WIDTH-1:0] addra_1 = 0; + reg [1:0] dina_1 = 0; + reg [1:0] douta_1; + reg wea_1 = 0; + + // Pipelining + reg [3:0][15:0] addr_pipe = 0; + reg [3:0][15:0] wdata_pipe = 0; + reg [3:0][15:0] rdata_pipe = 0; + reg [3:0] valid_pipe = 0; + reg [3:0] rw_pipe = 0; + + always @(posedge clk) begin + addr_pipe[0] <= addr_i; + wdata_pipe[0] <= wdata_i; + rdata_pipe[0] <= rdata_i; + valid_pipe[0] <= valid_i; + rw_pipe[0] <= rw_i; + + addr_o <= addr_pipe[3]; + wdata_o <= wdata_pipe[3]; + rdata_o <= rdata_pipe[3]; + valid_o <= valid_pipe[3]; + rw_o <= rw_pipe[3]; + + for(int i=1; i<4; i=i+1) begin + addr_pipe[i] <= addr_pipe[i-1]; + wdata_pipe[i] <= wdata_pipe[i-1]; + rdata_pipe[i] <= rdata_pipe[i-1]; + valid_pipe[i] <= valid_pipe[i-1]; + rw_pipe[i] <= rw_pipe[i-1]; + end + + + + wea_0 <= 0; + wea_1 <= 0; + + if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + (2 * BRAM_DEPTH))) begin + // compute correct bram to talk to + case (addr_i % 2) + 0: begin + wea_0 <= rw_i; + addra_0 <= (addr_i - BASE_ADDR) / 2; + dina_0 <= wdata_i; + rdata_o <= douta_0; + end + + 1: begin + wea_1 <= rw_i; + addra_1 <= (addr_i - BASE_ADDR) / 2; + dina_1 <= wdata_i[1:0]; + rdata_o <= {14'b0, douta_1}; + end + endcase + end + + if( (valid_pipe[3]) && (addr_pipe[3] >= BASE_ADDR) && (addr_pipe[3] <= BASE_ADDR + (2 * BRAM_DEPTH))) begin + // compute correct bram to talk to + case (addr_pipe[3] % 2) + 0: begin + rdata_o <= douta_0; + end + + 1: begin + rdata_o <= {14'b0, douta_1}; + end + endcase + + end + + end + + + // User-Controlled Side of BRAMs + reg [15:0] dinb_0; + reg [15:0] doutb_0; + reg [1:0] dinb_1; + reg [1:0] doutb_1; + + assign dinb_0 = din[15:0]; + assign dinb_1 = din[17:16]; + assign dout = {doutb_1, doutb_0}; + + dual_port_bram #( + .RAM_WIDTH(16), + .RAM_DEPTH(BRAM_DEPTH) + ) bram_0 ( + + // port A is controlled by the bus + .clka(clk), + .addra(addra_0), + .dina(dina_0), + .douta(douta_0), + .wea(wea_0), + + // port B is exposed to the user + .clkb(bram_clk), + .addrb(addr), + .dinb(dinb_0), + .doutb(doutb_0), + .web(we)); + + dual_port_bram #( + .RAM_WIDTH(2), + .RAM_DEPTH(BRAM_DEPTH) + ) bram_1 ( + + // port A is controlled by the bus + .clka(clk), + .addra(addra_1), + .dina(dina_1), + .douta(douta_1), + .wea(wea_1), + + // port B is exposed to the user + .clkb(bram_clk), + .addrb(addr), + .dinb(dinb_1), + .doutb(doutb_1), + .web(we)); + + +endmodule +`default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/bram_core/src/dual_port_bram.v b/examples/nexys_a7/bram_core/src/dual_port_bram.v index 513a84c..cc8d6a3 100644 --- a/examples/nexys_a7/bram_core/src/dual_port_bram.v +++ b/examples/nexys_a7/bram_core/src/dual_port_bram.v @@ -25,6 +25,15 @@ module dual_port_bram #( output wire [RAM_WIDTH-1:0] doutb ); + // The following code either initializes the memory values to a specified file or to all zeros to match hardware + generate + integer i; + initial begin + for (i = 0; i < RAM_DEPTH; i = i + 1) + BRAM[i] = {RAM_WIDTH{1'b0}}; + end + endgenerate + reg [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0]; reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}}; reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}}; diff --git a/examples/nexys_a7/bram_core/src/ssd.v b/examples/nexys_a7/bram_core/src/ssd.v new file mode 100644 index 0000000..dc27ee4 --- /dev/null +++ b/examples/nexys_a7/bram_core/src/ssd.v @@ -0,0 +1,85 @@ +module ssd( + input wire clk_in, + input wire rst_in, + input wire [31:0] val_in, + output reg[6:0] cat_out, + output reg[7:0] an_out); + + parameter COUNT_TO = 100000; + logic[7:0] segment_state; + logic[31:0] segment_counter; + logic [3:0] routed_vals; + logic [6:0] led_out; + + bto7s mbto7s (.x_in(routed_vals), .s_out(led_out)); + + assign cat_out = ~led_out; + assign an_out = ~segment_state; + + always @(*) begin + case(segment_state) + 8'b0000_0001: routed_vals = val_in[3:0]; + 8'b0000_0010: routed_vals = val_in[7:4]; + 8'b0000_0100: routed_vals = val_in[11:8]; + 8'b0000_1000: routed_vals = val_in[15:12]; + 8'b0001_0000: routed_vals = val_in[19:16]; + 8'b0010_0000: routed_vals = val_in[23:20]; + 8'b0100_0000: routed_vals = val_in[27:24]; + 8'b1000_0000: routed_vals = val_in[31:28]; + default: routed_vals = val_in[3:0]; + endcase + end + + always @(posedge clk_in) begin + if (rst_in) begin + segment_state <= 8'b0000_0001; + segment_counter <= 32'b0; + end + + else begin + if (segment_counter == COUNT_TO) begin + segment_counter <= 32'd0; + segment_state <= {segment_state[6:0],segment_state[7]}; + end else begin + segment_counter <= segment_counter +1; + end + end + end +endmodule + + +module bto7s( + input wire [3:0] x_in, + output reg [6:0] s_out); + + reg sa, sb, sc, sd, se, sf, sg; + assign s_out = {sg, sf, se, sd, sc, sb, sa}; + + // array of bits that are "one hot" with numbers 0 through 15 + reg [15:0] num; + + assign num[0] = ~x_in[3] && ~x_in[2] && ~x_in[1] && ~x_in[0]; + assign num[1] = ~x_in[3] && ~x_in[2] && ~x_in[1] && x_in[0]; + assign num[2] = x_in == 4'd2; + assign num[3] = x_in == 4'd3; + assign num[4] = x_in == 4'd4; + assign num[5] = x_in == 4'd5; + assign num[6] = x_in == 4'd6; + assign num[7] = x_in == 4'd7; + assign num[8] = x_in == 4'd8; + assign num[9] = x_in == 4'd9; + assign num[10] = x_in == 4'd10; + assign num[11] = x_in == 4'd11; + assign num[12] = x_in == 4'd12; + assign num[13] = x_in == 4'd13; + assign num[14] = x_in == 4'd14; + assign num[15] = x_in == 4'd15; + + assign sa = num[0] || num[2] || num[3] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[12] ||num[14] ||num[15]; + assign sb = num[0] || num[1] || num[2] || num[3] || num[4] || num[7] || num[8] || num[9] || num[10] || num[13]; + assign sc = num[0] || num[1] || num[3] || num[4] || num[5] || num[6] || num[7] || num[8] || num[9] || num[10] || num[11] || num[13]; + assign sd = num[0] || num[2] || num[3] || num[5] || num[6] || num[8] || num[9] || num[11] || num[12] || num[13] || num[14]; + assign se = num[0] || num[2] || num[6] || num[8] || num[10] || num[11] || num[12] || num[13] || num[14] || num[15]; + assign sf = num[0] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[12] || num[14] || num[15]; + assign sg = num[2] || num[3] || num[4] || num[5] || num[6] || num[8] || num[9] || num[10] || num[11] || num[13] || num[14] ||num[15]; +endmodule diff --git a/examples/nexys_a7/bram_core/src/top_level.sv b/examples/nexys_a7/bram_core/src/top_level.sv index 6d12668..a0a6dff 100644 --- a/examples/nexys_a7/bram_core/src/top_level.sv +++ b/examples/nexys_a7/bram_core/src/top_level.sv @@ -3,25 +3,33 @@ module top_level ( input wire clk, - input wire [7:0] ja, - input wire [7:0] jb, - input wire [1:0] jc, - output logic [1:0] jd); + input wire btnc, - dual_port_bram #(.RAM_DEPTH(256), .RAM_WIDTH(2)) bram_0 ( - .clka(clk), - .addra(ja), - .dina(jc), - .douta(), - .wea(1'b1), + output logic [15:0] led, + output logic ca, cb, cc, cd, ce, cf, cg, + output logic [7:0] an, - .clkb(clk), - .addrb(jb), - .dinb(8'b0), - .doutb(jd), - .web(1'b0) + input wire uart_txd_in, + output logic uart_rxd_out ); + manta manta_inst ( + .clk(clk), + + .rx(uart_txd_in), + .tx(uart_rxd_out)); + + assign led = manta_inst.brx_my_bram_core_addr; + + logic [6:0] cat; + assign {cg,cf,ce,cd,cc,cb,ca} = cat; + ssd ssd ( + .clk_in(clk), + .rst_in(btnc), + .val_in( {manta_inst.my_bram_core_btx_rdata, manta_inst.brx_my_bram_core_wdata} ), + .cat_out(cat), + .an_out(an)); + endmodule `default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/bram_core/xdc/top_level.xdc b/examples/nexys_a7/bram_core/xdc/top_level.xdc index 51081b9..dda448a 100644 --- a/examples/nexys_a7/bram_core/xdc/top_level.xdc +++ b/examples/nexys_a7/bram_core/xdc/top_level.xdc @@ -37,62 +37,62 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl ## LEDs -# set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -# set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -# set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -# set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -# set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -# set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -# set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -# set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -# set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -# set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -# set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -# set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -# set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -# set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -# set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -# set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -# set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -# set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -# set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -# set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -# set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -# set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r ##7 segment display -# set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -# set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -# set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -# set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -# set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -# set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -# set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg # set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp -# set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -# set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -# set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -# set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -# set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -# set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -# set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -# set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] ##Buttons -# set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn -# set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -# set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -# set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -# set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl +#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd ##Pmod Headers @@ -100,50 +100,50 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {cl ##Pmod Header JA -set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] ##Pmod Header JB -set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] ##Pmod Header JC -set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -# set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -# set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -# set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -# set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -# set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -# set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] ##Pmod Header JD -set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -# set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -# set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -# set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -# set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -# set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -# set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] ##Pmod Header JXADC @@ -222,8 +222,8 @@ set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] ##USB-RS232 Interface -# set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -# set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out #set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts #set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts @@ -237,15 +237,15 @@ set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc #set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -# set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -# set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crs/udv #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -# set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -# set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen #set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] #set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -# set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn diff --git a/test/functional_sim/bram_core_tb/bram_core.v b/test/functional_sim/bram_core_tb/bram_core.v index 59b0403..856941f 100644 --- a/test/functional_sim/bram_core_tb/bram_core.v +++ b/test/functional_sim/bram_core_tb/bram_core.v @@ -47,67 +47,38 @@ module bram_core ( reg wea_1 = 0; // Pipelining - reg [15:0] addr_pipe_0 = 0; - reg [15:0] addr_pipe_1 = 0; - reg [15:0] addr_pipe_2 = 0; - reg [15:0] addr_pipe_3 = 0; - - - reg [15:0] wdata_pipe_0 = 0; - reg [15:0] wdata_pipe_1 = 0; - reg [15:0] wdata_pipe_2 = 0; - reg [15:0] wdata_pipe_3 = 0; - - reg [15:0] rdata_pipe_0 = 0; - reg [15:0] rdata_pipe_1 = 0; - reg [15:0] rdata_pipe_2 = 0; - reg [15:0] rdata_pipe_3 = 0; - - reg valid_pipe_0 = 0; - reg valid_pipe_1 = 0; - reg valid_pipe_2 = 0; - reg valid_pipe_3 = 0; - - reg rw_pipe_0 = 0; - reg rw_pipe_1 = 0; - reg rw_pipe_2 = 0; - reg rw_pipe_3 = 0; + reg [15:0][3:0] addr_pipe = 0; + reg [15:0][3:0] wdata_pipe = 0; + reg [15:0][3:0] rdata_pipe = 0; + reg [3:0] valid_pipe = 0; + reg [3:0] rw_pipe = 0; always @(posedge clk) begin - addr_pipe_0 <= addr_i; - wdata_pipe_0 <= wdata_i; - rdata_pipe_0 <= rdata_i; - valid_pipe_0 <= valid_i; - rw_pipe_0 <= rw_i; + addr_pipe[0] <= addr_i; + wdata_pipe[0] <= wdata_i; + rdata_pipe[0] <= rdata_i; + valid_pipe[0] <= valid_i; + rw_pipe[0] <= rw_i; - addr_pipe_1 <= addr_pipe_0; - wdata_pipe_1 <= wdata_pipe_0; - rdata_pipe_1 <= rdata_pipe_0; - valid_pipe_1 <= valid_pipe_0; - rw_pipe_1 <= rw_pipe_0; + addr_o <= addr_pipe[3]; + wdata_o <= wdata_pipe[3]; + rdata_o <= rdata_pipe[3]; + valid_o <= valid_pipe[3]; + rw_o <= rw_pipe[3]; - addr_pipe_2 <= addr_pipe_1; - wdata_pipe_2 <= wdata_pipe_1; - rdata_pipe_2 <= rdata_pipe_1; - valid_pipe_2 <= valid_pipe_1; - rw_pipe_2 <= rw_pipe_1; + for(int i=1; i<4; i=i+1) begin + addr_pipe[i] <= addr_pipe[i-1]; + wdata_pipe[i] <= wdata_pipe[i-1]; + rdata_pipe[i] <= rdata_pipe[i-1]; + valid_pipe[i] <= valid_pipe[i-1]; + rw_pipe[i] <= rw_pipe[i-1]; + end - addr_pipe_3 <= addr_pipe_2; - wdata_pipe_3 <= wdata_pipe_2; - rdata_pipe_3 <= rdata_pipe_2; - valid_pipe_3 <= valid_pipe_2; - rw_pipe_3 <= rw_pipe_2; - addr_o <= addr_pipe_3; - wdata_o <= wdata_pipe_3; - rdata_o <= rdata_pipe_3; - valid_o <= valid_pipe_3; - rw_o <= rw_pipe_3; wea_0 <= 0; wea_1 <= 0; - if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + (2 * BRAM_DEPTH))) begin // compute correct bram to talk to case (addr_i % 2) @@ -127,9 +98,9 @@ module bram_core ( endcase end - if( (valid_pipe_3) && (addr_pipe_3 >= BASE_ADDR) && (addr_pipe_3 <= BASE_ADDR + (2 * BRAM_DEPTH))) begin + if( (valid_pipe[3]) && (addr_pipe[3] >= BASE_ADDR) && (addr_pipe[3] <= BASE_ADDR + (2 * BRAM_DEPTH))) begin // compute correct bram to talk to - case (addr_pipe_3 % 2) + case (addr_pipe[3] % 2) 0: begin rdata_o <= douta_0; end diff --git a/test/functional_sim/bram_core_tb/bram_core_tb.sv b/test/functional_sim/bram_core_tb/bram_core_tb.sv index 3c25d68..af8cae5 100644 --- a/test/functional_sim/bram_core_tb/bram_core_tb.sv +++ b/test/functional_sim/bram_core_tb/bram_core_tb.sv @@ -13,6 +13,7 @@ task read_reg ( bram_core_tb.tb_bc_rw = 0; bram_core_tb.tb_bc_valid = 1; #`CP + bram_core_tb.tb_bc_rw = 0; bram_core_tb.tb_bc_valid = 0; while (!bram_core_tb.bc_tb_valid) #`CP; data = bram_core_tb.bc_tb_rdata; @@ -31,6 +32,7 @@ task write_reg( bram_core_tb.tb_bc_rw = 1; bram_core_tb.tb_bc_valid = 1; #`CP + bram_core_tb.tb_bc_rw = 0; bram_core_tb.tb_bc_valid = 0; while (!bram_core_tb.bc_tb_valid) #`CP;