diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index f5b5edf..63798c6 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -10,6 +10,11 @@ class VerilogManipulator:
         if filepath is not None:
             self.hdl = pkgutil.get_data(__name__, filepath).decode()
 
+            # scrub any default_nettype or timescale directives from the source
+            self.hdl = self.hdl.replace("`default_nettype none", "")
+            self.hdl = self.hdl.replace("`default_nettype wire", "")
+            self.hdl = self.hdl.replace("`timescale 1ns/1ps", "")
+
         else:
             self.hdl = None
 
@@ -436,7 +441,7 @@ class LogicAnalyzerCore:
         return la_inst.get_hdl()
 
     def gen_trigger_block_def(self):
-        trigger_block = VerilogManipulator("trigger_block_template.v")
+        trigger_block = VerilogManipulator("trigger_block_def_tmpl.v")
 
         # add probe ports to module declaration
         # these ports belong to the logic analyzer, but
@@ -502,7 +507,7 @@ class LogicAnalyzerCore:
         return trigger_block.get_hdl()
 
     def gen_sample_mem_def(self):
-        sample_mem = VerilogManipulator("sample_mem_tmpl.v")
+        sample_mem = VerilogManipulator("sample_mem_def_tmpl.v")
 
         # add probe ports to module declaration
         # - these are the ports that belong to the logic analyzer, but
@@ -525,7 +530,7 @@ class LogicAnalyzerCore:
         return sample_mem.get_hdl()
 
     def gen_logic_analyzer_def(self):
-        la = VerilogManipulator("logic_analyzer_tmpl.v")
+        la = VerilogManipulator("logic_analyzer_def_tmpl.v")
 
         # add top level probe ports to module declaration
         ports = la.net_dec(self.probes, "input wire", trailing_comma=True)
@@ -776,23 +781,7 @@ class Manta:
 
         return '\n'.join(core_chain)
 
-    def gen_header(self):
-        # generate header
-        user = os.environ.get("USER", os.environ.get("USERNAME"))
-        timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S")
-
-        header = f"""
-/*
-This manta definition was generated on {timestamp} by {user}
-
-If this breaks or if you've got dank formal verification memes,
-please contact fischerm [at] mit.edu
-
-Provided under a GNU GPLv3 license. Go wild.
-"""
-        return header
-
-    def gen_example_inst(self):
+    def gen_example_inst_ports(self):
         # this is a C-style block comment that contains an instantiation
         # of the configured manta instance - the idea is that a user
         # can copy-paste that into their design instead of trying to spot
@@ -806,16 +795,14 @@ Provided under a GNU GPLv3 license. Go wild.
         interface_ports = self.interface.hdl_top_level_ports()
         interface_ports = [port.split(',')[0] for port in interface_ports]
         interface_ports = [port.split(' ')[-1] for port in interface_ports]
-        interface_ports = [f".{port}({port})" for port in interface_ports]
-        interface_ports = [f"    {port},\n" for port in interface_ports]
+        interface_ports = [f".{port}({port}),\n" for port in interface_ports]
         interface_ports = "".join(interface_ports)
 
         core_chain_ports = []
         for core in self.cores:
             ports = [port.split(',')[0] for port in core.hdl_top_level_ports()]
             ports = [port.split(' ')[-1] for port in ports]
-            ports = [f".{port}({port})" for port in ports]
-            ports = [f"    {port},\n" for port in ports]
+            ports = [f".{port}({port}), \n" for port in ports]
             ports = "".join(ports)
             ports = "\n" + ports
             core_chain_ports.append(ports)
@@ -829,28 +816,18 @@ Provided under a GNU GPLv3 license. Go wild.
         if ports[-1] == ",":
             ports = ports[:-1]
 
-        return f"""
-Here's an example instantiation of the Manta module you configured,
-feel free to copy-paste this into your source!
+        return ports
 
-manta manta_inst (
-    .clk(clk),
-
-{ports});
-
-*/
-"""
-
-    def gen_declaration(self):
+    def gen_top_level_ports(self):
         # get all the top level connections for each module.
 
         interface_ports = self.interface.hdl_top_level_ports()
-        interface_ports = [f"    {port},\n" for port in interface_ports]
+        interface_ports = [f"{port},\n" for port in interface_ports]
         interface_ports = "".join(interface_ports) + "\n"
 
         core_chain_ports = []
         for core in self.cores:
-            ports = [f"    {port},\n" for port in core.hdl_top_level_ports()]
+            ports = [f"{port},\n" for port in core.hdl_top_level_ports()]
             ports = "".join(ports)
             core_chain_ports.append(ports)
 
@@ -863,12 +840,7 @@ manta manta_inst (
         if ports[-1] == ",":
             ports = ports[:-1]
 
-        return f"""
-module manta (
-    input wire clk,
-
-{ports});
-"""
+        return ports
 
     def gen_interface_rx(self):
         # instantiate interface_rx, substitute in register names
@@ -906,45 +878,41 @@ module manta (
 
         return interface_tx_conn + interface_tx_inst
 
-    def gen_footer(self):
-        return """endmodule\n"""
-
     def gen_module_defs(self):
         # aggregate module definitions and remove duplicates
         module_defs_with_dups = [self.interface.rx_hdl_def()] + [core.hdl_def() for core in self.cores] + [self.interface.tx_hdl_def()]
         module_defs = []
         module_defs = [m_def for m_def in module_defs_with_dups if m_def not in module_defs]
-        return '\n'.join(module_defs)
+        module_defs = [m_def.strip() for m_def in module_defs]
+        return '\n\n'.join(module_defs)
 
     def generate_hdl(self, output_filepath):
-        header = self.gen_header()
-        ex_inst = self.gen_example_inst()
-        declaration = self.gen_declaration() + "\n"
+        manta = VerilogManipulator("manta_def_tmpl.v")
+
+        timestamp = datetime.now().strftime("%d %b %Y at %H:%M:%S")
+        manta.sub(timestamp, "/* TIMESTAMP */")
+
+        user = os.environ.get("USER", os.environ.get("USERNAME"))
+        manta.sub(user, "/* USER */")
+
+        ex_inst_ports = self.gen_example_inst_ports()
+        manta.sub(ex_inst_ports, "/* EX_INST_PORTS */")
+
+        top_level_ports = self.gen_top_level_ports()
+        manta.sub(top_level_ports, "/* TOP_LEVEL_PORTS */")
+
         interface_rx = self.gen_interface_rx()
+        manta.sub(interface_rx, "/* INTERFACE_RX */")
+
         core_chain = self.gen_core_chain()
+        manta.sub(core_chain, "/* CORE_CHAIN */")
+
         interface_tx = self.gen_interface_tx()
-        footer = self.gen_footer()
+        manta.sub(interface_tx, "/* INTERFACE_TX */")
+
         module_defs = self.gen_module_defs()
-
-        # assemble all the parts
-        hdl = header + ex_inst + declaration + interface_rx + core_chain + interface_tx + footer
-        hdl += "\n /* ---- Module Definitions ----  */\n"
-        hdl += module_defs
-
-        # default_nettype and timescale directives only at the beginning and end
-        hdl = hdl.replace("`default_nettype none\n", "")
-        hdl = hdl.replace("`default_nettype wire\n", "")
-        hdl = hdl.replace("`timescale 1ns/1ps\n", "")
-
-        hdl = hdl.replace("`default_nettype none", "")
-        hdl = hdl.replace("`default_nettype wire", "")
-        hdl = hdl.replace("`timescale 1ns/1ps", "")
-
-        hdl = "`default_nettype none\n" + "`timescale 1ns/1ps\n" + hdl + "`default_nettype wire"
-
-        with open(output_filepath, 'w') as f:
-            f.write(hdl)
-
+        manta.sub(module_defs, "/* MODULE_DEFS */")
+        return manta.get_hdl()
 
 def main():
     # print help menu if no args passed or help menu requested
@@ -994,7 +962,9 @@ Supported commands:
         ), "Wrong number of arguments, only a config file and output file must both be specified."
 
         manta = Manta(argv[2])
-        manta.generate_hdl(argv[3])
+        hdl = manta.generate_hdl(argv[3])
+        with open(argv[3], "w") as f:
+            f.write(hdl)
 
     # run the specified core
     elif argv[1] == "run":
diff --git a/src/manta/bridge_rx.v b/src/manta/bridge_rx.v
index a462f3b..4440750 100644
--- a/src/manta/bridge_rx.v
+++ b/src/manta/bridge_rx.v
@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module bridge_rx(
+module bridge_rx (
     input wire clk,
 
     input wire[7:0] rx_data,
@@ -10,124 +10,121 @@ module bridge_rx(
     output reg[15:0] addr_o,
     output reg[15:0] wdata_o,
     output reg rw_o,
-    output reg valid_o
-);
+    output reg valid_o);
+
+    // this is a hack, the FSM needs to be updated
+    // but this will bypass it for now
+    parameter ready_i = 1;
+
+    parameter ADDR_WIDTH = 0;
+    parameter DATA_WIDTH = 0;
+
+    localparam PREAMBLE = 8'h4D;
+    localparam CR = 8'h0D;
+    localparam LF = 8'h0A;
+
+    localparam ACQUIRE = 0;
+    localparam TRANSMIT = 1;
+    localparam ERROR = 2;
+
+    reg [1:0] state;
+    reg [3:0] bytes_received;
+
+    // no global resets!
+    initial begin
+        addr_o = 0;
+        wdata_o = 0;
+        rw_o = 0;
+        valid_o = 0;
+        bytes_received = 0;
+        state = ACQUIRE;
+    end
+
+    reg [3:0] rx_data_decoded;
+    reg rx_data_is_0_thru_9;
+    reg rx_data_is_A_thru_F;
+
+    always @(*) begin
+        rx_data_is_0_thru_9 = (rx_data >= 8'h30) & (rx_data <= 8'h39);
+        rx_data_is_A_thru_F = (rx_data >= 8'h41) & (rx_data <= 8'h46);
+
+        if (rx_data_is_0_thru_9) rx_data_decoded = rx_data - 8'h30;
+        else if (rx_data_is_A_thru_F) rx_data_decoded = rx_data - 8'h41 + 'd10;
+        else rx_data_decoded = 0;
+    end
 
 
-// this is a hack, the FSM needs to be updated
-// but this will bypass it for now
-parameter ready_i = 1;
+    always @(posedge clk) begin
+        if (state == ACQUIRE) begin
+            if(rx_valid) begin
 
-parameter ADDR_WIDTH = 0;
-parameter DATA_WIDTH = 0;
-
-localparam PREAMBLE = 8'h4D;
-localparam CR = 8'h0D;
-localparam LF = 8'h0A;
-
-localparam ACQUIRE = 0;
-localparam TRANSMIT = 1;
-localparam ERROR = 2;
-
-reg [1:0] state;
-reg [3:0] bytes_received;
-
-// no global resets!
-initial begin
-    addr_o = 0;
-    wdata_o = 0;
-    rw_o = 0;
-    valid_o = 0;
-    bytes_received = 0;
-    state = ACQUIRE;
-end
-
-reg [3:0] rx_data_decoded;
-reg rx_data_is_0_thru_9;
-reg rx_data_is_A_thru_F;
-
-always @(*) begin
-    rx_data_is_0_thru_9 = (rx_data >= 8'h30) & (rx_data <= 8'h39);
-    rx_data_is_A_thru_F = (rx_data >= 8'h41) & (rx_data <= 8'h46);
-
-    if (rx_data_is_0_thru_9) rx_data_decoded = rx_data - 8'h30;
-    else if (rx_data_is_A_thru_F) rx_data_decoded = rx_data - 8'h41 + 'd10;
-    else rx_data_decoded = 0;
-end
-
-
-always @(posedge clk) begin
-    if (state == ACQUIRE) begin
-        if(rx_valid) begin
-
-            if (bytes_received == 0) begin
-                if(rx_data == PREAMBLE) bytes_received <= 1;
-            end
-
-            else if( (bytes_received >= 1) & (bytes_received <= 4) ) begin
-                // only advance if byte is valid hex digit
-                if(rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
-                    addr_o <= (addr_o << 4) | rx_data_decoded;
-                    bytes_received <= bytes_received + 1;
+                if (bytes_received == 0) begin
+                    if(rx_data == PREAMBLE) bytes_received <= 1;
                 end
 
-                else state <= ERROR;
-            end
-
-            else if( bytes_received == 5) begin
-                    if( (rx_data == CR) | (rx_data == LF)) begin
-                        valid_o <= 1;
-                        rw_o = 0;
-                        bytes_received <= 0;
-                        state <= TRANSMIT;
-                    end
-
-                    else if (rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
+                else if( (bytes_received >= 1) & (bytes_received <= 4) ) begin
+                    // only advance if byte is valid hex digit
+                    if(rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
+                        addr_o <= (addr_o << 4) | rx_data_decoded;
                         bytes_received <= bytes_received + 1;
-                        wdata_o <= (wdata_o << 4) | rx_data_decoded;
                     end
 
                     else state <= ERROR;
-            end
-
-            else if ( (bytes_received >= 6) & (bytes_received <= 8) ) begin
-
-                if (rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
-                    wdata_o <= (wdata_o << 4) | rx_data_decoded;
-                    bytes_received <= bytes_received + 1;
                 end
 
-                else state <= ERROR;
-            end
+                else if( bytes_received == 5) begin
+                        if( (rx_data == CR) | (rx_data == LF)) begin
+                            valid_o <= 1;
+                            rw_o = 0;
+                            bytes_received <= 0;
+                            state <= TRANSMIT;
+                        end
 
-            else if (bytes_received == 9) begin
-                bytes_received <= 0;
-                if( (rx_data == CR) | (rx_data == LF)) begin
-                    valid_o <= 1;
-                    rw_o <= 1;
-                    state <= TRANSMIT;
+                        else if (rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
+                            bytes_received <= bytes_received + 1;
+                            wdata_o <= (wdata_o << 4) | rx_data_decoded;
+                        end
+
+                        else state <= ERROR;
                 end
 
-                else state <= ERROR;
+                else if ( (bytes_received >= 6) & (bytes_received <= 8) ) begin
+
+                    if (rx_data_is_0_thru_9 | rx_data_is_A_thru_F) begin
+                        wdata_o <= (wdata_o << 4) | rx_data_decoded;
+                        bytes_received <= bytes_received + 1;
+                    end
+
+                    else state <= ERROR;
+                end
+
+                else if (bytes_received == 9) begin
+                    bytes_received <= 0;
+                    if( (rx_data == CR) | (rx_data == LF)) begin
+                        valid_o <= 1;
+                        rw_o <= 1;
+                        state <= TRANSMIT;
+                    end
+
+                    else state <= ERROR;
+                end
             end
         end
-    end
 
 
-    else if (state == TRANSMIT) begin
-        if(ready_i) begin
-            valid_o <= 0;
-            state <= ACQUIRE;
-        end
-
-        if(rx_valid) begin
-            if ( (rx_data != CR) & (rx_data != LF)) begin
+        else if (state == TRANSMIT) begin
+            if(ready_i) begin
                 valid_o <= 0;
-                state <= ERROR;
+                state <= ACQUIRE;
+            end
+
+            if(rx_valid) begin
+                if ( (rx_data != CR) & (rx_data != LF)) begin
+                    valid_o <= 0;
+                    state <= ERROR;
+                end
             end
         end
     end
-end
-
 endmodule
 `default_nettype wire
\ No newline at end of file
diff --git a/src/manta/bridge_tx.v b/src/manta/bridge_tx.v
index 44d4234..0f403ce 100644
--- a/src/manta/bridge_tx.v
+++ b/src/manta/bridge_tx.v
@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module bridge_tx(
+module bridge_tx (
     input wire clk,
 
     input wire [15:0] rdata_i,
@@ -12,61 +12,60 @@ module bridge_tx(
     input wire ready_i,
     output reg valid_o);
 
-localparam PREAMBLE = 8'h4D;
-localparam CR = 8'h0D;
-localparam LF = 8'h0A;
+    localparam PREAMBLE = 8'h4D;
+    localparam CR = 8'h0D;
+    localparam LF = 8'h0A;
 
-logic busy;
-logic [15:0] buffer;
-logic [3:0] byte_counter;
+    logic busy;
+    logic [15:0] buffer;
+    logic [3:0] byte_counter;
 
-initial begin
-    busy = 0;
-    buffer = 0;
-    byte_counter = 0;
-    valid_o = 0;
-end
-
-always @(posedge clk) begin
-    if (!busy) begin
-        if (valid_i && !rw_i) begin
-            busy <= 1;
-            buffer <= rdata_i;
-            byte_counter <= 0;
-            valid_o <= 1;
-        end
+    initial begin
+        busy = 0;
+        buffer = 0;
+        byte_counter = 0;
+        valid_o = 0;
     end
 
-    if (busy) begin
-
-        if(ready_i) begin
-            byte_counter <= byte_counter + 1;
-
-            if (byte_counter > 5) begin
+    always @(posedge clk) begin
+        if (!busy) begin
+            if (valid_i && !rw_i) begin
+                busy <= 1;
+                buffer <= rdata_i;
                 byte_counter <= 0;
+                valid_o <= 1;
+            end
+        end
 
-                // stop transmitting if we don't have both valid and read
-                if ( !(valid_i && !rw_i) ) begin
-                    busy <= 0;
-                    valid_o <= 0;
+        if (busy) begin
+
+            if(ready_i) begin
+                byte_counter <= byte_counter + 1;
+
+                if (byte_counter > 5) begin
+                    byte_counter <= 0;
+
+                    // stop transmitting if we don't have both valid and read
+                    if ( !(valid_i && !rw_i) ) begin
+                        busy <= 0;
+                        valid_o <= 0;
+                    end
                 end
             end
         end
     end
-end
-
-always @(*) begin
-    case (byte_counter)
-        0: data_o = PREAMBLE;
-        1: data_o = (buffer[15:12] < 10) ? (buffer[15:12] + 8'h30) : (buffer[15:12] + 8'h41 - 'd10);
-        2: data_o = (buffer[11:8] < 10) ? (buffer[11:8] + 8'h30) : (buffer[11:8] + 8'h41 - 'd10);
-        3: data_o = (buffer[7:4] < 10) ? (buffer[7:4] + 8'h30) : (buffer[7:4] + 8'h41 - 'd10);
-        4: data_o = (buffer[3:0] < 10) ? (buffer[3:0] + 8'h30) : (buffer[3:0] + 8'h41 - 'd10);
-        5: data_o = CR;
-        6: data_o = LF;
-        default: data_o = 0;
-    endcase
-end
 
+    always @(*) begin
+        case (byte_counter)
+            0: data_o = PREAMBLE;
+            1: data_o = (buffer[15:12] < 10) ? (buffer[15:12] + 8'h30) : (buffer[15:12] + 8'h41 - 'd10);
+            2: data_o = (buffer[11:8] < 10) ? (buffer[11:8] + 8'h30) : (buffer[11:8] + 8'h41 - 'd10);
+            3: data_o = (buffer[7:4] < 10) ? (buffer[7:4] + 8'h30) : (buffer[7:4] + 8'h41 - 'd10);
+            4: data_o = (buffer[3:0] < 10) ? (buffer[3:0] + 8'h30) : (buffer[3:0] + 8'h41 - 'd10);
+            5: data_o = CR;
+            6: data_o = LF;
+            default: data_o = 0;
+        endcase
+    end
 endmodule
 `default_nettype wire
\ No newline at end of file
diff --git a/src/manta/io_core_def_tmpl.v b/src/manta/io_core_def_tmpl.v
index a5fb8ef..0bf8875 100644
--- a/src/manta/io_core_def_tmpl.v
+++ b/src/manta/io_core_def_tmpl.v
@@ -20,6 +20,7 @@ module /* MODULE_NAME */ (
     );
 
     parameter BASE_ADDR = 0;
+
     always @(posedge clk) begin
         addr_o <= addr_i;
         wdata_o <= wdata_i;
diff --git a/src/manta/io_core_inst_tmpl.v b/src/manta/io_core_inst_tmpl.v
index b136b3a..52f83eb 100644
--- a/src/manta/io_core_inst_tmpl.v
+++ b/src/manta/io_core_inst_tmpl.v
@@ -16,5 +16,4 @@
     .wdata_o(),
     .rdata_o(),
     .rw_o(),
-    .valid_o()
-    );
\ No newline at end of file
+    .valid_o());
\ No newline at end of file
diff --git a/src/manta/logic_analyzer_tmpl.v b/src/manta/logic_analyzer_def_tmpl.v
similarity index 100%
rename from src/manta/logic_analyzer_tmpl.v
rename to src/manta/logic_analyzer_def_tmpl.v
diff --git a/src/manta/logic_analyzer_inst_tmpl.v b/src/manta/logic_analyzer_inst_tmpl.v
index d2c00bf..1004ab3 100644
--- a/src/manta/logic_analyzer_inst_tmpl.v
+++ b/src/manta/logic_analyzer_inst_tmpl.v
@@ -1,16 +1,16 @@
 logic_analyzer /* INST_NAME */ (
-        .clk(clk),
+    .clk(clk),
 
-        .addr_i(),
-        .wdata_i(),
-        .rdata_i(),
-        .rw_i(),
-        .valid_i(),
+    .addr_i(),
+    .wdata_i(),
+    .rdata_i(),
+    .rw_i(),
+    .valid_i(),
 
-        /* NET_CONNS */
+    /* NET_CONNS */
 
-        .addr_o(),
-        .wdata_o(),
-        .rdata_o(),
-        .rw_o(),
-        .valid_o());
\ No newline at end of file
+    .addr_o(),
+    .wdata_o(),
+    .rdata_o(),
+    .rw_o(),
+    .valid_o());
\ No newline at end of file
diff --git a/src/manta/lut_ram.v b/src/manta/lut_ram.v
index a102434..7c20169 100644
--- a/src/manta/lut_ram.v
+++ b/src/manta/lut_ram.v
@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module lut_ram(
+module lut_ram (
     input wire clk,
 
     // input port
@@ -16,33 +16,32 @@ module lut_ram(
     output reg [15:0] wdata_o,
     output reg [15:0] rdata_o,
     output reg rw_o,
-    output reg valid_o
-);
+    output reg valid_o);
 
-parameter DEPTH = 8;
-parameter BASE_ADDR = 0;
-parameter READ_ONLY = 0;
-reg [DEPTH-1:0] mem [15:0];
+    parameter DEPTH = 8;
+    parameter BASE_ADDR = 0;
+    parameter READ_ONLY = 0;
+    reg [DEPTH-1:0] mem [15:0];
 
-always @(posedge clk) begin
-    addr_o <= addr_i;
-    wdata_o <= wdata_i;
-    rdata_o <= rdata_i;
-    rw_o <= rw_i;
-    valid_o <= valid_i;
-    rdata_o <= rdata_i;
+    always @(posedge clk) begin
+        addr_o <= addr_i;
+        wdata_o <= wdata_i;
+        rdata_o <= rdata_i;
+        rw_o <= rw_i;
+        valid_o <= valid_i;
+        rdata_o <= rdata_i;
 
 
-    if(valid_i) begin
-        // check if address is valid
-        if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin
+        if(valid_i) begin
+            // check if address is valid
+            if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin
 
-            // read/write
-            if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= wdata_i;
-            else rdata_o <= mem[addr_i - BASE_ADDR];
+                // read/write
+                if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= wdata_i;
+                else rdata_o <= mem[addr_i - BASE_ADDR];
+            end
         end
     end
-end
 endmodule
 
 `default_nettype wire
\ No newline at end of file
diff --git a/src/manta/manta_def_tmpl.v b/src/manta/manta_def_tmpl.v
new file mode 100644
index 0000000..40db13c
--- /dev/null
+++ b/src/manta/manta_def_tmpl.v
@@ -0,0 +1,35 @@
+/*
+This manta definition was generated on /* TIMESTAMP */ by /* USER */
+
+If this breaks or if you've got dank formal verification memes,
+please contact fischerm [at] mit.edu
+
+Provided under a GNU GPLv3 license. Go wild.
+
+Here's an example instantiation of the Manta module you configured,
+feel free to copy-paste this into your source!
+
+manta manta_inst (
+    .clk(clk),
+
+    /* EX_INST_PORTS */);
+
+*/
+
+module manta(
+    input wire clk,
+
+    /* TOP_LEVEL_PORTS */);
+
+
+    /* INTERFACE_RX */
+
+    /* CORE_CHAIN */
+
+    /* INTERFACE_TX */
+
+endmodule
+
+/* ---- Module Definitions ----  */
+
+/* MODULE_DEFS */
\ No newline at end of file
diff --git a/src/manta/rx_uart.v b/src/manta/rx_uart.v
index dd56d75..ea35f7e 100644
--- a/src/manta/rx_uart.v
+++ b/src/manta/rx_uart.v
@@ -50,68 +50,68 @@
 `default_nettype none
 
 module rx_uart(
-	input wire i_clk,
-	input wire i_uart_rx,
-	output reg o_wr,
-	output reg [7:0] o_data);
+    input wire i_clk,
+    input wire i_uart_rx,
+    output reg o_wr,
+    output reg [7:0] o_data);
 
-	parameter  [15:0]	CLOCKS_PER_BAUD = 868;
-	localparam	[3:0]	IDLE      = 4'h0;
-	localparam	[3:0]	BIT_ZERO  = 4'h1;
-	// localparam	[3:0]	BIT_ONE   = 4'h2;
-	// localparam	[3:0]	BIT_TWO   = 4'h3;
-	// localparam	[3:0]	BIT_THREE = 4'h4;
-	// localparam	[3:0]	BIT_FOUR  = 4'h5;
-	// localparam	[3:0]	BIT_FIVE  = 4'h6;
-	// localparam	[3:0]	BIT_SIX   = 4'h7;
-	// localparam	[3:0]	BIT_SEVEN = 4'h8;
-	localparam	[3:0]	STOP_BIT  = 4'h9;
+    parameter  [15:0]	CLOCKS_PER_BAUD = 868;
+    localparam	[3:0]	IDLE      = 4'h0;
+    localparam	[3:0]	BIT_ZERO  = 4'h1;
+    // localparam	[3:0]	BIT_ONE   = 4'h2;
+    // localparam	[3:0]	BIT_TWO   = 4'h3;
+    // localparam	[3:0]	BIT_THREE = 4'h4;
+    // localparam	[3:0]	BIT_FOUR  = 4'h5;
+    // localparam	[3:0]	BIT_FIVE  = 4'h6;
+    // localparam	[3:0]	BIT_SIX   = 4'h7;
+    // localparam	[3:0]	BIT_SEVEN = 4'h8;
+    localparam	[3:0]	STOP_BIT  = 4'h9;
 
-	reg	[3:0]		state;
-	reg	[15:0]		baud_counter;
-	reg			zero_baud_counter;
+    reg	[3:0]		state;
+    reg	[15:0]		baud_counter;
+    reg			zero_baud_counter;
 
-	// 2FF Synchronizer
-	//
-	reg		ck_uart;
-	reg		q_uart;
-	initial	{ ck_uart, q_uart } = -1;
-	always @(posedge i_clk)
-		{ ck_uart, q_uart } <= { q_uart, i_uart_rx };
+    // 2FF Synchronizer
+    //
+    reg		ck_uart;
+    reg		q_uart;
+    initial	{ ck_uart, q_uart } = -1;
+    always @(posedge i_clk)
+        { ck_uart, q_uart } <= { q_uart, i_uart_rx };
 
-	initial	state = IDLE;
-	initial	baud_counter = 0;
+    initial	state = IDLE;
+    initial	baud_counter = 0;
 
-	always @(posedge i_clk)
-		if (state == IDLE) begin
-			state <= IDLE;
-			baud_counter <= 0;
-			if (!ck_uart) begin
-				state <= BIT_ZERO;
-				baud_counter <= CLOCKS_PER_BAUD+CLOCKS_PER_BAUD/2-1'b1;
-			end
-		end
+    always @(posedge i_clk)
+        if (state == IDLE) begin
+            state <= IDLE;
+            baud_counter <= 0;
+            if (!ck_uart) begin
+                state <= BIT_ZERO;
+                baud_counter <= CLOCKS_PER_BAUD+CLOCKS_PER_BAUD/2-1'b1;
+            end
+        end
 
-		else if (zero_baud_counter) begin
-			state <= state + 1;
-			baud_counter <= CLOCKS_PER_BAUD-1'b1;
-			if (state == STOP_BIT) begin
-				state <= IDLE;
-				baud_counter <= 0;
-			end
-		end
+        else if (zero_baud_counter) begin
+            state <= state + 1;
+            baud_counter <= CLOCKS_PER_BAUD-1'b1;
+            if (state == STOP_BIT) begin
+                state <= IDLE;
+                baud_counter <= 0;
+            end
+        end
 
-		else baud_counter <= baud_counter - 1'b1;
+        else baud_counter <= baud_counter - 1'b1;
 
-	always @(*)
-		zero_baud_counter = (baud_counter == 0);
+    always @(*)
+        zero_baud_counter = (baud_counter == 0);
 
-	always @(posedge i_clk)
-	if ((zero_baud_counter)&&(state != STOP_BIT))
-		o_data <= { ck_uart, o_data[7:1] };
+    always @(posedge i_clk)
+    if ((zero_baud_counter)&&(state != STOP_BIT))
+        o_data <= { ck_uart, o_data[7:1] };
 
-	initial	o_wr = 1'b0;
-	always @(posedge i_clk)
-		o_wr <= ((zero_baud_counter)&&(state == STOP_BIT));
+    initial	o_wr = 1'b0;
+    always @(posedge i_clk)
+        o_wr <= ((zero_baud_counter)&&(state == STOP_BIT));
 
 endmodule
diff --git a/src/manta/sample_mem_tmpl.v b/src/manta/sample_mem_def_tmpl.v
similarity index 98%
rename from src/manta/sample_mem_tmpl.v
rename to src/manta/sample_mem_def_tmpl.v
index 89e2a7f..e76ea9b 100644
--- a/src/manta/sample_mem_tmpl.v
+++ b/src/manta/sample_mem_def_tmpl.v
@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module sample_mem(
+module sample_mem (
     input wire clk,
 
     // fifo
diff --git a/src/manta/trigger.v b/src/manta/trigger.v
index f9aed35..05939e1 100644
--- a/src/manta/trigger.v
+++ b/src/manta/trigger.v
@@ -1,15 +1,14 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module trigger(
+module trigger (
     input wire clk,
 
     input wire [INPUT_WIDTH-1:0] probe,
     input wire [3:0] op,
     input wire [INPUT_WIDTH-1:0] arg,
 
-    output reg trig
-    );
+    output reg trig);
 
     parameter INPUT_WIDTH = 0;
 
diff --git a/src/manta/trigger_block_template.v b/src/manta/trigger_block_def_tmpl.v
similarity index 100%
rename from src/manta/trigger_block_template.v
rename to src/manta/trigger_block_def_tmpl.v
diff --git a/src/manta/trigger_block_inst_tmpl.v b/src/manta/trigger_block_inst_tmpl.v
index 38e9487..f796fa2 100644
--- a/src/manta/trigger_block_inst_tmpl.v
+++ b/src/manta/trigger_block_inst_tmpl.v
@@ -8,5 +8,4 @@ trigger #(.INPUT_WIDTH(/* INPUT_WIDTH */)) /* NAME */ (
     .probe(/* PROBE */),
     .op(/* OP */),
     .arg(/* ARG */),
-    .trig(/* TRIG */)
-);
+    .trig(/* TRIG */));
diff --git a/src/manta/tx_uart.v b/src/manta/tx_uart.v
index f24b9e6..38ec6b2 100644
--- a/src/manta/tx_uart.v
+++ b/src/manta/tx_uart.v
@@ -35,146 +35,146 @@
 ////////////////////////////////////////////////////////////////////////////////
 //
 //
-`default_nettype	none
+`default_nettype none
 //
 //
 //
 module tx_uart(
-	input wire i_clk,
-	input wire i_wr,
-	input wire [7:0] i_data,
-	output reg o_uart_tx,
-	output reg o_busy);
+    input wire i_clk,
+    input wire i_wr,
+    input wire [7:0] i_data,
+    output reg o_uart_tx,
+    output reg o_busy);
 
-	parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
+    parameter	[23:0]	CLOCKS_PER_BAUD = 24'd868;
 
-	// A line to tell others when we are ready to accept data.  If
-	// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
-	// for transmission.
+    // A line to tell others when we are ready to accept data.  If
+    // (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
+    // for transmission.
 
-	// Define several states
-	localparam [3:0] START	= 4'h0,
-		BIT_ZERO	= 4'h1,
-		BIT_ONE		= 4'h2,
-		BIT_TWO		= 4'h3,
-		BIT_THREE	= 4'h4,
-		BIT_FOUR	= 4'h5,
-		BIT_FIVE	= 4'h6,
-		BIT_SIX		= 4'h7,
-		BIT_SEVEN	= 4'h8,
-		LAST		= 4'h8,
-		IDLE		= 4'hf;
+    // Define several states
+    localparam [3:0] START	= 4'h0,
+        BIT_ZERO	= 4'h1,
+        BIT_ONE		= 4'h2,
+        BIT_TWO		= 4'h3,
+        BIT_THREE	= 4'h4,
+        BIT_FOUR	= 4'h5,
+        BIT_FIVE	= 4'h6,
+        BIT_SIX		= 4'h7,
+        BIT_SEVEN	= 4'h8,
+        LAST		= 4'h8,
+        IDLE		= 4'hf;
 
-	reg	[23:0]	counter;
-	reg	[3:0]	state;
-	reg	[8:0]	lcl_data;
-	reg		baud_stb;
+    reg	[23:0]	counter;
+    reg	[3:0]	state;
+    reg	[8:0]	lcl_data;
+    reg		baud_stb;
 
-	// o_busy
-	//
-	// This is a register, designed to be true is we are ever busy above.
-	// originally, this was going to be true if we were ever not in the
-	// idle state.  The logic has since become more complex, hence we have
-	// a register dedicated to this and just copy out that registers value.
+    // o_busy
+    //
+    // This is a register, designed to be true is we are ever busy above.
+    // originally, this was going to be true if we were ever not in the
+    // idle state.  The logic has since become more complex, hence we have
+    // a register dedicated to this and just copy out that registers value.
 
-	initial	o_busy = 1'b0;
-	initial	state  = IDLE;
-	always @(posedge i_clk)
-	if ((i_wr)&&(!o_busy))
-		// Immediately start us off with a start bit
-		{ o_busy, state } <= { 1'b1, START };
-	else if (baud_stb)
-	begin
-		if (state == IDLE) // Stay in IDLE
-			{ o_busy, state } <= { 1'b0, IDLE };
-		else if (state < LAST) begin
-			o_busy <= 1'b1;
-			state <= state + 1'b1;
-		end else // Wait for IDLE
-			{ o_busy, state } <= { 1'b1, IDLE };
-	end
+    initial	o_busy = 1'b0;
+    initial	state  = IDLE;
+    always @(posedge i_clk)
+    if ((i_wr)&&(!o_busy))
+        // Immediately start us off with a start bit
+        { o_busy, state } <= { 1'b1, START };
+    else if (baud_stb)
+    begin
+        if (state == IDLE) // Stay in IDLE
+            { o_busy, state } <= { 1'b0, IDLE };
+        else if (state < LAST) begin
+            o_busy <= 1'b1;
+            state <= state + 1'b1;
+        end else // Wait for IDLE
+            { o_busy, state } <= { 1'b1, IDLE };
+    end
 
 
 
-	// lcl_data
-	//
-	// This is our working copy of the i_data register which we use
-	// when transmitting.  It is only of interest during transmit, and is
-	// allowed to be whatever at any other time.  Hence, if o_busy isn't
-	// true, we can always set it.  On the one clock where o_busy isn't
-	// true and i_wr is, we set it and o_busy is true thereafter.
-	// Then, on any baud_stb (i.e. change between baud intervals)
-	// we simple logically shift the register right to grab the next bit.
-	initial	lcl_data = 9'h1ff;
-	always @(posedge i_clk)
-	if ((i_wr)&&(!o_busy))
-		lcl_data <= { i_data, 1'b0 };
-	else if (baud_stb)
-		lcl_data <= { 1'b1, lcl_data[8:1] };
+    // lcl_data
+    //
+    // This is our working copy of the i_data register which we use
+    // when transmitting.  It is only of interest during transmit, and is
+    // allowed to be whatever at any other time.  Hence, if o_busy isn't
+    // true, we can always set it.  On the one clock where o_busy isn't
+    // true and i_wr is, we set it and o_busy is true thereafter.
+    // Then, on any baud_stb (i.e. change between baud intervals)
+    // we simple logically shift the register right to grab the next bit.
+    initial	lcl_data = 9'h1ff;
+    always @(posedge i_clk)
+    if ((i_wr)&&(!o_busy))
+        lcl_data <= { i_data, 1'b0 };
+    else if (baud_stb)
+        lcl_data <= { 1'b1, lcl_data[8:1] };
 
-	// o_uart_tx
-	//
-	// This is the final result/output desired of this core.  It's all
-	// centered about o_uart_tx.  This is what finally needs to follow
-	// the UART protocol.
-	//
-	assign	o_uart_tx = lcl_data[0];
+    // o_uart_tx
+    //
+    // This is the final result/output desired of this core.  It's all
+    // centered about o_uart_tx.  This is what finally needs to follow
+    // the UART protocol.
+    //
+    assign	o_uart_tx = lcl_data[0];
 
 
-	// All of the above logic is driven by the baud counter.  Bits must last
-	// CLOCKS_PER_BAUD in length, and this baud counter is what we use to
-	// make certain of that.
-	//
-	// The basic logic is this: at the beginning of a bit interval, start
-	// the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
-	// to zero, restart it.
-	//
-	// However, comparing a 28'bit number to zero can be rather complex--
-	// especially if we wish to do anything else on that same clock.  For
-	// that reason, we create "baud_stb".  baud_stb is
-	// nothing more than a flag that is true anytime baud_counter is zero.
-	// It's true when the logic (above) needs to step to the next bit.
-	// Simple enough?
-	//
-	// I wish we could stop there, but there are some other (ugly)
-	// conditions to deal with that offer exceptions to this basic logic.
-	//
-	// 1. When the user has commanded a BREAK across the line, we need to
-	// wait several baud intervals following the break before we start
-	// transmitting, to give any receiver a chance to recognize that we are
-	// out of the break condition, and to know that the next bit will be
-	// a stop bit.
-	//
-	// 2. A reset is similar to a break condition--on both we wait several
-	// baud intervals before allowing a start bit.
-	//
-	// 3. In the idle state, we stop our counter--so that upon a request
-	// to transmit when idle we can start transmitting immediately, rather
-	// than waiting for the end of the next (fictitious and arbitrary) baud
-	// interval.
-	//
-	// When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
-	// the idle state, but we also just accepted a command to start writing
-	// the next word.  At this point, the baud counter needs to be reset
-	// to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
-	//
-	// The logic is a bit twisted here, in that it will only check for the
-	// above condition when baud_stb is false--so as to make
-	// certain the STOP bit is complete.
-	initial	baud_stb = 1'b1;
-	initial	counter = 0;
-	always @(posedge i_clk)
-	if ((i_wr)&&(!o_busy))
-	begin
-		counter  <= CLOCKS_PER_BAUD - 1'b1;
-		baud_stb <= 1'b0;
-	end else if (!baud_stb)
-	begin
-		baud_stb <= (counter == 24'h01);
-		counter  <= counter - 1'b1;
-	end else if (state != IDLE)
-	begin
-		counter <= CLOCKS_PER_BAUD - 1'b1;
-		baud_stb <= 1'b0;
-	end
+    // All of the above logic is driven by the baud counter.  Bits must last
+    // CLOCKS_PER_BAUD in length, and this baud counter is what we use to
+    // make certain of that.
+    //
+    // The basic logic is this: at the beginning of a bit interval, start
+    // the baud counter and set it to count CLOCKS_PER_BAUD.  When it gets
+    // to zero, restart it.
+    //
+    // However, comparing a 28'bit number to zero can be rather complex--
+    // especially if we wish to do anything else on that same clock.  For
+    // that reason, we create "baud_stb".  baud_stb is
+    // nothing more than a flag that is true anytime baud_counter is zero.
+    // It's true when the logic (above) needs to step to the next bit.
+    // Simple enough?
+    //
+    // I wish we could stop there, but there are some other (ugly)
+    // conditions to deal with that offer exceptions to this basic logic.
+    //
+    // 1. When the user has commanded a BREAK across the line, we need to
+    // wait several baud intervals following the break before we start
+    // transmitting, to give any receiver a chance to recognize that we are
+    // out of the break condition, and to know that the next bit will be
+    // a stop bit.
+    //
+    // 2. A reset is similar to a break condition--on both we wait several
+    // baud intervals before allowing a start bit.
+    //
+    // 3. In the idle state, we stop our counter--so that upon a request
+    // to transmit when idle we can start transmitting immediately, rather
+    // than waiting for the end of the next (fictitious and arbitrary) baud
+    // interval.
+    //
+    // When (i_wr)&&(!o_busy)&&(state == IDLE) then we're not only in
+    // the idle state, but we also just accepted a command to start writing
+    // the next word.  At this point, the baud counter needs to be reset
+    // to the number of CLOCKS_PER_BAUD, and baud_stb set to zero.
+    //
+    // The logic is a bit twisted here, in that it will only check for the
+    // above condition when baud_stb is false--so as to make
+    // certain the STOP bit is complete.
+    initial	baud_stb = 1'b1;
+    initial	counter = 0;
+    always @(posedge i_clk)
+    if ((i_wr)&&(!o_busy))
+    begin
+        counter  <= CLOCKS_PER_BAUD - 1'b1;
+        baud_stb <= 1'b0;
+    end else if (!baud_stb)
+    begin
+        baud_stb <= (counter == 24'h01);
+        counter  <= counter - 1'b1;
+    end else if (state != IDLE)
+    begin
+        counter <= CLOCKS_PER_BAUD - 1'b1;
+        baud_stb <= 1'b0;
+    end
 endmodule
diff --git a/src/manta/uart_rx_bridge_rx_inst_templ.v b/src/manta/uart_rx_bridge_rx_inst_templ.v
index 610930b..52d3f04 100644
--- a/src/manta/uart_rx_bridge_rx_inst_templ.v
+++ b/src/manta/uart_rx_bridge_rx_inst_templ.v
@@ -1,8 +1,8 @@
 rx_uart #(.CLOCKS_PER_BAUD(/* CLOCKS_PER_BAUD */)) urx (
-        .i_clk(clk),
-        .i_uart_rx(rx),
-        .o_wr(urx_brx_axiv),
-        .o_data(urx_brx_axid));
+    .i_clk(clk),
+    .i_uart_rx(rx),
+    .o_wr(urx_brx_axiv),
+    .o_data(urx_brx_axid));
 
 logic [7:0] urx_brx_axid;
 logic urx_brx_axiv;
diff --git a/src/manta/uart_tx.v b/src/manta/uart_tx.v
index 52a8fa1..47d7286 100644
--- a/src/manta/uart_tx.v
+++ b/src/manta/uart_tx.v
@@ -1,7 +1,7 @@
 `default_nettype none
 `timescale 1ns/1ps
 
-module uart_tx(
+module uart_tx (
 	input wire clk,
 
 	input wire [7:0] data,
@@ -67,9 +67,6 @@ module uart_tx(
 			end
 		end
 	end
-
-
-
 endmodule
 
-`default_nettype wire
+`default_nettype wire
\ No newline at end of file
diff --git a/src/manta/bit_fifo.v b/test/functional_sim/bit_fifo_tb/bit_fifo.v
similarity index 100%
rename from src/manta/bit_fifo.v
rename to test/functional_sim/bit_fifo_tb/bit_fifo.v
diff --git a/test/functional_sim/bit_fifo_tb.sv b/test/functional_sim/bit_fifo_tb/bit_fifo_tb.sv
similarity index 100%
rename from test/functional_sim/bit_fifo_tb.sv
rename to test/functional_sim/bit_fifo_tb/bit_fifo_tb.sv
diff --git a/src/manta/io_core.v b/test/functional_sim/io_core_tb/io_core.v
similarity index 100%
rename from src/manta/io_core.v
rename to test/functional_sim/io_core_tb/io_core.v
diff --git a/test/functional_sim/io_core_tb.sv b/test/functional_sim/io_core_tb/io_core_tb.sv
similarity index 100%
rename from test/functional_sim/io_core_tb.sv
rename to test/functional_sim/io_core_tb/io_core_tb.sv
diff --git a/src/manta/logic_analyzer.v b/test/functional_sim/logic_analyzer_tb/logic_analyzer.v
similarity index 100%
rename from src/manta/logic_analyzer.v
rename to test/functional_sim/logic_analyzer_tb/logic_analyzer.v
diff --git a/test/functional_sim/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
similarity index 100%
rename from test/functional_sim/logic_analyzer_tb.sv
rename to test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
diff --git a/src/manta/sample_mem.v b/test/functional_sim/logic_analyzer_tb/sample_mem.v
similarity index 100%
rename from src/manta/sample_mem.v
rename to test/functional_sim/logic_analyzer_tb/sample_mem.v
diff --git a/src/manta/trigger_block.v b/test/functional_sim/logic_analyzer_tb/trigger_block.v
similarity index 100%
rename from src/manta/trigger_block.v
rename to test/functional_sim/logic_analyzer_tb/trigger_block.v