From 3482e8eee034c6c3aaeffb4c88866cb329714696 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
Parameters:
phy
+ phy
(str)
–
clk_freq
+ clk_freq
(int | float)
–
fpga_ip_addr
+ fpga_ip_addr
(str)
–
host_ip_addr
+ host_ip_addr
(str)
–
udp_port
+ udp_port
(Optional[int], default:
2001
)
@@ -946,7 +946,7 @@ FPGA will send packets back to.
**kwargs
+ **kwargs
–
Any additional keyword arguments to this function will @@ -984,6 +984,11 @@ provided below:
+ + + + +Parameters:
inputs
+ inputs
(Optional[List[Signal]], default:
[]
)
@@ -1003,7 +1003,7 @@ at least one probe, but it need not be an input.
outputs
+ outputs
(Optional[List[Signal]], default:
[]
)
@@ -1020,6 +1020,11 @@ at least one probe, but it need not be an output.
+
+
+
+
+
Parameters:
probe
+ probe
(str | Signal)
–
Parameters:
probe
+ probe
(str | Signal)
–
value
+ value
(int)
–
Parameters:
sample_depth
+ sample_depth
(int)
–
probes
+ probes
(List[Signal])
–
Parameters:
trigger_mode
+ trigger_mode
(TriggerMode | str, default:
None
)
@@ -1406,7 +1411,7 @@ containing the capture and its metadata.
triggers
+ triggers
(Optional[Sequence[Sequence[str | int]]], default:
None
)
@@ -1416,7 +1421,7 @@ containing the capture and its metadata.
trigger_location
+ trigger_location
(Optional[int], default:
None
)
@@ -1461,6 +1466,11 @@ CSV file, or a Verilog module.
+
+
+
+
+
Parameters:
path
+ path
(str)
–
Parameters:
path
+ path
(str)
–
Parameters:
name
+ name
(str)
–
Parameters:
mode
+ mode
(str)
–
width
+ width
(int)
–
depth
+ depth
(int)
–
Parameters:
addrs
+ addrs
(int | List[int])
–
Parameters:
addrs
+ addrs
(int | List[int])
–
datas
+ datas
(int | List[int])
–
Parameters:
port
+ port
(str)
–
baudrate
+ baudrate
(float | int)
–
clock_freq
+ clock_freq
(float | int)
–
stall_interval
+ stall_interval
(Optional[int], default:
16
)
@@ -927,7 +927,7 @@ reports that bytes are being dropped.
chunk_size
+ chunk_size
(Optional[int], default:
256
)
@@ -959,6 +959,11 @@ provided, or the clock frequency or baudrate is invalid.
+
+
+
+
+