From 24ee956d6cda395f138357d61fad971c60669ff9 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Fri, 9 Feb 2024 18:58:02 -0800 Subject: [PATCH] add liteeth wrapper --- project_0/build.tcl | 65 -- project_0/manta.yaml | 23 - project_0/manta_test.yaml | 12 - project_0/stream.py | 68 -- project_0/test.yml | 28 - project_0/xdc/top_level.xdc | 260 -------- project_1/build.tcl | 65 -- project_1/liteeth_config.yml | 28 - project_1/manta.yaml | 27 - project_1/stream.py | 40 -- project_1/test.py | 5 - project_1/xdc/top_level.xdc | 260 -------- pyproject.toml | 1 + src/manta/cli.py | 11 +- .../{ethernet.py => ethernet/__init__.py} | 101 ++- src/manta/ethernet/liteeth_gen.py | 611 ++++++++++++++++++ src/manta/ethernet/sink_bridge.py | 26 + src/manta/ethernet/source_bridge.py | 37 ++ src/manta/manta.py | 22 + 19 files changed, 741 insertions(+), 949 deletions(-) delete mode 100644 project_0/build.tcl delete mode 100644 project_0/manta.yaml delete mode 100644 project_0/manta_test.yaml delete mode 100644 project_0/stream.py delete mode 100644 project_0/test.yml delete mode 100644 project_0/xdc/top_level.xdc delete mode 100644 project_1/build.tcl delete mode 100644 project_1/liteeth_config.yml delete mode 100644 project_1/manta.yaml delete mode 100644 project_1/stream.py delete mode 100644 project_1/test.py delete mode 100644 project_1/xdc/top_level.xdc rename src/manta/{ethernet.py => ethernet/__init__.py} (79%) create mode 100755 src/manta/ethernet/liteeth_gen.py create mode 100644 src/manta/ethernet/sink_bridge.py create mode 100644 src/manta/ethernet/source_bridge.py diff --git a/project_0/build.tcl b/project_0/build.tcl deleted file mode 100644 index d0441d6..0000000 --- a/project_0/build.tcl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/tclsh -# jay's build script -# pass -tclargs -d to generate diagnostics - -# switches - -set partNum xc7a100tcsg324-1 -set outputDir output_files -set verbose 0 - -if { $argc > 0 } { - if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } { - set verbose 1 - } else { - puts "usage: $argv0 \[-d\]" - exit 1 - } -} - -file mkdir $outputDir -set files [glob -nocomplain "$outputDir/*"] -if {[llength $files] != 0} { - file delete -force {*}[glob -directory $outputDir *]; -} - -read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] -read_xdc ./xdc/top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -if { $verbose } { - report_timing_summary -file $outputDir/post_synth_timing_summary.rpt - report_timing -file $outputDir/post_synth_timing.rpt -} - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -if { $verbose } { - report_clock_utilization -file $outputDir/clock_util.rpt - report_timing_summary -file $outputDir/post_place_timing_summary.rpt - report_timing -file $outputDir/post_place_timing.rpt -} - -# route design and generate bitstream - -route_design -directive Explore -write_bitstream -force $outputDir/final.bit - -if { $verbose } { - report_route_status -file $outputDir/post_route_status.rpt - report_timing_summary -file $outputDir/post_route_timing_summary.rpt - report_timing -file $outputDir/post_route_timing.rpt - report_power -file $outputDir/post_route_power.rpt - report_drc -file $outputDir/post_imp_drc.rpt - write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true - # unfortunately, does nothing - show_schematic [ get_cells ] -} \ No newline at end of file diff --git a/project_0/manta.yaml b/project_0/manta.yaml deleted file mode 100644 index 4fd772f..0000000 --- a/project_0/manta.yaml +++ /dev/null @@ -1,23 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - dhcp_done: 1 - dhcp_ip_address: 32 - dhcp_timeout: 1 - led: 16 - - outputs: - dhcp_start: 1 - ip_address: 32 - udp_port: 16 - udp0_ip_address: 32 - udp0_sink_data: 32 - udp0_sink_valid: 1 - -uart: - port: "/dev/ttyUSB1" - baudrate: 115200 - clock_freq: 50000000 diff --git a/project_0/manta_test.yaml b/project_0/manta_test.yaml deleted file mode 100644 index a7a83c4..0000000 --- a/project_0/manta_test.yaml +++ /dev/null @@ -1,12 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - foobar: 1 - - -ethernet: - desired_fpga_ip: "192.168.0.110" - host_ip: "192.168.0.100" diff --git a/project_0/stream.py b/project_0/stream.py deleted file mode 100644 index 82a17c8..0000000 --- a/project_0/stream.py +++ /dev/null @@ -1,68 +0,0 @@ -from manta import Manta -import socket -import time - - -def configure(ip_address, udp_port): - m = Manta("manta.yaml") - - # Compute IP address - octets = [bin(int(o))[2:].zfill(8) for o in ip_address.split(".")] - ip_binary = int("".join(octets), 2) - - # Set IP address - m.io_core.set_probe("ip_address", ip_binary) - m.io_core.set_probe("dhcp_start", 1) - m.io_core.set_probe("dhcp_start", 0) - while m.io_core.get_probe("dhcp_done") != 1: - pass - print(m.io_core.get_probe("dhcp_ip_address")) - - # Set UDP port - m.io_core.set_probe("udp_port", udp_port) - - -def leds_test(ip_address, udp_port): - m = Manta("manta.yaml") - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - for i in range(0xFF): - sock.sendto(int(i).to_bytes(1, byteorder="big"), (ip_address, udp_port)) - led = m.io_core.get_probe("led") - print(f"i:{i} led:{led}") - time.sleep(0.2) - - -def send_variable_length_test(): - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - for i in range(0xFF): - sock.sendto(int(i).to_bytes(i, byteorder="big"), (ip_address, udp_port)) - time.sleep(0.2) - - -def send_to_host_test(host_ip, udp_port): - m = Manta("manta.yaml") - - # Set UDP port - m.io_core.set_probe("udp_port", udp_port) - - # Compute and set destination IP address: - octets = [bin(int(o))[2:].zfill(8) for o in host_ip.split(".")] - ip_binary = int("".join(octets), 2) - m.io_core.set_probe("udp0_ip_address", ip_binary) - - # Send data - m.io_core.set_probe("udp0_sink_data", 0x21_43_65_87) - m.io_core.set_probe("udp0_sink_valid", 1) - m.io_core.set_probe("udp0_sink_valid", 0) - - -if __name__ == "__main__": - ip_address = "192.168.0.110" - udp_port = 42069 - - configure(ip_address, udp_port) - # time.sleep(0.2) - # for _ in range(64): - # send_to_host_test("192.168.0.107", 42069) - # leds_test(ip_address, udp_port) - # send_variable_length_test() diff --git a/project_0/test.yml b/project_0/test.yml deleted file mode 100644 index 666a399..0000000 --- a/project_0/test.yml +++ /dev/null @@ -1,28 +0,0 @@ -# -# This file is part of LiteEth. -# -# Copyright (c) 2020-2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -# PHY -------------------------------------------------------------------------- -phy: LiteEthPHYRMII -vendor: xilinx -toolchain: vivado - -# Core ------------------------------------------------------------------------- -refclk_freq: 50e6 -clk_freq: 50e6 -core: udp -mac_address: 0x10e2d5000000 -dhcp: True -data_width: 8 - -# UDP Ports -------------------------------------------------------------------- -udp_ports: { - "udp0": { - "udp_port" : 2000, # Static Params. - "data_width" : 32, - "tx_fifo_depth" : 64, - "rx_fifo_depth" : 64, - }, -} diff --git a/project_0/xdc/top_level.xdc b/project_0/xdc/top_level.xdc deleted file mode 100644 index 7a77074..0000000 --- a/project_0/xdc/top_level.xdc +++ /dev/null @@ -1,260 +0,0 @@ -## R1.0 2019-08-27 -## Updated by jodalyst in 2020-2022 -## all inputs/outputs changed to lowercase; arrays start with zero. -## system clock renamed to clk_100mhz -## ja, jb, jc, jd renamed to 0-7 -## xa port renamed 0-3 -## seven segments renamed to a,b,c,d,e,f,dp - -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - diff --git a/project_1/build.tcl b/project_1/build.tcl deleted file mode 100644 index d0441d6..0000000 --- a/project_1/build.tcl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/tclsh -# jay's build script -# pass -tclargs -d to generate diagnostics - -# switches - -set partNum xc7a100tcsg324-1 -set outputDir output_files -set verbose 0 - -if { $argc > 0 } { - if { $argc == 1 && [string compare [ lindex $argv 0 ] "-d"] == 0 } { - set verbose 1 - } else { - puts "usage: $argv0 \[-d\]" - exit 1 - } -} - -file mkdir $outputDir -set files [glob -nocomplain "$outputDir/*"] -if {[llength $files] != 0} { - file delete -force {*}[glob -directory $outputDir *]; -} - -read_verilog -sv [ glob ./src/*.{sv,v,svh,vh} ] -read_xdc ./xdc/top_level.xdc - -set_part $partNum - -# synth -synth_design -top top_level -part $partNum -verbose -report_utilization -file $outputDir/post_synth_util.rpt -if { $verbose } { - report_timing_summary -file $outputDir/post_synth_timing_summary.rpt - report_timing -file $outputDir/post_synth_timing.rpt -} - -# place -opt_design -place_design -phys_opt_design -report_utilization -file $outputDir/post_place_util.rpt - -if { $verbose } { - report_clock_utilization -file $outputDir/clock_util.rpt - report_timing_summary -file $outputDir/post_place_timing_summary.rpt - report_timing -file $outputDir/post_place_timing.rpt -} - -# route design and generate bitstream - -route_design -directive Explore -write_bitstream -force $outputDir/final.bit - -if { $verbose } { - report_route_status -file $outputDir/post_route_status.rpt - report_timing_summary -file $outputDir/post_route_timing_summary.rpt - report_timing -file $outputDir/post_route_timing.rpt - report_power -file $outputDir/post_route_power.rpt - report_drc -file $outputDir/post_imp_drc.rpt - write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true - # unfortunately, does nothing - show_schematic [ get_cells ] -} \ No newline at end of file diff --git a/project_1/liteeth_config.yml b/project_1/liteeth_config.yml deleted file mode 100644 index 666a399..0000000 --- a/project_1/liteeth_config.yml +++ /dev/null @@ -1,28 +0,0 @@ -# -# This file is part of LiteEth. -# -# Copyright (c) 2020-2022 Florent Kermarrec -# SPDX-License-Identifier: BSD-2-Clause - -# PHY -------------------------------------------------------------------------- -phy: LiteEthPHYRMII -vendor: xilinx -toolchain: vivado - -# Core ------------------------------------------------------------------------- -refclk_freq: 50e6 -clk_freq: 50e6 -core: udp -mac_address: 0x10e2d5000000 -dhcp: True -data_width: 8 - -# UDP Ports -------------------------------------------------------------------- -udp_ports: { - "udp0": { - "udp_port" : 2000, # Static Params. - "data_width" : 32, - "tx_fifo_depth" : 64, - "rx_fifo_depth" : 64, - }, -} diff --git a/project_1/manta.yaml b/project_1/manta.yaml deleted file mode 100644 index 23f7b6d..0000000 --- a/project_1/manta.yaml +++ /dev/null @@ -1,27 +0,0 @@ ---- -cores: - io_core: - type: io - - inputs: - sw: 16 - - outputs: - led: 16 - -ethernet: - phy: LiteEthPHYRMII - vendor: xilinx - toolchain: vivado - - refclk_freq: 50e6 - clk_freq: 50e6 - - fpga_ip_addr: "192.168.0.110" - host_ip_addr: "192.168.0.100" - udp_port: 42069 - - core: udp # we handle this - mac_address: # this should be optional - dhcp: # should be optional, default to true? - data_width: 32 # using DHCP will force this to 32, but for ease of use we should design for that even for static IP devices diff --git a/project_1/stream.py b/project_1/stream.py deleted file mode 100644 index ae56e49..0000000 --- a/project_1/stream.py +++ /dev/null @@ -1,40 +0,0 @@ -import socket -def write(addrs, datas): - bytes_out = b"" - for addr, data in zip(addrs, datas): - bytes_out += int(1).to_bytes(4, byteorder="little") - bytes_out += int(addr).to_bytes(2, byteorder="little") - bytes_out += int(data).to_bytes(2, byteorder="little") - - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - sock.sendto(bytes_out, (fpga_ip_addr, udp_port)) - -def read(addrs): - bytes_out = b"" - for addr in addrs: - bytes_out += int(0).to_bytes(4, byteorder="little") - bytes_out += int(addr).to_bytes(2, byteorder="little") - bytes_out += int(0).to_bytes(2, byteorder="little") - - sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) - sock.bind((host_ip_addr, udp_port)) - sock.sendto(bytes_out, (fpga_ip_addr, udp_port)) - data, addr = sock.recvfrom(1024) - - return int.from_bytes(data, "little") - -if __name__ == "__main__": - host_ip_addr = "192.168.0.100" - fpga_ip_addr = "192.168.0.110" - udp_port = 42069 - - for i in range(2**16): - write([0x0000],[0x0000]) - write([0x0000],[0x0001]) - write([0x0000],[0x0000]) - write([0x0002],[i]) - # print(read([0x0002])) - # write([0x0002],[0b0101_0101_0101_0101]) - # write([0x0000],[0x0000]) - # write([0x0000],[0x0001]) - # write([0x0000],[0x0000]) diff --git a/project_1/test.py b/project_1/test.py deleted file mode 100644 index 3a725ad..0000000 --- a/project_1/test.py +++ /dev/null @@ -1,5 +0,0 @@ -from manta import Manta -m = Manta("manta.yaml") - -print(bin(m.io_core.get_probe("sw"))) -m.io_core.set_probe("led", 4) \ No newline at end of file diff --git a/project_1/xdc/top_level.xdc b/project_1/xdc/top_level.xdc deleted file mode 100644 index 7a77074..0000000 --- a/project_1/xdc/top_level.xdc +++ /dev/null @@ -1,260 +0,0 @@ -## R1.0 2019-08-27 -## Updated by jodalyst in 2020-2022 -## all inputs/outputs changed to lowercase; arrays start with zero. -## system clock renamed to clk_100mhz -## ja, jb, jc, jd renamed to 0-7 -## xa port renamed 0-3 -## seven segments renamed to a,b,c,d,e,f,dp - -## This file is a general .xdc for the Nexys4 DDR Rev. C -## To use it in a project: -## - uncomment the lines corresponding to used pins -## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project - -## Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }]; #IO_L12P_T1_MRCC_35 Sch=clk_100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_100mhz}]; - - -##Switches - -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] - - -## LEDs - -set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] - -#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { led16_b }]; #IO_L5P_T0_D06_14 Sch=led16_b -#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { led16_g }]; #IO_L10P_T1_D14_14 Sch=led16_g -#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led16_r }]; #IO_L11P_T1_SRCC_14 Sch=led16_r -#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led17_b }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b -#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { led17_g }]; #IO_0_14 Sch=led17_g -#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led17_r }]; #IO_L11N_T1_SRCC_14 Sch=led17_r - - -##7 segment display - -#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca }]; #IO_L24N_T3_A00_D16_14 Sch=ca -#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb }]; #IO_25_14 Sch=cb -#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc }]; #IO_25_15 Sch=cc -#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd }]; #IO_L17P_T2_A26_15 Sch=cd -#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; #IO_L13P_T2_MRCC_14 Sch=ce -#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf -#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg - -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp - -#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an[6] }]; #IO_L23P_T3_35 Sch=an[6] -#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] - - -##Buttons - -#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { cpu_resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn - -set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { btnc }]; #IO_L9P_T1_DQS_14 Sch=btnc -set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { btnu }]; #IO_L4N_T0_D05_14 Sch=btnu -set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { btnl }]; #IO_L12P_T1_MRCC_14 Sch=btnl -set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd - - -##Pmod Headers - - -##Pmod Header JA - -#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L20N_T3_A19_15 Sch=ja[1] -#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] -#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] -#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L18N_T2_A23_15 Sch=ja[4] -#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L16N_T2_A27_15 Sch=ja[7] -#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L16P_T2_A28_15 Sch=ja[8] -#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L22N_T3_A16_15 Sch=ja[9] -#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L22P_T3_A17_15 Sch=ja[10] - - -##Pmod Header JB - -#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] -#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] -#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] -#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] -#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] -#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] -#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_0_15 Sch=jb[9] -#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] - - -##Pmod Header JC - -#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L23N_T3_35 Sch=jc[1] -#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] -#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22N_T3_35 Sch=jc[3] -#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L19P_T3_35 Sch=jc[4] -#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L6P_T0_35 Sch=jc[7] -#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22P_T3_35 Sch=jc[8] -#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] -#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] - - -##Pmod Header JD - -#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] -#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L17P_T2_35 Sch=jd[2] -#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L17N_T2_35 Sch=jd[3] -#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L20N_T3_35 Sch=jd[4] -#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] -#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L20P_T3_35 Sch=jd[8] -#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] -#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] - - -##Pmod Header JXADC - -#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { xa_n[0] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] -#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { xa_p[0] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] -#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { xa_n[1] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] -#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { xa_p[1] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] -#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { xa_n[2] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { xa_p[2] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] -#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { xa_n[3] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] -#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { xa_p[3] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] - - -##VGA Connector - -#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { vga_r[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] -#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] -#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { vga_r[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] -#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { vga_r[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] -# -#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] -#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { vga_g[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] -#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] -#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { vga_g[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] -# -#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] -#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] -#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { vga_b[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] -#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { vga_b[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] - -#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { vga_hs }]; #IO_L4P_T0_15 Sch=vga_hs -#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vga_vs }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs - -##Micro SD Connector - -#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset -#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd -#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { sd_sck }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck -#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L16N_T2_35 Sch=sd_cmd -#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] -#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] -#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] -#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { sd_dat[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] - - -##Accelerometer - -#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { acl_miso }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso -#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { acl_mosi }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi -#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { acl_sclk }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk -#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { acl_csn }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn -#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { acl_int[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] -#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { acl_int[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] - - -##Temperature Sensor - -#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { tmp_scl }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl -#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { tmp_sda }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda -#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { tmp_int }]; #IO_L6N_T0_VREF_15 Sch=tmp_int -#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { tmp_ct }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct - -##Omnidirectional Microphone - -#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { m_clk }]; #IO_25_35 Sch=m_clk -#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { m_data }]; #IO_L24N_T3_35 Sch=m_data -#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { m_lrsel }]; #IO_0_35 Sch=m_lrsel - - -##PWM Audio Amplifier - -#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]; #IO_L4N_T0_15 Sch=aud_pwm -#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]; #IO_L6P_T0_15 Sch=aud_sd - - -##USB-RS232 Interface - -set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in -set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out -#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { uart_cts }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts -#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { uart_rts }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts - -##USB HID (PS/2) - -#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { ps2_clk }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk -#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ps2_data }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data - - -##SMSC Ethernet PHY - -set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc -set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio -set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn -set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { eth_crsdv }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv -set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr -set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] -set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] -set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { eth_txen }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen -set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] -set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] -set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_refclk }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk -set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { eth_intn }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn - - -##Quad SPI Flash - -#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] -#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] -#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] -#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_csn }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn - diff --git a/pyproject.toml b/pyproject.toml index 0b798de..b794d15 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -10,6 +10,7 @@ dependencies = [ "amaranth[builtin-yosys]", "PyYAML", "pyserial", + "liteeth@git+https://github.com/enjoy-digital/liteeth@2023.12", "pyvcd", ] diff --git a/src/manta/cli.py b/src/manta/cli.py index 610ec13..0d64bd5 100644 --- a/src/manta/cli.py +++ b/src/manta/cli.py @@ -71,17 +71,8 @@ def wrong_args(): def gen(config_path, output_path): m = Manta(config_path) - from amaranth.back import verilog - with open(output_path, "w") as f: - f.write( - verilog.convert( - m, - name="manta", - ports=m.get_top_level_ports(), - strip_internal_attrs=True, - ) - ) + f.write(m.generate_verilog()) def inst(config_path): diff --git a/src/manta/ethernet.py b/src/manta/ethernet/__init__.py similarity index 79% rename from src/manta/ethernet.py rename to src/manta/ethernet/__init__.py index 9f174fd..4b16ee8 100644 --- a/src/manta/ethernet.py +++ b/src/manta/ethernet/__init__.py @@ -1,10 +1,14 @@ from amaranth import * -from manta.utils import * +from ..utils import * +from .source_bridge import UDPSourceBridge +from .sink_bridge import UDPSinkBridge +from random import randint import socket class EthernetInterface(Elaboratable): def __init__(self, config): + self.config = config self.fpga_ip_addr = config["fpga_ip_addr"] self.host_ip_addr = config["host_ip_addr"] self.udp_port = config["udp_port"] @@ -54,10 +58,10 @@ class EthernetInterface(Elaboratable): def elaborate(self, platform): m = Module() - with m.If(self.dhcp_timer < 15): + with m.If(self.dhcp_timer < int(50e6)): m.d.sync += self.dhcp_timer.eq(self.dhcp_timer + 1) - m.d.sync += self.dhcp_start.eq(self.dhcp_timer == 14) + m.d.sync += self.dhcp_start.eq(self.dhcp_timer == (int(50e6) - 2)) m.submodules.liteeth = Instance( "liteeth_core", @@ -129,7 +133,7 @@ class EthernetInterface(Elaboratable): # Send read requests, and get responses sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) sock.bind((self.host_ip_addr, self.udp_port)) - chunk_size = 128 + chunk_size = 64 # 128 addr_chunks = split_into_chunks(addrs, chunk_size) datas = [] @@ -146,6 +150,9 @@ class EthernetInterface(Elaboratable): # Split into groups of four bytes datas += [int.from_bytes(d, "little") for d in split_into_chunks(data, 4)] + if len(datas) != len(addrs): + raise ValueError("Got less data than expected from FPGA.") + return datas def write(self, addrs, datas): @@ -184,61 +191,39 @@ class EthernetInterface(Elaboratable): sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM) sock.sendto(bytes_out, (self.fpga_ip_addr, self.udp_port)) + def generate_liteeth_core(self): + # Randomly assign a MAC address if one is not specified in the configuration. + # This will choose a MAC address in the Locally Administered, Administratively Assigned group. + # For more information, see: + # https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses -class UDPSourceBridge(Elaboratable): - def __init__(self): - self.bus_o = Signal(InternalBus()) + if "mac_address" not in self.config: + mac_address = list(f"{randint(0, (2**48) - 1):012x}") + mac_address[1] = "2" + mac_address = int("".join(mac_address), 16) - self.data_i = Signal(32) - self.last_i = Signal() - self.ready_o = Signal() - self.valid_i = Signal() + else: + mac_address = self.config["mac_address"] - def elaborate(self, platform): - m = Module() + liteeth_config = { + "phy": self.config["phy"], + "vendor": self.config["vendor"], + "toolchain": self.config["toolchain"], + "refclk_freq": self.config["refclk_freq"], + "clk_freq": self.config["clk_freq"], + "mac_address": mac_address, + "dhcp": True, + "data_width": 32, + "udp_ports": { + "udp0": { + "udp_port": self.udp_port, + "data_width": 32, + "tx_fifo_depth": 64, + "rx_fifo_depth": 64, + } + }, + } - state = Signal() # can either be 0, for read/write, or 1, for data - rw_buf = Signal().like(self.bus_o.rw) - - # Can always take more data - m.d.sync += self.ready_o.eq(1) - - m.d.sync += self.bus_o.eq(0) - with m.If(self.valid_i): - m.d.sync += state.eq(~state) - - with m.If(state == 0): - m.d.sync += rw_buf.eq(self.data_i) - - with m.Else(): - m.d.sync += self.bus_o.addr.eq(self.data_i[:16]) - m.d.sync += self.bus_o.data.eq(self.data_i[16:]) - m.d.sync += self.bus_o.rw.eq(rw_buf) - m.d.sync += self.bus_o.valid.eq(1) - m.d.sync += self.bus_o.last.eq(self.last_i) - - return m - - -class UDPSinkBridge(Elaboratable): - def __init__(self): - self.bus_i = Signal(InternalBus()) - - self.data_o = Signal(32) - self.last_o = Signal() - self.ready_i = Signal() - self.valid_o = Signal() - - def elaborate(self, platform): - m = Module() - - m.d.sync += self.data_o.eq(0) - m.d.sync += self.last_o.eq(0) - m.d.sync += self.valid_o.eq(0) - - with m.If( (self.bus_i.valid) & (~self.bus_i.rw)): - m.d.sync += self.data_o.eq(self.bus_i.data) - m.d.sync += self.last_o.eq(self.bus_i.last) - m.d.sync += self.valid_o.eq(1) - - return m + # Generate the core + from .liteeth_gen import main + return main(liteeth_config) diff --git a/src/manta/ethernet/liteeth_gen.py b/src/manta/ethernet/liteeth_gen.py new file mode 100755 index 0000000..e07481e --- /dev/null +++ b/src/manta/ethernet/liteeth_gen.py @@ -0,0 +1,611 @@ +# LiteEth Core Generator +# Modified from https://github.com/enjoy-digital/liteeth/blob/master/liteeth/gen.py + +# Unless otherwise noted, LiteEth is Copyright 2012-2022 / EnjoyDigital + +# Redistribution and use in source and binary forms, with or without modification, +# are permitted provided that the following conditions are met: + +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. + +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR +# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# Other authors retain ownership of their contributions. If a submission can +# reasonably be considered independently copyrightable, it's yours and we +# encourage you to claim it with appropriate copyright notices. This submission +# then falls under the "otherwise noted" category. All submissions are strongly +# encouraged to use the two-clause BSD license reproduced above. + +# Copyright (c) 2015-2023 Florent Kermarrec +# Copyright (c) 2020 Xiretza +# Copyright (c) 2020 Stefan Schrijvers +# Copyright (c) 2022 Victor Suarez Rovere +# Copyright (c) 2023 LumiGuide Fietsdetectie B.V. +# SPDX-License-Identifier: BSD-2-Clause + +from migen import * + +from litex.gen import * + +from litex.build.generic_platform import * +from litex.build.xilinx.platform import XilinxPlatform +from litex.build.lattice.platform import LatticePlatform + +from litex.soc.interconnect import wishbone +from litex.soc.interconnect import axi +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.integration.soc import SoCRegion + +from liteeth.common import * + +from liteeth import phy as liteeth_phys +from liteeth.mac import LiteEthMAC +from liteeth.core import LiteEthUDPIPCore +from liteeth.core.dhcp import LiteEthDHCP + +from liteeth.frontend.stream import LiteEthUDPStreamer +from liteeth.frontend.etherbone import LiteEthEtherbone + +from tempfile import TemporaryDirectory + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk / Rst + ("sys_clock", 0, Pins(1)), + ("sys_reset", 1, Pins(1)), + # IP/MAC Address. + ("mac_address", 0, Pins(48)), + ("ip_address", 0, Pins(32)), + # Interrupt + ("interrupt", 0, Pins(1)), + # DHCP. + ( + "dhcp", + 0, + Subsignal("start", Pins(1)), + Subsignal("done", Pins(1)), + Subsignal("timeout", Pins(1)), + Subsignal("ip_address", Pins(32)), + ), + # MII PHY Pads + ( + "mii_clocks", + 0, + Subsignal("tx", Pins(1)), + Subsignal("rx", Pins(1)), + ), + ( + "mii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("mdio", Pins(1)), + Subsignal("mdc", Pins(1)), + Subsignal("rx_dv", Pins(1)), + Subsignal("rx_er", Pins(1)), + Subsignal("rx_data", Pins(4)), + Subsignal("tx_en", Pins(1)), + Subsignal("tx_data", Pins(4)), + Subsignal("col", Pins(1)), + Subsignal("crs", Pins(1)), + ), + # RMII PHY Pads + ("rmii_clocks", 0, Subsignal("ref_clk", Pins(1))), + ( + "rmii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("rx_data", Pins(2)), + Subsignal("crs_dv", Pins(1)), + Subsignal("tx_en", Pins(1)), + Subsignal("tx_data", Pins(2)), + Subsignal("mdc", Pins(1)), + Subsignal("mdio", Pins(1)), + ), + # GMII PHY Pads + ( + "gmii_clocks", + 0, + Subsignal("tx", Pins(1)), + Subsignal("gtx", Pins(1)), + Subsignal("rx", Pins(1)), + ), + ( + "gmii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("int_n", Pins(1)), + Subsignal("mdio", Pins(1)), + Subsignal("mdc", Pins(1)), + Subsignal("rx_dv", Pins(1)), + Subsignal("rx_er", Pins(1)), + Subsignal("rx_data", Pins(8)), + Subsignal("tx_en", Pins(1)), + Subsignal("tx_er", Pins(1)), + Subsignal("tx_data", Pins(8)), + Subsignal("col", Pins(1)), + Subsignal("crs", Pins(1)), + ), + # RGMII PHY Pads + ("rgmii_clocks", 0, Subsignal("tx", Pins(1)), Subsignal("rx", Pins(1))), + ( + "rgmii", + 0, + Subsignal("rst_n", Pins(1)), + Subsignal("int_n", Pins(1)), + Subsignal("mdio", Pins(1)), + Subsignal("mdc", Pins(1)), + Subsignal("rx_ctl", Pins(1)), + Subsignal("rx_data", Pins(4)), + Subsignal("tx_ctl", Pins(1)), + Subsignal("tx_data", Pins(4)), + ), + # SGMII PHY Pads + ( + "sgmii", + 0, + Subsignal("refclk", Pins(1)), + Subsignal("rst", Pins(1)), + Subsignal("txp", Pins(1)), + Subsignal("txn", Pins(1)), + Subsignal("rxp", Pins(1)), + Subsignal("rxn", Pins(1)), + Subsignal("link_up", Pins(1)), + ), +] + + +def get_udp_port_ios(name, data_width, dynamic_params=False): + return [ + ( + f"{name}", + 0, + # Parameters. + *( + [ + Subsignal("udp_port", Pins(16)), + Subsignal("ip_address", Pins(32)), + ] + if dynamic_params + else [] + ), + # Sink. + Subsignal("sink_valid", Pins(1)), + Subsignal("sink_last", Pins(1)), + Subsignal("sink_ready", Pins(1)), + Subsignal("sink_data", Pins(data_width)), + # Source. + Subsignal("source_valid", Pins(1)), + Subsignal("source_last", Pins(1)), + Subsignal("source_ready", Pins(1)), + Subsignal("source_data", Pins(data_width)), + Subsignal("source_error", Pins(1)), + ), + ] + + +def get_udp_raw_port_ios(name, data_width): + return [ + ( + f"{name}", + 0, + # Sink. + Subsignal("sink_ip_address", Pins(32)), + Subsignal("sink_src_port", Pins(16)), + Subsignal("sink_dst_port", Pins(16)), + Subsignal("sink_valid", Pins(1)), + Subsignal("sink_length", Pins(16)), + Subsignal("sink_last", Pins(1)), + Subsignal("sink_ready", Pins(1)), + Subsignal("sink_data", Pins(data_width)), + Subsignal("sink_last_be", Pins(data_width // 8)), + # Source. + Subsignal("source_ip_address", Pins(32)), + Subsignal("source_src_port", Pins(16)), + Subsignal("source_dst_port", Pins(16)), + Subsignal("source_valid", Pins(1)), + Subsignal("source_length", Pins(16)), + Subsignal("source_last", Pins(1)), + Subsignal("source_ready", Pins(1)), + Subsignal("source_data", Pins(data_width)), + Subsignal("source_last_be", Pins(data_width // 8)), + Subsignal("source_error", Pins(1)), + ), + ] + + +# PHY Core ----------------------------------------------------------------------------------------- +class PHYCore(SoCMini): + SoCMini.csr_map = { + "ctrl": 0, + "ethphy": 1, + "ethmac": 2, + } + + def __init__(self, platform, core_config): + for deprecated in ("csr_map", "mem_map"): + if deprecated in core_config: + raise RuntimeWarning( + "Config option {!r} is now a sub-option of 'soc'".format(deprecated) + ) + + # SoC parameters --------------------------------------------------------------------------- + soc_args = {} + if "soc" in core_config: + soc_config = core_config["soc"] + + for arg in soc_config: + if arg in ("csr_map", "interrupt_map", "mem_map"): + getattr(self, arg).update(soc_config[arg]) + else: + soc_args[arg] = soc_config[arg] + + # SoCMini ---------------------------------------------------------------------------------- + SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args) + + # CRG -------------------------------------------------------------------------------------- + self.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset")) + + # PHY -------------------------------------------------------------------------------------- + phy = core_config["phy"] + # MII. + if phy in [liteeth_phys.LiteEthPHYMII]: + ethphy = phy( + clock_pads=platform.request("mii_clocks"), pads=platform.request("mii") + ) + # RMII. + elif phy in [liteeth_phys.LiteEthPHYRMII]: + ethphy = phy( + refclk_cd=None, + clock_pads=platform.request("rmii_clocks"), + pads=platform.request("rmii"), + ) + # GMII. + elif phy in [liteeth_phys.LiteEthPHYGMII]: + ethphy = phy( + clock_pads=platform.request("gmii_clocks"), + pads=platform.request("gmii"), + ) + # GMII / MII. + elif phy in [liteeth_phys.LiteEthPHYGMIIMII]: + ethphy = phy( + clock_pads=platform.request("gmii_clocks"), + pads=platform.request("gmii"), + clk_freq=self.clk_freq, + ) + # RGMII. + elif phy in [ + liteeth_phys.LiteEthS7PHYRGMII, + liteeth_phys.LiteEthECP5PHYRGMII, + ]: + ethphy = phy( + clock_pads=platform.request("rgmii_clocks"), + pads=platform.request("rgmii"), + tx_delay=core_config.get("phy_tx_delay", 2e-9), + rx_delay=core_config.get("phy_rx_delay", 2e-9), + with_hw_init_reset=False, + ) # FIXME: required since sys_clk = eth_rx_clk. + # SGMII. + elif phy in [ + liteeth_phys.A7_1000BASEX, + liteeth_phys.A7_2500BASEX, + liteeth_phys.K7_1000BASEX, + liteeth_phys.K7_2500BASEX, + liteeth_phys.KU_1000BASEX, + liteeth_phys.KU_2500BASEX, + liteeth_phys.USP_GTH_1000BASEX, + liteeth_phys.USP_GTH_2500BASEX, + liteeth_phys.USP_GTY_1000BASEX, + liteeth_phys.USP_GTY_2500BASEX, + ]: + ethphy_pads = platform.request("sgmii") + # Artix7. + if phy in [liteeth_phys.A7_1000BASEX, liteeth_phys.A7_2500BASEX]: + refclk_freq = core_config.get("refclk_freq", 0) + assert refclk_freq in [125e6, 156.25e6] + from liteeth.phy.a7_gtp import QPLLSettings, QPLL + + qpll_settings = QPLLSettings( + refclksel=0b001, + fbdiv=4, + fbdiv_45={125e6: 5, 156.25e6: 4}[refclk_freq], + refclk_div=1, + ) + qpll = QPLL(ethphy_pads.refclk, qpll_settings) + self.submodules += qpll + ethphy = phy( + qpll_channel=qpll.channels[0], + data_pads=ethphy_pads, + sys_clk_freq=self.clk_freq, + with_csr=False, + rx_polarity=core_config.get("phy_rx_polarity", 0), + tx_polarity=core_config.get("phy_tx_polarity", 0), + ) + # Other 7-Series/Ultrascale(+). + else: + ethphy = phy( + refclk_or_clk_pads=ethphy_pads.refclk, + data_pads=ethphy_pads, + sys_clk_freq=self.clk_freq, + refclk_freq=core_config.get("refclk_freq", 200e6), + with_csr=False, + rx_polarity=core_config.get("phy_rx_polarity", 0), + tx_polarity=core_config.get("phy_tx_polarity", 0), + ) + self.comb += [ + ethphy.reset.eq(ethphy_pads.rst), + ethphy_pads.link_up.eq(ethphy.link_up), + ] + else: + raise ValueError("Unsupported PHY") + self.ethphy = ethphy + + # Timing constaints. + # Generate timing constraints to ensure the "keep" attribute is properly set on the various + # clocks. This also adds the constraints to the generated .xdc that can then be "imported" + # in the project using the core. + eth_rx_clk = getattr(ethphy, "crg", ethphy).cd_eth_rx.clk + eth_tx_clk = getattr(ethphy, "crg", ethphy).cd_eth_tx.clk + from liteeth.phy.model import LiteEthPHYModel + + if not isinstance(ethphy, LiteEthPHYModel): + self.platform.add_period_constraint(eth_rx_clk, 1e9 / phy.rx_clk_freq) + self.platform.add_period_constraint(eth_tx_clk, 1e9 / phy.tx_clk_freq) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk + ) + + +# UDP Core ----------------------------------------------------------------------------------------- +class UDPCore(PHYCore): + def add_streamer_port(self, platform, name, port_cfg): + # Use default Data-Width of 8-bit when not specified. + data_width = port_cfg.get("data_width", 8) + + # Used dynamic UDP-Port/IP-Address when not specified. + dynamic_params = port_cfg.get("ip_address", None) is None + + # FIFO Depth. + tx_fifo_depth = port_cfg.get("tx_fifo_depth", 64) + rx_fifo_depth = port_cfg.get("rx_fifo_depth", 64) + + # Create/Add IOs. + # --------------- + platform.add_extension( + get_udp_port_ios(name, data_width=data_width, dynamic_params=dynamic_params) + ) + + port_ios = platform.request(name) + + if dynamic_params: + ip_address = port_ios.ip_address + udp_port = port_ios.udp_port + else: + ip_address = port_cfg.get("ip_address") + udp_port = port_cfg.get("udp_port") + + # Create UDPStreamer. + # ------------------- + udp_streamer = LiteEthUDPStreamer( + self.core.udp, + ip_address=ip_address, + udp_port=udp_port, + data_width=data_width, + tx_fifo_depth=tx_fifo_depth, + rx_fifo_depth=rx_fifo_depth, + ) + self.submodules += udp_streamer + + # Connect IOs. + # ------------ + # Connect UDP Sink IOs to UDP Steamer. + self.comb += [ + udp_streamer.sink.valid.eq(port_ios.sink_valid), + udp_streamer.sink.last.eq(port_ios.sink_last), + port_ios.sink_ready.eq(udp_streamer.sink.ready), + udp_streamer.sink.data.eq(port_ios.sink_data), + ] + + # Connect UDP Streamer to UDP Source IOs. + self.comb += [ + port_ios.source_valid.eq(udp_streamer.source.valid), + port_ios.source_last.eq(udp_streamer.source.last), + udp_streamer.source.ready.eq(port_ios.source_ready), + port_ios.source_data.eq(udp_streamer.source.data), + port_ios.source_error.eq(udp_streamer.source.error), + ] + + def add_raw_port(self, platform, name, port_cfg): + # Use default Data-Width of 8-bit when not specified. + data_width = port_cfg.get("data_width", 8) + + # Create/Add IOs. + # --------------- + platform.add_extension( + get_udp_raw_port_ios( + name, + data_width=data_width, + ) + ) + + port_ios = platform.request(name) + + raw_port = self.core.udp.crossbar.get_port( + port_ios.sink_dst_port, dw=data_width + ) + + # Connect IOs. + # ------------ + # Connect UDP Sink IOs to UDP. + self.comb += [ + raw_port.sink.valid.eq(port_ios.sink_valid), + raw_port.sink.last.eq(port_ios.sink_last), + raw_port.sink.dst_port.eq(port_ios.sink_dst_port), + raw_port.sink.src_port.eq(port_ios.sink_src_port), + raw_port.sink.ip_address.eq(port_ios.sink_ip_address), + raw_port.sink.length.eq(port_ios.sink_length), + port_ios.sink_ready.eq(raw_port.sink.ready), + raw_port.sink.data.eq(port_ios.sink_data), + raw_port.sink.last_be.eq(port_ios.sink_last_be), + ] + + # Connect UDP to UDP Source IOs. + self.comb += [ + port_ios.source_valid.eq(raw_port.source.valid), + port_ios.source_last.eq(raw_port.source.last), + port_ios.source_dst_port.eq(raw_port.source.dst_port), + port_ios.source_src_port.eq(raw_port.source.src_port), + port_ios.source_ip_address.eq(raw_port.source.ip_address), + port_ios.source_length.eq(raw_port.source.length), + raw_port.source.ready.eq(port_ios.source_ready), + port_ios.source_data.eq(raw_port.source.data), + port_ios.source_last_be.eq(raw_port.source.last_be), + port_ios.source_error.eq(raw_port.source.error), + ] + + def __init__(self, platform, core_config): + # Config ----------------------------------------------------------------------------------- + tx_cdc_depth = core_config.get("tx_cdc_depth", 32) + tx_cdc_buffered = core_config.get("tx_cdc_buffered", False) + rx_cdc_depth = core_config.get("rx_cdc_depth", 32) + rx_cdc_buffered = core_config.get("rx_cdc_buffered", False) + + # MAC Address. + mac_address = core_config.get("mac_address", None) + # Get MAC Address from IOs when not specified. + if mac_address is None: + mac_address = platform.request("mac_address") + + # IP Address. + dhcp = core_config.get("dhcp", False) + ip_address = core_config.get("ip_address", None) + # Get IP Address from IOs when not specified. + if ip_address is None: + ip_address = platform.request("ip_address") + else: + assert not dhcp + + # PHY -------------------------------------------------------------------------------------- + PHYCore.__init__(self, platform, core_config) + + # Core ------------------------------------------------------------------------------------- + data_width = core_config.get("data_width", 8) + self.core = LiteEthUDPIPCore( + self.ethphy, + mac_address=mac_address, + ip_address=ip_address, + clk_freq=core_config["clk_freq"], + dw=data_width, + with_sys_datapath=(data_width == 32), + tx_cdc_depth=tx_cdc_depth, + tx_cdc_buffered=tx_cdc_buffered, + rx_cdc_depth=rx_cdc_depth, + rx_cdc_buffered=rx_cdc_buffered, + ) + + # DHCP ------------------------------------------------------------------------------------- + + if dhcp: + dhcp_pads = platform.request("dhcp") + dhcp_port = self.core.udp.crossbar.get_port(68, dw=32, cd="sys") + if isinstance(mac_address, Signal): + dhcp_mac_address = mac_address + else: + dhcp_mac_address = Signal(48, reset=0x10E2D5000001) + self.dhcp = LiteEthDHCP(udp_port=dhcp_port, sys_clk_freq=self.sys_clk_freq) + self.comb += [ + self.dhcp.start.eq(dhcp_pads.start), + dhcp_pads.done.eq(self.dhcp.done), + dhcp_pads.timeout.eq(self.dhcp.timeout), + dhcp_pads.ip_address.eq(self.dhcp.ip_address), + ] + + # Etherbone -------------------------------------------------------------------------------- + + etherbone = core_config.get("etherbone", False) + etherbone_port = core_config.get("etherbone_port", 1234) + etherbone_buffer_depth = core_config.get("etherbone_buffer_depth", 16) + + if etherbone: + assert data_width == 32 + self.etherbone = LiteEthEtherbone( + udp=self.core.udp, + udp_port=etherbone_port, + buffer_depth=etherbone_buffer_depth, + cd="sys", + ) + axil_bus = axi.AXILiteInterface(address_width=32, data_width=32) + platform.add_extension(axil_bus.get_ios("mmap")) + self.submodules += axi.Wishbone2AXILite( + self.etherbone.wishbone.bus, axil_bus + ) + self.comb += axil_bus.connect_to_pads( + platform.request("mmap"), mode="master" + ) + + # UDP Ports -------------------------------------------------------------------------------- + for name, port_cfg in core_config["udp_ports"].items(): + # mode either `raw` or `stream`, default to streamer to be backwards compatible + mode = port_cfg.get("mode", "streamer") + assert mode == "raw" or mode == "streamer" + + if mode == "streamer": + self.add_streamer_port(platform, name, port_cfg) + elif mode == "raw": + self.add_raw_port(platform, name, port_cfg) + + +# Build -------------------------------------------------------------------------------------------- +def main(core_config): + # Convert YAML elements to Python/LiteX -------------------------------------------------------- + for k, v in core_config.items(): + replaces = {"False": False, "True": True, "None": None} + for r in replaces.keys(): + if v == r: + core_config[k] = replaces[r] + if k == "phy": + core_config[k] = getattr(liteeth_phys, core_config[k]) + if k in ["refclk_freq", "clk_freq"]: + core_config[k] = int(float(core_config[k])) + if k in ["phy_tx_delay", "phy_rx_delay"]: + core_config[k] = float(core_config[k]) + + # Generate core -------------------------------------------------------------------------------- + if "device" not in core_config: + core_config["device"] = "" + if core_config["vendor"] == "lattice": + toolchain = core_config.get("toolchain", "diamond") + platform = LatticePlatform(core_config["device"], io=[], toolchain=toolchain) + elif core_config["vendor"] == "xilinx": + toolchain = core_config.get("toolchain", "vivado") + platform = XilinxPlatform(core_config["device"], io=[], toolchain=toolchain) + else: + raise ValueError("Unsupported vendor: {}".format(core_config["vendor"])) + platform.add_extension(_io) + + soc = UDPCore(platform, core_config) + + with TemporaryDirectory() as path: + builder = Builder(soc, compile_gateware=False, output_dir=path) + builder.build(build_name="liteeth_core") + + file = open(path + "/gateware/liteeth_core.v") + data = file.read() + file.close() + + return data diff --git a/src/manta/ethernet/sink_bridge.py b/src/manta/ethernet/sink_bridge.py new file mode 100644 index 0000000..c10a290 --- /dev/null +++ b/src/manta/ethernet/sink_bridge.py @@ -0,0 +1,26 @@ +from amaranth import * +from manta.utils import * + + +class UDPSinkBridge(Elaboratable): + def __init__(self): + self.bus_i = Signal(InternalBus()) + + self.data_o = Signal(32) + self.last_o = Signal() + self.ready_i = Signal() + self.valid_o = Signal() + + def elaborate(self, platform): + m = Module() + + m.d.sync += self.data_o.eq(0) + m.d.sync += self.last_o.eq(0) + m.d.sync += self.valid_o.eq(0) + + with m.If((self.bus_i.valid) & (~self.bus_i.rw)): + m.d.sync += self.data_o.eq(self.bus_i.data) + m.d.sync += self.last_o.eq(self.bus_i.last) + m.d.sync += self.valid_o.eq(1) + + return m diff --git a/src/manta/ethernet/source_bridge.py b/src/manta/ethernet/source_bridge.py new file mode 100644 index 0000000..e87967b --- /dev/null +++ b/src/manta/ethernet/source_bridge.py @@ -0,0 +1,37 @@ +from amaranth import * +from manta.utils import * + + +class UDPSourceBridge(Elaboratable): + def __init__(self): + self.bus_o = Signal(InternalBus()) + + self.data_i = Signal(32) + self.last_i = Signal() + self.ready_o = Signal() + self.valid_i = Signal() + + def elaborate(self, platform): + m = Module() + + state = Signal() # can either be 0, for read/write, or 1, for data + rw_buf = Signal().like(self.bus_o.rw) + + # Can always take more data + m.d.sync += self.ready_o.eq(1) + + m.d.sync += self.bus_o.eq(0) + with m.If(self.valid_i): + m.d.sync += state.eq(~state) + + with m.If(state == 0): + m.d.sync += rw_buf.eq(self.data_i) + + with m.Else(): + m.d.sync += self.bus_o.addr.eq(self.data_i[:16]) + m.d.sync += self.bus_o.data.eq(self.data_i[16:]) + m.d.sync += self.bus_o.rw.eq(rw_buf) + m.d.sync += self.bus_o.valid.eq(1) + m.d.sync += self.bus_o.last.eq(self.last_i) + + return m diff --git a/src/manta/manta.py b/src/manta/manta.py index c503fd2..35744a5 100644 --- a/src/manta/manta.py +++ b/src/manta/manta.py @@ -155,3 +155,25 @@ class Manta(Elaboratable): ports += instance.get_top_level_ports() return ports + + def generate_verilog(self, strip_internal_attrs=False): + from amaranth.back import verilog + + output = verilog.convert( + self, + name="manta", + ports=self.get_top_level_ports(), + strip_internal_attrs=strip_internal_attrs, + ) + + # Below is a hack! + # The Ethernet core is a Verilog snippet generated by LiteEth, + # which gets appended to the Amaranth output such that everything + # still lives within one file. + + # In the future this shouldn't be required once Amaranth SOC + # launches, but until then, this is likely the simplest approach. + if isinstance(self.interface, EthernetInterface): + output += self.interface.generate_liteeth_core() + + return output