diff --git a/doc/repository_structure.md b/doc/repository_structure.md
index 157410a..a113baf 100644
--- a/doc/repository_structure.md
+++ b/doc/repository_structure.md
@@ -1,6 +1,6 @@
 ## Repository Structure
 - `src/manta/` contains the Python and Verilog source needed to generate and run the cores.
-- `test/` contains testbenchs for HDL. Manta is written in Verilog 2001, but the testbenches are written in SystemVerilog 2012. These are simulated using Icarus Verilog, which produces `.vcd` files, viewable your favorite waveform viewer, like GTKWave.
+- `test/` contains testbenchs for HDL. Manta is written in Verilog 2001, but the testbenches are written in SystemVerilog 2012. These are simulated using Icarus Verilog, which produces `.vcd` files, viewable with your favorite waveform viewer, like GTKWave.
 - `doc/` contains the documentation you're reading right now! It's built into a nice static site by Material for MkDocs, which automatically rebuilds the site on every commit to `main`. This is done with a GitHub Action configured in `.github/`
 - `examples/` is exactly what it sounds like. It contains examples for both the Digilent Nexys 4 DDR/Nexys A7 with thier onboard Series-7, as well as the Icestick with its onboard iCE40.
 - `.github/` also contains some GitHub Actions configuration for automatically running the SystemVerilog testbenches and building the examples, in addition to automatically rebuilding the site.
diff --git a/doc/roadmap.md b/doc/roadmap.md
deleted file mode 100644
index 711de4f..0000000
--- a/doc/roadmap.md
+++ /dev/null
@@ -1,25 +0,0 @@
-# Roadmap
-
-## Prior to v1.0.0 release:
-_targeting August 2023_
-
-- ~~Clean up UART testbenches, make them actually test things~~
-- Pull text from thesis into documentation site
-- Add API reference to documentation site
-- Port logic analyzer examples to the icestick
-    - This requires refactoring the block memory core to use unpacked arrays, since Yosys doesn't support packed arrays.
-- Add method for dumping logic analyzer data to Python
-- Add clock domain crossing to IO core
-- Verify that >16 bit probes work on IO core
-- Add clock domain crossing to Logic Analyzer Core
-- Verify that capture modes work on the Logic Analyzer Core
-- Verify that external triggers work on the Logic Analyzer Core
-- Add global AND/OR to Logic Analyzer Core
-- Make super super sure everything works (need hardware for that)
-
-## Prior to v1.1.0 release:
-- Fix Ethernet packet format
-- Switch from Scapy to Python sockets library
-
-## Prior to v1.2.0 release:
-- [FuseSoC](https://github.com/fusesoc/fusesoc.github.io) Integration
\ No newline at end of file
diff --git a/mkdocs.yml b/mkdocs.yml
index a3b4f4b..cba1c74 100644
--- a/mkdocs.yml
+++ b/mkdocs.yml
@@ -64,7 +64,5 @@ nav:
       - IO Core: io_core.md
       - Logic Analyzer Core: logic_analyzer.md
       - Block Memory Core: block_memory.md
-      # - Ethernet Interface: ethernet.md
-      # - UART: uart.md
     - Repository Structure: repository_structure.md
-    - Roadmap: roadmap.md
+    - Roadmap: https://github.com/fischermoseley/manta/milestones