diff --git a/doc/uart_interface.md b/doc/uart_interface.md
index 3ab3d31..f2d9661 100644
--- a/doc/uart_interface.md
+++ b/doc/uart_interface.md
@@ -13,8 +13,8 @@ The UART interface is used by adding a `uart` entry at the bottom of the configu
 ```yaml
 uart:
   port: "auto"
-  baudrate: 3000000
-  clock_freq: 100000000
+  baudrate: 115200
+  clock_freq: 100e6
   stall_interval: 16
   chunk_size: 256
 ```
diff --git a/examples/verilog/icestick/uart_io_core/manta.yaml b/examples/verilog/icestick/uart_io_core/manta.yaml
index d957e31..e724f7b 100644
--- a/examples/verilog/icestick/uart_io_core/manta.yaml
+++ b/examples/verilog/icestick/uart_io_core/manta.yaml
@@ -13,4 +13,4 @@ cores:
 uart:
   port: "/dev/ttyUSB3"
   baudrate: 115200
-  clock_freq: 12000000
+  clock_freq: 12e6
diff --git a/examples/verilog/icestick/uart_logic_analyzer/manta.yaml b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
index af3d95d..53116ee 100644
--- a/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
+++ b/examples/verilog/icestick/uart_logic_analyzer/manta.yaml
@@ -17,4 +17,4 @@ cores:
 uart:
   port: "/dev/ttyUSB3"
   baudrate: 115200
-  clock_freq: 12000000
+  clock_freq: 12e6
diff --git a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml
index 6bb32d6..21db0e1 100644
--- a/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml
+++ b/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem/manta.yaml
@@ -9,4 +9,4 @@ cores:
 uart:
   port: "/dev/ttyUSB1"
   baudrate: 115200
-  clock_freq: 100000000
+  clock_freq: 100e6
diff --git a/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml b/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml
index e179440..7e4d4aa 100644
--- a/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml
+++ b/examples/verilog/nexys4_ddr/uart_io_core/manta.yaml
@@ -23,4 +23,4 @@ cores:
 uart:
   port: "/dev/ttyUSB1"
   baudrate: 115200
-  clock_freq: 100000000
+  clock_freq: 100e6
diff --git a/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml
index 093613d..c6131a1 100644
--- a/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml
+++ b/examples/verilog/nexys4_ddr/uart_logic_analyzer/manta.yaml
@@ -17,4 +17,4 @@ cores:
 uart:
   port: "/dev/ttyUSB1"
   baudrate: 115200
-  clock_freq: 100000000
+  clock_freq: 100e6
diff --git a/src/manta/uart/__init__.py b/src/manta/uart/__init__.py
index b983537..7537fde 100644
--- a/src/manta/uart/__init__.py
+++ b/src/manta/uart/__init__.py
@@ -75,25 +75,36 @@ class UARTInterface(Elaboratable):
 
     @classmethod
     def from_config(cls, config):
-        port = config.get("port")
-        clock_freq = config.get("clock_freq")
-        baudrate = config.get("baudrate")
-
-        # Warn if unrecognized options have been given
-        recognized_options = [
-            "port",
+        integer_options = [
             "clock_freq",
             "baudrate",
             "chunk_size",
             "stall_interval",
         ]
+
+        string_options = [
+            "port",
+        ]
+
+        sanitized_config = {}
         for option in config:
-            if option not in recognized_options:
+            # Since PyYAML is written to the YAML 1.1 spec, it will parse numeric values written
+            # with scientific notation (ie, `12e6` or `+5.0E+2`) as strings, not floats. At the
+            # time of writing, YAML 1.2 support is pending in PyYAML, so the casting is done
+            # manually here. Switching to ruyaml would also solve this.
+
+            if option in integer_options:
+                sanitized_config[option] = int(float(config[option]))
+
+            elif option in string_options:
+                sanitized_config[option] = config[option]
+
+            else:
                 warn(
                     f"Ignoring unrecognized option '{option}' in UART interface config."
                 )
 
-        return cls(**config)
+        return cls(**sanitized_config)
 
     def to_config(self):
         return {
diff --git a/test/test_verilog_gen.yaml b/test/test_verilog_gen.yaml
index 09feddc..ba0d7b0 100644
--- a/test/test_verilog_gen.yaml
+++ b/test/test_verilog_gen.yaml
@@ -24,4 +24,4 @@ cores:
 uart:
   port: "/dev/ttyUSB1"
   baudrate: 115200
-  clock_freq: 12000000
+  clock_freq: 12e6