From 1cb1b784229e2fc0da90a6df5c1dbafe90830fa5 Mon Sep 17 00:00:00 2001 From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com> Date: Wed, 25 Feb 2026 13:25:16 -0700 Subject: [PATCH] meta: autoformat with updated ruff config --- src/manta/ethernet/__init__.py | 4 +--- src/manta/logic_analyzer/fsm.py | 4 +--- src/manta/memory_core.py | 8 ++------ src/manta/uart/cobs_encode.py | 16 ++++------------ src/manta/uart/stream_packer.py | 4 +--- src/manta/utils.py | 8 ++------ test/test_cobs_encode.py | 12 +++--------- test/test_ether_bridge_sim.py | 12 +++--------- test/test_uart_bridge_sim.py | 4 +--- 9 files changed, 18 insertions(+), 54 deletions(-) diff --git a/src/manta/ethernet/__init__.py b/src/manta/ethernet/__init__.py index 5113370..375bc04 100644 --- a/src/manta/ethernet/__init__.py +++ b/src/manta/ethernet/__init__.py @@ -654,9 +654,7 @@ class EthernetInterface(Elaboratable): data_chunks = split_into_chunks(data, EthernetMessageHeader.MAX_WRITE_LENGTH) for i, chunk in enumerate(data_chunks): - self._write_request( - base_addr + (i * EthernetMessageHeader.MAX_WRITE_LENGTH), chunk - ) + self._write_request(base_addr + (i * EthernetMessageHeader.MAX_WRITE_LENGTH), chunk) def read(self, addrs): """ diff --git a/src/manta/logic_analyzer/fsm.py b/src/manta/logic_analyzer/fsm.py index 85555e2..5afe1dd 100644 --- a/src/manta/logic_analyzer/fsm.py +++ b/src/manta/logic_analyzer/fsm.py @@ -195,9 +195,7 @@ class LogicAnalyzerFSM(Elaboratable): start_time = time.monotonic() while self.registers.get_probe("state") != States.CAPTURED: if timeout is not None and (time.monotonic() - start_time) >= timeout: - raise TimeoutError( - f"Capture did not complete within {timeout} seconds!" - ) + raise TimeoutError(f"Capture did not complete within {timeout} seconds!") time.sleep(0.1) diff --git a/src/manta/memory_core.py b/src/manta/memory_core.py index 3b4c20f..6e859d2 100644 --- a/src/manta/memory_core.py +++ b/src/manta/memory_core.py @@ -217,9 +217,7 @@ class MemoryCore(MantaCore): m.submodules[f"mem_{i}"] = mem # Pipeline the bus to accommodate the two clock-cycle delay in the memories - self._bus_pipe = [ - Signal(InternalBusLayout, name=f"bus_pipe_{i}") for i in range(3) - ] + self._bus_pipe = [Signal(InternalBusLayout, name=f"bus_pipe_{i}") for i in range(3)] m.d.sync += self._bus_pipe[0].eq(self.bus_sink.p) for i in range(1, 3): @@ -255,9 +253,7 @@ class MemoryCore(MantaCore): assert base_addr + length <= self._depth words_by_mem = [ - self.interface.read_block( - self.base_addr + base_addr + (i * self._depth), length - ) + self.interface.read_block(self.base_addr + base_addr + (i * self._depth), length) for i in range(self._n_mems) ] diff --git a/src/manta/uart/cobs_encode.py b/src/manta/uart/cobs_encode.py index a197916..4ca8a26 100644 --- a/src/manta/uart/cobs_encode.py +++ b/src/manta/uart/cobs_encode.py @@ -29,9 +29,7 @@ class COBSEncode(wiring.Component): with m.If(self.sink.valid & self.sink.ready): # Send the length byte, as either a zero has been found, the end of the packet # has been reached, or 254 bytes have been read in. - with m.If( - (self.sink.last) | (self.sink.data == 0) | (fifo.r_level == 253) - ): + with m.If((self.sink.last) | (self.sink.data == 0) | (fifo.r_level == 253)): # Handle edge case where 254th byte is a zero with m.If(fifo.r_level == 253): with m.If(self.sink.data == 0): @@ -41,9 +39,7 @@ class COBSEncode(wiring.Component): m.d.sync += fsm_data.eq(255) with m.Else(): - m.d.sync += fsm_data.eq( - fifo.r_level + fifo_written_to_last_cycle + 1 - ) + m.d.sync += fsm_data.eq(fifo.r_level + fifo_written_to_last_cycle + 1) m.d.sync += was_last.eq(self.sink.last) m.d.sync += was_zero.eq(self.sink.data == 0) @@ -81,16 +77,12 @@ class COBSEncode(wiring.Component): # Wire FIFO input to sink m.d.comb += fifo.w_data.eq(self.sink.data) - m.d.comb += fifo.w_en.eq( - (self.sink.ready) & (self.sink.valid) & (self.sink.data != 0) - ) + m.d.comb += fifo.w_en.eq((self.sink.ready) & (self.sink.valid) & (self.sink.data != 0)) m.d.comb += self.sink.ready.eq(fifo.w_rdy & fsm.ongoing("COUNT_BYTES")) # Wire FIFO output to source, allow FSM to preempt FIFO with m.If( - fsm.ongoing("SEND_LENGTH") - | fsm.ongoing("SEND_ONE") - | fsm.ongoing("SEND_DELIMITER") + fsm.ongoing("SEND_LENGTH") | fsm.ongoing("SEND_ONE") | fsm.ongoing("SEND_DELIMITER") ): m.d.comb += self.source.data.eq(fsm_data) m.d.comb += self.source.valid.eq(1) diff --git a/src/manta/uart/stream_packer.py b/src/manta/uart/stream_packer.py index 89a8840..2b05cb5 100644 --- a/src/manta/uart/stream_packer.py +++ b/src/manta/uart/stream_packer.py @@ -22,9 +22,7 @@ class StreamPacker(wiring.Component): with m.If(idle): with m.If(self.sink.valid): - m.d.sync += self.source.data.eq( - Cat(self.source.data[8:], self.sink.data) - ) + m.d.sync += self.source.data.eq(Cat(self.source.data[8:], self.sink.data)) m.d.sync += count.eq(count + 1) with m.If(count == 3): diff --git a/src/manta/utils.py b/src/manta/utils.py index 2bd66a4..1d0e3a8 100644 --- a/src/manta/utils.py +++ b/src/manta/utils.py @@ -130,14 +130,10 @@ class EthernetMessageHeader(Struct): @classmethod def from_params(cls, msg_type, seq_num, length=0): - return cls.const( - init={"msg_type": msg_type, "seq_num": seq_num, "length": length} - ) + return cls.const(init={"msg_type": msg_type, "seq_num": seq_num, "length": length}) @classmethod - def concat_signals( - cls, msg_type: MessageTypes, seq_num: Signal, length: Signal = None - ): + def concat_signals(cls, msg_type: MessageTypes, seq_num: Signal, length: Signal = None): # Make sure each signal is the right width! widths = cls.from_bits(0).shape().members diff --git a/test/test_cobs_encode.py b/test/test_cobs_encode.py index 23166f3..fd7a9cb 100644 --- a/test/test_cobs_encode.py +++ b/test/test_cobs_encode.py @@ -50,17 +50,11 @@ async def test_cobs_encode_random(ctx): data_no_pref = random.choices(population, weights=no_preference, k=length) data_pref_zeros = random.choices(population, weights=prefer_zeros, k=length) - data_pref_nonzeros = random.choices( - population, weights=prefer_nonzeros, k=length - ) + data_pref_nonzeros = random.choices(population, weights=prefer_nonzeros, k=length) await encode_and_compare(ctx, data_no_pref, tx_irritate=True, rx_irritate=True) - await encode_and_compare( - ctx, data_pref_zeros, tx_irritate=True, rx_irritate=True - ) - await encode_and_compare( - ctx, data_pref_nonzeros, tx_irritate=True, rx_irritate=True - ) + await encode_and_compare(ctx, data_pref_zeros, tx_irritate=True, rx_irritate=True) + await encode_and_compare(ctx, data_pref_nonzeros, tx_irritate=True, rx_irritate=True) async def encode(ctx, data, tx_irritate, rx_irritate): diff --git a/test/test_ether_bridge_sim.py b/test/test_ether_bridge_sim.py index f4747f4..be02273 100644 --- a/test/test_ether_bridge_sim.py +++ b/test/test_ether_bridge_sim.py @@ -64,9 +64,7 @@ async def send_bytes_sporadic(ctx, bytes): async def send_write_request(ctx, module, seq_num, addr, write_data): - await send_bytes( - ctx, module, [(seq_num << 3) | MessageTypes.WRITE_REQUEST, addr] + write_data - ) + await send_bytes(ctx, module, [(seq_num << 3) | MessageTypes.WRITE_REQUEST, addr] + write_data) async def send_read_request(ctx, module, seq_num, addr, read_length): @@ -99,9 +97,7 @@ async def test_ether_bridge(ctx): # write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222, 0x3333_3333], # ) # await send_write_request(ctx, seq_num=4, addr=0x1234_5678, write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222]) - await send_read_request( - ctx, ether_bridge, seq_num=0, addr=0x1234_5678, read_length=1 - ) + await send_read_request(ctx, ether_bridge, seq_num=0, addr=0x1234_5678, read_length=1) # await send_bytes(ctx, [0x0123_4567]) # await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF]) # await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF, 0x0123_4567]) @@ -173,9 +169,7 @@ async def test_ether_bridge_plus_mem_core(ctx): # write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222, 0x3333_3333], # ) # await send_write_request(ctx, seq_num=4, addr=0x1234_5678, write_data=[0x0000_0000, 0x1111_1111, 0x2222_2222]) - await send_read_request( - ctx, bridge_plus_mem_core, seq_num=0, addr=0x1234_5678, read_length=1 - ) + await send_read_request(ctx, bridge_plus_mem_core, seq_num=0, addr=0x1234_5678, read_length=1) # await send_bytes(ctx, [0x0123_4567]) # await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF]) # await send_bytes(ctx, [0x0123_4567, 0x89AB_CDEF, 0x0123_4567]) diff --git a/test/test_uart_bridge_sim.py b/test/test_uart_bridge_sim.py index 53845f2..ffbb78d 100644 --- a/test/test_uart_bridge_sim.py +++ b/test/test_uart_bridge_sim.py @@ -52,9 +52,7 @@ async def send_byte(ctx, module, data): @simulate(uart_hw) async def test_read_request(ctx): addr = 0x5678_9ABC - header = EthernetMessageHeader.from_params( - MessageTypes.READ_REQUEST, seq_num=0x0, length=1 - ) + header = EthernetMessageHeader.from_params(MessageTypes.READ_REQUEST, seq_num=0x0, length=1) request = bytestring_from_ints([header.as_bits(), addr], byteorder="little") encoded = cobs.encode(request) encoded = encoded + int(0).to_bytes(1)