From 1c74d4a71474f095f5ef5c480b1908a22fc4d1e4 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Fri, 14 Apr 2023 19:06:23 -0400
Subject: [PATCH] add running the logic analyzer to the python API

---
 .../logic_analyzer/run_logic_analyzer.py      | 21 +-----
 src/manta/__init__.py                         | 64 ++++++++++++++++++-
 2 files changed, 64 insertions(+), 21 deletions(-)

diff --git a/examples/nexys_a7/logic_analyzer/run_logic_analyzer.py b/examples/nexys_a7/logic_analyzer/run_logic_analyzer.py
index 732136c..ab8022d 100644
--- a/examples/nexys_a7/logic_analyzer/run_logic_analyzer.py
+++ b/examples/nexys_a7/logic_analyzer/run_logic_analyzer.py
@@ -1,23 +1,4 @@
 from manta import Manta
 
 m = Manta('manta.yaml')
-
-# setup trigger to trigger when moe = 1:
-m.my_logic_analyzer.interface.write_register(0, 0) # set state to IDLE
-m.my_logic_analyzer.interface.write_register(6, 8) # set operation to eq
-m.my_logic_analyzer.interface.write_register(7, 1) # set argument to 1
-
-# read that back
-print(m.my_logic_analyzer.interface.read_register(0))
-print(m.my_logic_analyzer.interface.read_register(6))
-print(m.my_logic_analyzer.interface.read_register(7))
-
-
-# start the capture
-m.my_logic_analyzer.interface.write_register(0, 1) # set state to START_CAPTURE
-print(m.my_logic_analyzer.interface.read_register(0))
-
-# display sample data
-for i in range(m.my_logic_analyzer.sample_depth):
-    data = m.my_logic_analyzer.interface.read_register(i)
-    print(f"addr: {i}  data: {data}")
\ No newline at end of file
+print(m.my_logic_analyzer.run())
\ No newline at end of file
diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index 9e3c3c4..1c8b416 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -438,6 +438,21 @@ class LogicAnalyzerCore:
         self.block_memory_base_addr = self.trigger_block_base_addr + (2*len(self.probes))
         self.max_addr = self.block_memory_base_addr + (n_brams * self.sample_depth)
 
+        # build out self register map:
+        #   these are also defined in logic_analyzer_fsm_registers.v, and should match
+        self.state_reg_addr = self.base_addr
+        self.trigger_loc_reg_addr = self.base_addr + 1
+        self.current_loc_reg_addr = self.base_addr + 2
+        self.request_start_reg_addr = self.base_addr + 3
+        self.request_stop_reg_addr = self.base_addr + 4
+        self.read_pointer_reg_addr = self.base_addr + 5
+
+        self.IDLE = 0
+        self.MOVE_TO_POSITION = 1
+        self.IN_POSITION = 2
+        self.CAPTURING = 3
+        self.CAPTURED = 4
+
     def hdl_inst(self):
         la_inst = VerilogManipulator("logic_analyzer_inst_tmpl.v")
 
@@ -566,8 +581,55 @@ class LogicAnalyzerCore:
         return ports
         #return VerilogManipulator().net_dec(self.probes, "input wire")
 
+
+
+    # functions for actually using the core:
+
     def run(self):
-        pass
+        # Check state - if it's in anything other than IDLE,
+        # request to stop the existing capture
+        print(" -> Resetting core...")
+        state = self.interface.read_register(self.state_reg_addr)
+        if state != self.IDLE:
+            self.interface.write_register(self.request_stop_reg_addr, 0)
+            self.interface.write_register(self.request_stop_reg_addr, 1)
+
+            state = self.interface.read_register(self.state_reg_addr)
+            assert state == self.IDLE, "Logic analyzer did not reset to correct state when requested to."
+
+        # Configure trigger settings and positions - highkey don't really know how we're going to do this
+        #   for now, let's just trigger on a changing value of the first probe
+        print(" -> Configuring triggers...")
+        self.interface.write_register(self.trigger_block_base_addr, 3)
+        trigger_setting = self.interface.read_register(self.trigger_block_base_addr)
+        assert trigger_setting == 3, "Trigger did not save the value written to it."
+
+        # Configure the trigger_pos, but we'll skip that for now
+        print(" -> Setting trigger location...")
+
+        # Start the capture by pulsing request_start
+        print(" -> Starting capture...")
+        self.interface.write_register(self.request_start_reg_addr, 1)
+        self.interface.write_register(self.request_start_reg_addr, 0)
+
+        # Wait for core to finish capturing data
+        print(" -> Waiting for capture to complete...")
+        state = self.interface.read_register(self.state_reg_addr)
+        while(state != self.CAPTURED):
+            state = self.interface.read_register(self.state_reg_addr)
+
+        # Read out contents from memory
+        print(" -> Reading sample memory contents...")
+        block_mem_contents = []
+        for i in range(self.block_memory_base_addr, self.max_addr):
+            block_mem_contents.append(self.interface.read_register(i))
+
+        # Revolve BRAM contents around so the data pointed to by the read_pointer
+        # is at the beginning
+        print(" -> Reading read_pointer and revolving memory...")
+        read_pointer = self.interface.read_register(self.read_pointer_reg_addr)
+        return block_mem_contents[read_pointer:] + block_mem_contents[:read_pointer]
+
 
     def part_select(self, data, width):
         top, bottom = width