From 1b6127eb7055ff794a70f931811ef289d75dc7c0 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Fri, 9 Aug 2024 12:51:47 -0700
Subject: [PATCH] meta: fix circular imports

---
 .gitignore                          | 1 +
 doc/getting_started.md              | 2 +-
 src/manta/logic_analyzer/capture.py | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.gitignore b/.gitignore
index 44697e8..e28f46b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,6 +6,7 @@
 venv/
 manta.egg-info/
 .pytest_cache
+.ruff_cache
 __pycache__/
 build/
 
diff --git a/doc/getting_started.md b/doc/getting_started.md
index a6e67ae..eb981b8 100644
--- a/doc/getting_started.md
+++ b/doc/getting_started.md
@@ -19,7 +19,7 @@ Although modern HDLs are rising in popularity, most existing FPGA designs use a
 
 !!! success "VHDL works too!"
 
-    If your FPGA design is VHDL-based, fret not! Most synthesis tools support mixed-language projects, and will happily ingest both a Verilog-based Manta module inside of a VHDL-based design. Just take care to ensure that the interfaces match.
+    If your FPGA design is VHDL-based, fret not! Most synthesis tools support mixed-language projects, and will happily ingest both a Verilog-based Manta module inside of a VHDL-based design. Just take care to ensure that interfaces match between the VHDL and Verilog modules.
 
 ### Example
 
diff --git a/src/manta/logic_analyzer/capture.py b/src/manta/logic_analyzer/capture.py
index 9d9c3a1..878299c 100644
--- a/src/manta/logic_analyzer/capture.py
+++ b/src/manta/logic_analyzer/capture.py
@@ -1,4 +1,4 @@
-from manta.logic_analyzer import TriggerModes
+from manta.logic_analyzer.fsm import TriggerModes
 from manta.logic_analyzer.playback import LogicAnalyzerPlayback