diff --git a/examples/nexys_a7/io_core/knight_rider.py b/examples/nexys_a7/io_core/knight_rider.py
new file mode 100644
index 0000000..d9d03b4
--- /dev/null
+++ b/examples/nexys_a7/io_core/knight_rider.py
@@ -0,0 +1,40 @@
+from manta import Manta
+from time import sleep
+
+m = Manta('manta.yaml')
+
+i = 0
+direction = "left"
+
+while True:
+    if direction == "left":
+        if i == 15:
+            direction = "right"
+            i = i - 1
+            m.my_io_core.led16_r.set(1)
+            m.my_io_core.led16_g.set(0)
+            m.my_io_core.led16_b.set(1)
+        else:
+            i = i + 1
+    
+    if direction == "right":
+        if i == 0:
+            direction = "left"
+            i = i + 1
+            m.my_io_core.led16_r.set(0)
+            m.my_io_core.led16_g.set(1)
+            m.my_io_core.led16_b.set(0)
+        
+        else:
+            i = i - 1
+    
+    m.my_io_core.led.set(2**i)
+    print(f"Input Ports:")
+    print(f"  btnu: {m.my_io_core.btnu.get()}")
+    print(f"  btnd: {m.my_io_core.btnd.get()}")
+    print(f"  btnr: {m.my_io_core.btnr.get()}")
+    print(f"  btnl: {m.my_io_core.btnl.get()}")
+    print(f"  btnc: {m.my_io_core.btnc.get()}")
+    print(f"  sw: {m.my_io_core.sw.get()}\n")
+    sleep(0.5)
+
diff --git a/examples/nexys_a7/io_core/src/top_level.sv b/examples/nexys_a7/io_core/src/top_level.sv
index b7e09b9..5372c05 100644
--- a/examples/nexys_a7/io_core/src/top_level.sv
+++ b/examples/nexys_a7/io_core/src/top_level.sv
@@ -53,7 +53,7 @@ module top_level (
 	assign {cg,cf,ce,cd,cc,cb,ca} = cat;
     ssd ssd (
         .clk_in(clk),
-        .rst_in(cpu_resetn),
+        .rst_in(!cpu_resetn),
         .val_in( (manta.my_io_core_btx_rdata << 16) | (manta.brx_my_io_core_wdata) ),
         .cat_out(cat),
         .an_out(an));
diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index c4352f4..a6419cf 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -175,6 +175,9 @@ class IOCoreProbe:
         self.interface = interface
 
     def set(self, data):
+        # make sure that we're an output probe
+        assert self.direction == "output", "Cannot set value of input port."
+
         # check that value is within range for the width of the probe
         assert isinstance(data, int), "Data must be an integer."
         if data > 0:
@@ -186,7 +189,7 @@ class IOCoreProbe:
 
         self.interface.write_register(self.base_addr, data)
 
-    def get(self, probe):
+    def get(self):
         return self.interface.read_register(self.base_addr)
 
 class IOCore: