From 18d8b76f422d1fb01a87930bf881578b781d8805 Mon Sep 17 00:00:00 2001 From: Fischer Moseley Date: Sat, 4 Feb 2023 11:50:22 -0500 Subject: [PATCH] add workflows --- .github/workflows/run_all_tests.yml | 12 ++++++++++++ README.md | 4 ---- 2 files changed, 12 insertions(+), 4 deletions(-) create mode 100644 .github/workflows/run_all_tests.yml diff --git a/.github/workflows/run_all_tests.yml b/.github/workflows/run_all_tests.yml new file mode 100644 index 0000000..42b52a4 --- /dev/null +++ b/.github/workflows/run_all_tests.yml @@ -0,0 +1,12 @@ +name: run_all_tests +on: [push] +jobs: + install-iverilog: + runs-on: ubuntu-latest + steps: + - run: sudo apt install bison flex g++ gcc + - run: git clone https://github.com/steveicarus/iverilog.git + - run: cd iverilog/ + - run: ./configure + - run: make + - run: sudo make install \ No newline at end of file diff --git a/README.md b/README.md index 4ea7288..02788b7 100644 --- a/README.md +++ b/README.md @@ -1,9 +1,5 @@ ![](assets/manta.png) -
- An In-Situ Debugging Tool for Programmable Hardware -
- Manta is a tool for debugging FPGA designs over UART. It has two modes for doing this, downlink and uplink. The downlink mode feels similar to a logic analyzer, in that Manta provides a waveform view of a configurable set of signals, which get captured when some trigger condition is met. The uplink mode allows a host machine to remotely set values of registers on the FPGA via a python interface. This permits rapid prototyping of logic in Python, and a means of incrementally migrating it to HDL. A more detailed description of each mode is below. Manta is written in Python, and generates SystemVerilog HDL. It's cross-platform, and its only dependency is pySerial. The SystemVerilog templates are included in the Python source, so only a single python file must be included in your project.