From 1710da6f87f7d6b503b96d751451d7ff1826d8f2 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Sun, 9 Apr 2023 22:33:58 -0400
Subject: [PATCH] update makefile to represent new functional sim locations

---
 Makefile                                      | 26 +++++-----
 .../nexys_a7/ether_io_core/send_packet.py     | 51 ++++++++++++++-----
 test/functional_sim/io_core_tb/io_core_tb.sv  |  2 +-
 3 files changed, 51 insertions(+), 28 deletions(-)

diff --git a/Makefile b/Makefile
index 62bd7ff..39dca29 100644
--- a/Makefile
+++ b/Makefile
@@ -29,20 +29,28 @@ auto_gen:
 	python3 test/auto_gen/run_tests.py
 
 # Functional Simulation
-functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_ram_tb uart_tb uart_tx_tb
+functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_ram_tb
 
 io_core_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/io_core_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta			\
+	test/functional_sim/io_core_tb/io_core_tb.sv	\
+	test/functional_sim/io_core_tb/io_core.v
 	vvp sim.out
 	rm sim.out
 
 logic_analyzer_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/logic_analyzer_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta 					\
+	test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv	\
+	test/functional_sim/logic_analyzer_tb/logic_analyzer.v 		\
+	test/functional_sim/logic_analyzer_tb/sample_mem.v			\
+	test/functional_sim/logic_analyzer_tb/trigger_block.v
 	vvp sim.out
 	rm sim.out
 
 bit_fifo_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bit_fifo_tb.sv
+	iverilog -g2012 -o sim.out -y src/manta 		\
+	test/functional_sim/bit_fifo_tb/bit_fifo_tb.sv 	\
+	test/functional_sim/bit_fifo_tb/bit_fifo.v
 	vvp sim.out
 	rm sim.out
 
@@ -61,16 +69,6 @@ lut_ram_tb:
 	vvp sim.out
 	rm sim.out
 
-uart_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tb.sv
-	vvp sim.out
-	rm sim.out
-
-uart_tx_tb:
-	iverilog -g2012 -o sim.out -y src/manta test/functional_sim/uart_tx_tb.sv
-	vvp sim.out
-	rm sim.out
-
 # Build Examples
 
 examples: icestick nexys_a7
diff --git a/examples/nexys_a7/ether_io_core/send_packet.py b/examples/nexys_a7/ether_io_core/send_packet.py
index da82531..8bac7cb 100644
--- a/examples/nexys_a7/ether_io_core/send_packet.py
+++ b/examples/nexys_a7/ether_io_core/send_packet.py
@@ -1,21 +1,46 @@
+from manta import Manta
 from scapy.all import *
 
-src_mac = "00:e0:4c:68:06:aa"
-dst_mac = "69:69:5a:06:54:91"
-ifc = "en8"
+m = Manta('manta.yaml')
+print(m.my_io_core.led.base_addr)
 
-############
 
-echosvc_etype = 0x1234
+def set_led(val):
+    src_mac = "00:e0:4c:68:06:aa"
+    dst_mac = "69:69:5a:06:54:91"
+    ifc = "en8"
 
-mypkt = Ether()
-mypkt.src = src_mac
-mypkt.dst = dst_mac
-mypkt.type = 0x1234
+    mypkt = Ether()
+    mypkt.src = src_mac
+    mypkt.dst = dst_mac
+    mypkt.type = 0x1234
 
-msg = b'\x00\x06\x00\x06'
+    msg = b'\x00\x06' + val.to_bytes(2, 'big')
 
-mypkt = mypkt / msg
-for i in range(200):
+    mypkt = mypkt / msg
     mypkt.load = msg
-    sendp(mypkt, iface=ifc)
\ No newline at end of file
+    sendpfast(mypkt, iface=ifc)
+
+
+
+from time import sleep
+led_val = 1
+direction = True
+while True:
+    if direction:
+        if led_val == 2**15:
+            direction = False
+
+        else:
+            led_val = led_val * 2
+            set_led(led_val)
+
+    else:
+        if led_val == 1:
+            direction = True
+
+        else:
+            led_val = led_val // 2
+            set_led(led_val)
+
+    sleep(0.01)
diff --git a/test/functional_sim/io_core_tb/io_core_tb.sv b/test/functional_sim/io_core_tb/io_core_tb.sv
index 70fe64f..cc0226c 100644
--- a/test/functional_sim/io_core_tb/io_core_tb.sv
+++ b/test/functional_sim/io_core_tb/io_core_tb.sv
@@ -36,7 +36,7 @@ module io_core_tb;
     logic la_tb_valid;
 
 
-    io_core #(.BASE_ADDR(0), .SAMPLE_DEPTH(128)) io(
+    io_core #(.BASE_ADDR(0)) io(
         .clk(clk),
 
         // inputs