diff --git a/examples/nexys_a7/io_core_ether/top_level.sv b/examples/nexys_a7/io_core_ether/top_level.sv index c87b981..44951ea 100644 --- a/examples/nexys_a7/io_core_ether/top_level.sv +++ b/examples/nexys_a7/io_core_ether/top_level.sv @@ -115,7 +115,7 @@ module top_level ( .tx(uart_rxd_out), .brx_my_io_core_addr(aggregate_axiod[31:16]), - .brx_my_io_core_wdata(aggregate_axiod[15:0]), + .brx_my_io_core_data(aggregate_axiod[15:0]), .brx_my_io_core_rw(1'b1), .brx_my_io_core_valid(aggregate_axiov), diff --git a/examples/nexys_a7/io_core_uart/top_level.sv b/examples/nexys_a7/io_core_uart/top_level.sv index 4dff60c..d652eef 100644 --- a/examples/nexys_a7/io_core_uart/top_level.sv +++ b/examples/nexys_a7/io_core_uart/top_level.sv @@ -14,6 +14,7 @@ module top_level ( input wire [15:0] sw, output logic [15:0] led, + output logic dp, output logic led16_b, output logic led16_g, output logic led16_r, @@ -49,12 +50,27 @@ module top_level ( .led17_g(led17_g), .led17_r(led17_r)); + // Show bus on 7-segment display + reg [15:0] addr_latched = 0; + reg [15:0] data_latched = 0; + reg rw_latched = 0; + + always @(posedge clk) begin + if (manta.brx_my_io_core_valid) begin + addr_latched <= manta.my_io_core_brx_addr; + data_latched <= manta.my_io_core_brx_data; + rw_latched <= manta.my_io_core_btx_rw; + end + end + ssd ssd ( .clk(clk), - .val( (manta.my_io_core_btx_rdata << 16) | (manta.brx_my_io_core_wdata) ), + .val( (addr_latched << 16) | (data_latched) ), .cat({cg,cf,ce,cd,cc,cb,ca}), .an(an)); + assign dp = rw_latched; + endmodule `default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/io_core_uart/top_level.xdc b/examples/nexys_a7/io_core_uart/top_level.xdc index fca36e0..b5d0c5e 100644 --- a/examples/nexys_a7/io_core_uart/top_level.xdc +++ b/examples/nexys_a7/io_core_uart/top_level.xdc @@ -72,7 +72,7 @@ set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg -# set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] diff --git a/examples/nexys_a7/lut_mem_ether/top_level.sv b/examples/nexys_a7/lut_mem_ether/top_level.sv index e9d1f4c..e4b32be 100644 --- a/examples/nexys_a7/lut_mem_ether/top_level.sv +++ b/examples/nexys_a7/lut_mem_ether/top_level.sv @@ -6,6 +6,7 @@ module top_level ( output logic [15:0] led, output logic ca, cb, cc, cd, ce, cf, cg, + output logic dp, output logic [7:0] an, output logic led16_r, @@ -26,8 +27,6 @@ module top_level ( assign eth_refclk = clk_50mhz; divider d (.clk(clk), .ethclk(clk_50mhz)); - - manta manta_inst ( .clk(clk_50mhz), @@ -36,26 +35,26 @@ module top_level ( .txen(eth_txen), .txd(eth_txd)); - // debugging! - initial led17_r = 0; - reg [31:0] val = 0; + // Show bus on 7-segment display + reg [15:0] addr_latched = 0; + reg [15:0] data_latched = 0; + reg rw_latched = 0; - always @(posedge clk_50mhz) begin - if(manta_inst.my_lut_mem.valid_o) begin - led <= manta_inst.my_lut_mem.addr_o; - led16_r <= manta_inst.my_lut_mem.rw_o; - led17_r <= !led17_r; - val <= {manta_inst.my_lut_mem.rdata_o, manta_inst.my_lut_mem.wdata_o}; + always @(posedge clk) begin + if (manta.brx_my_lut_mem_valid) begin + addr_latched <= manta.my_lut_mem_brx_addr; + data_latched <= manta.my_lut_mem_brx_data; + rw_latched <= manta.my_lut_mem_btx_rw; end end ssd ssd ( - .clk(clk_50mhz), - .val(val), + .clk(clk), + .val( (addr_latched << 16) | (data_latched) ), .cat({cg,cf,ce,cd,cc,cb,ca}), .an(an)); - + assign dp = rw_latched; endmodule `default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/lut_mem_ether/top_level.xdc b/examples/nexys_a7/lut_mem_ether/top_level.xdc index ee0e978..aac056b 100644 --- a/examples/nexys_a7/lut_mem_ether/top_level.xdc +++ b/examples/nexys_a7/lut_mem_ether/top_level.xdc @@ -72,7 +72,7 @@ set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg -# set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] diff --git a/examples/nexys_a7/lut_mem_uart/top_level.sv b/examples/nexys_a7/lut_mem_uart/top_level.sv index 0436932..0b3570f 100644 --- a/examples/nexys_a7/lut_mem_uart/top_level.sv +++ b/examples/nexys_a7/lut_mem_uart/top_level.sv @@ -7,6 +7,7 @@ module top_level ( output logic [15:0] led, output logic ca, cb, cc, cd, ce, cf, cg, + output logic dp, output logic [7:0] an, input wire uart_txd_in, @@ -19,14 +20,27 @@ module top_level ( .rx(uart_txd_in), .tx(uart_rxd_out)); - assign led = manta_inst.brx_my_lut_mem_addr; + // Show bus on 7-segment display + reg [15:0] addr_latched = 0; + reg [15:0] data_latched = 0; + reg rw_latched = 0; + + always @(posedge clk) begin + if (manta.brx_my_lut_mem_valid) begin + addr_latched <= manta.my_lut_mem_brx_addr; + data_latched <= manta.my_lut_mem_brx_data; + rw_latched <= manta.my_lut_mem_btx_rw; + end + end ssd ssd ( .clk(clk), - .val( {manta_inst.my_lut_mem_btx_rdata, manta_inst.brx_my_lut_mem_wdata} ), + .val( (addr_latched << 16) | (data_latched) ), .cat({cg,cf,ce,cd,cc,cb,ca}), .an(an)); + assign dp = rw_latched; + endmodule `default_nettype wire \ No newline at end of file diff --git a/examples/nexys_a7/lut_mem_uart/top_level.xdc b/examples/nexys_a7/lut_mem_uart/top_level.xdc index dda448a..cd8e731 100644 --- a/examples/nexys_a7/lut_mem_uart/top_level.xdc +++ b/examples/nexys_a7/lut_mem_uart/top_level.xdc @@ -72,7 +72,7 @@ set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg -# set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] diff --git a/examples/nexys_a7/video_sprite_uart/src/top_level.sv b/examples/nexys_a7/video_sprite_uart/src/top_level.sv index b11b8a4..bb87d97 100644 --- a/examples/nexys_a7/video_sprite_uart/src/top_level.sv +++ b/examples/nexys_a7/video_sprite_uart/src/top_level.sv @@ -9,7 +9,7 @@ input wire btnc, output logic [15:0] led, - output logic ca, cb, cc, cd, ce, cf, cg, + output logic ca, cb, cc, cd, ce, cf, cg, dp, output logic [7:0] an, input wire uart_txd_in, @@ -92,14 +92,26 @@ assign vga_hs = ~hsync_pipe[1]; assign vga_vs = ~vsync_pipe[1]; - // debug - assign led = manta_inst.brx_image_mem_addr; + // Show bus on 7-segment display + reg [15:0] addr_latched = 0; + reg [15:0] data_latched = 0; + reg rw_latched = 0; + + always @(posedge clk) begin + if (manta.brx_image_mem_valid) begin + addr_latched <= manta.image_mem_brx_addr; + data_latched <= manta.image_mem_brx_data; + rw_latched <= manta.image_mem_btx_rw; + end + end ssd ssd ( - .clk(clk_65mhz), - .val( {manta_inst.image_mem_btx_rdata, manta_inst.brx_image_mem_wdata} ), + .clk(clk), + .val( (addr_latched << 16) | (data_latched) ), .cat({cg,cf,ce,cd,cc,cb,ca}), .an(an)); + + assign dp = rw_latched; endmodule `default_nettype wire diff --git a/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc b/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc index 9ca45f2..4972848 100644 --- a/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc +++ b/examples/nexys_a7/video_sprite_uart/xdc/top_level.xdc @@ -73,7 +73,7 @@ set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce }]; set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf }]; #IO_L19P_T3_A10_D26_14 Sch=cf set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg }]; #IO_L4P_T0_D04_14 Sch=cg -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp }]; #IO_L19N_T3_A21_VREF_15 Sch=dp set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] diff --git a/src/manta/__init__.py b/src/manta/__init__.py index 301cd15..cbe3567 100644 --- a/src/manta/__init__.py +++ b/src/manta/__init__.py @@ -96,8 +96,7 @@ class Manta: dst = core_pair[1].name hdl = f"reg [15:0] {src}_{dst}_addr;\n" - hdl += f"reg [15:0] {src}_{dst}_wdata;\n" - hdl += f"reg [15:0] {src}_{dst}_rdata;\n" + hdl += f"reg [15:0] {src}_{dst}_data;\n" hdl += f"reg {src}_{dst}_rw;\n" hdl += f"reg {src}_{dst}_valid;\n" conns.append(hdl) @@ -119,10 +118,9 @@ class Manta: else: src_name = self.cores[i-1].name - hdl = hdl.replace(".rdata_i()", f".rdata_i({src_name}_{core.name}_rdata)") hdl = hdl.replace(".addr_i()", f".addr_i({src_name}_{core.name}_addr)") - hdl = hdl.replace(".wdata_i()", f".wdata_i({src_name}_{core.name}_wdata)") + hdl = hdl.replace(".data_i()", f".data_i({src_name}_{core.name}_data)") hdl = hdl.replace(".rw_i()", f".rw_i({src_name}_{core.name}_rw)") hdl = hdl.replace(".valid_i()", f".valid_i({src_name}_{core.name}_valid)") @@ -132,12 +130,11 @@ class Manta: if (i < len(self.cores)-1): dst_name = self.cores[i+1].name hdl = hdl.replace(".addr_o()", f".addr_o({core.name}_{dst_name}_addr)") - hdl = hdl.replace(".wdata_o()", f".wdata_o({core.name}_{dst_name}_wdata)") else: dst_name = "btx" - hdl = hdl.replace(".rdata_o()", f".rdata_o({core.name}_{dst_name}_rdata)") + hdl = hdl.replace(".data_o()", f".data_o({core.name}_{dst_name}_data)") hdl = hdl.replace(".rw_o()", f".rw_o({core.name}_{dst_name}_rw)") hdl = hdl.replace(".valid_o()", f".valid_o({core.name}_{dst_name}_valid)") @@ -223,14 +220,14 @@ class Manta: interface_rx_inst = self.interface.rx_hdl_inst() interface_rx_inst = interface_rx_inst.replace("addr_o()", f"addr_o(brx_{self.cores[0].name}_addr)") - interface_rx_inst = interface_rx_inst.replace("wdata_o()", f"wdata_o(brx_{self.cores[0].name}_wdata)") + interface_rx_inst = interface_rx_inst.replace("data_o()", f"data_o(brx_{self.cores[0].name}_data)") interface_rx_inst = interface_rx_inst.replace("rw_o()", f"rw_o(brx_{self.cores[0].name}_rw)") interface_rx_inst = interface_rx_inst.replace("valid_o()", f"valid_o(brx_{self.cores[0].name}_valid)") # connect interface_rx to core_chain interface_rx_conn= f""" reg [15:0] brx_{self.cores[0].name}_addr; -reg [15:0] brx_{self.cores[0].name}_wdata; +reg [15:0] brx_{self.cores[0].name}_data; reg brx_{self.cores[0].name}_rw; reg brx_{self.cores[0].name}_valid;\n""" @@ -240,7 +237,7 @@ reg brx_{self.cores[0].name}_valid;\n""" # connect core_chain to interface_tx interface_tx_conn = f""" -reg [15:0] {self.cores[-1].name}_btx_rdata; +reg [15:0] {self.cores[-1].name}_btx_data; reg {self.cores[-1].name}_btx_rw; reg {self.cores[-1].name}_btx_valid;\n""" @@ -248,7 +245,7 @@ reg {self.cores[-1].name}_btx_valid;\n""" interface_tx_inst = self.interface.tx_hdl_inst() interface_tx_inst = interface_tx_inst.replace("addr_i()", f"addr_i({self.cores[0].name}_btx_addr)") - interface_tx_inst = interface_tx_inst.replace("rdata_i()", f"rdata_i({self.cores[0].name}_btx_rdata)") + interface_tx_inst = interface_tx_inst.replace("data_i()", f"data_i({self.cores[0].name}_btx_data)") interface_tx_inst = interface_tx_inst.replace("rw_i()", f"rw_i({self.cores[0].name}_btx_rw)") interface_tx_inst = interface_tx_inst.replace("valid_i()", f"valid_i({self.cores[0].name}_btx_valid)") diff --git a/src/manta/block_mem_core/block_memory.v b/src/manta/block_mem_core/block_memory.v index e0d5814..006df1e 100644 --- a/src/manta/block_mem_core/block_memory.v +++ b/src/manta/block_mem_core/block_memory.v @@ -6,15 +6,13 @@ module block_memory ( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o, @@ -52,28 +50,24 @@ module block_memory ( // Pipelining reg [2:0][15:0] addr_pipe = 0; - reg [2:0][15:0] wdata_pipe = 0; - reg [2:0][15:0] rdata_pipe = 0; + reg [2:0][15:0] data_pipe = 0; reg [2:0] valid_pipe = 0; reg [2:0] rw_pipe = 0; always @(posedge clk) begin addr_pipe[0] <= addr_i; - wdata_pipe[0] <= wdata_i; - rdata_pipe[0] <= rdata_i; + data_pipe[0] <= data_i; valid_pipe[0] <= valid_i; rw_pipe[0] <= rw_i; addr_o <= addr_pipe[2]; - wdata_o <= wdata_pipe[2]; - rdata_o <= rdata_pipe[2]; + data_o <= data_pipe[2]; valid_o <= valid_pipe[2]; rw_o <= rw_pipe[2]; for(int i=1; i<3; i=i+1) begin addr_pipe[i] <= addr_pipe[i-1]; - wdata_pipe[i] <= wdata_pipe[i-1]; - rdata_pipe[i] <= rdata_pipe[i-1]; + data_pipe[i] <= data_pipe[i-1]; valid_pipe[i] <= valid_pipe[i-1]; rw_pipe[i] <= rw_pipe[i-1]; end @@ -83,12 +77,12 @@ module block_memory ( if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= MAX_ADDR)) begin wea[addr_i % N_BRAMS] <= rw_i; addra[addr_i % N_BRAMS] <= (addr_i - BASE_ADDR) / N_BRAMS; - dina[addr_i % N_BRAMS] <= wdata_i; + dina[addr_i % N_BRAMS] <= data_i; end // pull BRAM reads from the back of the pipeline if( (valid_pipe[2]) && (addr_pipe[2] >= BASE_ADDR) && (addr_pipe[2] <= MAX_ADDR)) begin - rdata_o <= douta[addr_pipe[2] % N_BRAMS]; + data_o <= douta[addr_pipe[2] % N_BRAMS]; end end diff --git a/src/manta/block_mem_core/block_memory_inst_tmpl.v b/src/manta/block_mem_core/block_memory_inst_tmpl.v index b64baae..f1c8767 100644 --- a/src/manta/block_mem_core/block_memory_inst_tmpl.v +++ b/src/manta/block_mem_core/block_memory_inst_tmpl.v @@ -5,8 +5,7 @@ block_memory #( .clk(clk), .addr_i(), - .wdata_i(), - .rdata_i(), + .data_i(), .rw_i(), .valid_i(), @@ -17,7 +16,6 @@ block_memory #( .user_we(/* INST_NAME */_we), .addr_o(), - .wdata_o(), - .rdata_o(), + .data_o(), .rw_o(), .valid_o()); \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_rx.v b/src/manta/ether_iface/ethernet_rx.v index f057709..ba36ec7 100644 --- a/src/manta/ether_iface/ethernet_rx.v +++ b/src/manta/ether_iface/ethernet_rx.v @@ -8,7 +8,7 @@ module ethernet_rx ( input wire [1:0] rxd, output reg [15:0] addr_o, - output reg [15:0] wdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o ); @@ -33,7 +33,7 @@ module ethernet_rx ( assign rw_o = (payload[39:32] == 8'd1); assign addr_o = payload[31:16]; - assign wdata_o = payload[15:0]; + assign data_o = payload[15:0]; assign valid_o = valid && ( payload[39:32] == 8'd0 || payload[39:32] == 8'd1) && (payload[55:40] == 16'h88B5); endmodule diff --git a/src/manta/ether_iface/ethernet_rx_inst_tmpl.v b/src/manta/ether_iface/ethernet_rx_inst_tmpl.v index 937ce52..7eae02b 100644 --- a/src/manta/ether_iface/ethernet_rx_inst_tmpl.v +++ b/src/manta/ether_iface/ethernet_rx_inst_tmpl.v @@ -8,6 +8,6 @@ ethernet_rx #( .rxd(rxd), .addr_o(), - .wdata_o(), + .data_o(), .rw_o(), .valid_o()); \ No newline at end of file diff --git a/src/manta/ether_iface/ethernet_tx.v b/src/manta/ether_iface/ethernet_tx.v index cce4110..318b3ba 100644 --- a/src/manta/ether_iface/ethernet_tx.v +++ b/src/manta/ether_iface/ethernet_tx.v @@ -4,7 +4,7 @@ module ethernet_tx ( input wire clk, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, @@ -16,10 +16,10 @@ module ethernet_tx ( parameter HOST_MAC = 0; parameter ETHERTYPE = 0; - reg [15:0] rdata_buf = 0; + reg [15:0] data_buf = 0; always @(posedge clk) - if(~rw_i && valid_i) rdata_buf <= rdata_i; + if(~rw_i && valid_i) data_buf <= data_i; mac_tx #( .SRC_MAC(FPGA_MAC), @@ -29,7 +29,7 @@ module ethernet_tx ( ) mtx ( .clk(clk), - .payload({24'd0, rdata_buf}), + .payload({24'd0, data_buf}), .start(~rw_i && valid_i), .txen(txen), diff --git a/src/manta/ether_iface/ethernet_tx_inst_tmpl.v b/src/manta/ether_iface/ethernet_tx_inst_tmpl.v index d618593..6082910 100644 --- a/src/manta/ether_iface/ethernet_tx_inst_tmpl.v +++ b/src/manta/ether_iface/ethernet_tx_inst_tmpl.v @@ -5,7 +5,7 @@ ethernet_tx #( ) etx ( .clk(clk), - .rdata_i(), + .data_i(), .rw_i(), .valid_i(), diff --git a/src/manta/io_core/__init__.py b/src/manta/io_core/__init__.py index 8363b9b..313f727 100644 --- a/src/manta/io_core/__init__.py +++ b/src/manta/io_core/__init__.py @@ -105,22 +105,22 @@ class IOCore: # add to read block if probe.width == 16: - rcsb += f"{probe.base_addr}: rdata_o <= {probe.name};\n" + rcsb += f"{probe.base_addr}: data_o <= {probe.name};\n" else: - rcsb += f"{probe.base_addr}: rdata_o <= {{{16-probe.width}'b0, {probe.name}}};\n" + rcsb += f"{probe.base_addr}: data_o <= {{{16-probe.width}'b0, {probe.name}}};\n" # if output, add to write block if probe.direction == "output": if probe.width == 1: - wcsb += f"{probe.base_addr}: {probe.name} <= wdata_i[0];\n" + wcsb += f"{probe.base_addr}: {probe.name} <= data_i[0];\n" elif probe.width == 16: - wcsb += f"{probe.base_addr}: {probe.name} <= wdata_i;\n" + wcsb += f"{probe.base_addr}: {probe.name} <= data_i;\n" else: - wcsb += f"{probe.base_addr}: {probe.name} <= wdata_i[{probe.width-1}:0];\n" + wcsb += f"{probe.base_addr}: {probe.name} <= data_i[{probe.width-1}:0];\n" # remove trailing newline rcsb = rcsb.rstrip() diff --git a/src/manta/io_core/io_core_def_tmpl.v b/src/manta/io_core/io_core_def_tmpl.v index 0bf8875..faad92a 100644 --- a/src/manta/io_core/io_core_def_tmpl.v +++ b/src/manta/io_core/io_core_def_tmpl.v @@ -6,15 +6,13 @@ module /* MODULE_NAME */ ( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o ); @@ -23,12 +21,9 @@ module /* MODULE_NAME */ ( always @(posedge clk) begin addr_o <= addr_i; - wdata_o <= wdata_i; - rdata_o <= rdata_i; + data_o <= data_i; rw_o <= rw_i; valid_o <= valid_i; - rdata_o <= rdata_i; - // check if address is valid if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + /* MAX_ADDR */)) begin diff --git a/src/manta/io_core/io_core_inst_tmpl.v b/src/manta/io_core/io_core_inst_tmpl.v index 52f83eb..8eeb7f5 100644 --- a/src/manta/io_core/io_core_inst_tmpl.v +++ b/src/manta/io_core/io_core_inst_tmpl.v @@ -6,14 +6,12 @@ // input port .addr_i(), - .wdata_i(), - .rdata_i(), + .data_i(), .rw_i(), .valid_i(), // output port .addr_o(), - .wdata_o(), - .rdata_o(), + .data_o(), .rw_o(), .valid_o()); \ No newline at end of file diff --git a/src/manta/la_core/__init__.py b/src/manta/la_core/__init__.py index 8071873..b80bf4e 100644 --- a/src/manta/la_core/__init__.py +++ b/src/manta/la_core/__init__.py @@ -159,12 +159,12 @@ class LogicAnalyzerCore: addr = 0 for i, name in enumerate(self.probes): addr = 2 * i - rcsb += f"BASE_ADDR + {addr}: rdata_o <= {name}_op;\n" - wcsb += f"BASE_ADDR + {addr}: {name}_op <= wdata_i;\n" + rcsb += f"BASE_ADDR + {addr}: data_o <= {name}_op;\n" + wcsb += f"BASE_ADDR + {addr}: {name}_op <= data_i;\n" addr = (2 * i) + 1 - rcsb += f"BASE_ADDR + {addr}: rdata_o <= {name}_arg;\n" - wcsb += f"BASE_ADDR + {addr}: {name}_arg <= wdata_i;\n" + rcsb += f"BASE_ADDR + {addr}: data_o <= {name}_arg;\n" + wcsb += f"BASE_ADDR + {addr}: {name}_arg <= data_i;\n" rcsb = rcsb.strip() wcsb = wcsb.strip() diff --git a/src/manta/la_core/logic_analyzer_def_tmpl.v b/src/manta/la_core/logic_analyzer_def_tmpl.v index 3d6b1c4..cbb0ef9 100644 --- a/src/manta/la_core/logic_analyzer_def_tmpl.v +++ b/src/manta/la_core/logic_analyzer_def_tmpl.v @@ -9,15 +9,13 @@ module logic_analyzer ( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o ); @@ -68,14 +66,12 @@ module logic_analyzer ( .clk(clk), .addr_i(addr_i), - .wdata_i(wdata_i), - .rdata_i(rdata_i), + .data_i(data_i), .rw_i(rw_i), .valid_i(valid_i), .addr_o(fsm_reg_trig_blk_addr), - .wdata_o(fsm_reg_trig_blk_wdata), - .rdata_o(fsm_reg_trig_blk_rdata), + .data_o(fsm_reg_trig_blk_data), .rw_o(fsm_reg_trig_blk_rw), .valid_o(fsm_reg_trig_blk_valid), @@ -88,8 +84,7 @@ module logic_analyzer ( .write_pointer(write_pointer)); reg [15:0] fsm_reg_trig_blk_addr; - reg [15:0] fsm_reg_trig_blk_wdata; - reg [15:0] fsm_reg_trig_blk_rdata; + reg [15:0] fsm_reg_trig_blk_data; reg fsm_reg_trig_blk_rw; reg fsm_reg_trig_blk_valid; @@ -102,20 +97,17 @@ module logic_analyzer ( .trig(trig), .addr_i(fsm_reg_trig_blk_addr), - .wdata_i(fsm_reg_trig_blk_wdata), - .rdata_i(fsm_reg_trig_blk_rdata), + .data_i(fsm_reg_trig_blk_data), .rw_i(fsm_reg_trig_blk_rw), .valid_i(fsm_reg_trig_blk_valid), .addr_o(trig_blk_block_mem_addr), - .wdata_o(trig_blk_block_mem_wdata), - .rdata_o(trig_blk_block_mem_rdata), + .data_o(trig_blk_block_mem_data), .rw_o(trig_blk_block_mem_rw), .valid_o(trig_blk_block_mem_valid)); reg [15:0] trig_blk_block_mem_addr; - reg [15:0] trig_blk_block_mem_wdata; - reg [15:0] trig_blk_block_mem_rdata; + reg [15:0] trig_blk_block_mem_data; reg trig_blk_block_mem_rw; reg trig_blk_block_mem_valid; @@ -129,15 +121,13 @@ module logic_analyzer ( // input port .addr_i(trig_blk_block_mem_addr), - .wdata_i(trig_blk_block_mem_wdata), - .rdata_i(trig_blk_block_mem_rdata), + .data_i(trig_blk_block_mem_data), .rw_i(trig_blk_block_mem_rw), .valid_i(trig_blk_block_mem_valid), // output port .addr_o(addr_o), - .wdata_o(wdata_o), - .rdata_o(rdata_o), + .data_o(data_o), .rw_o(rw_o), .valid_o(valid_o), diff --git a/src/manta/la_core/logic_analyzer_fsm_registers.v b/src/manta/la_core/logic_analyzer_fsm_registers.v index 9efa6d4..d35bcfb 100644 --- a/src/manta/la_core/logic_analyzer_fsm_registers.v +++ b/src/manta/la_core/logic_analyzer_fsm_registers.v @@ -6,15 +6,13 @@ module logic_analyzer_fsm_registers( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o, @@ -40,8 +38,7 @@ module logic_analyzer_fsm_registers( always @(posedge clk) begin addr_o <= addr_i; - wdata_o <= wdata_i; - rdata_o <= rdata_i; + data_o <= data_i; rw_o <= rw_i; valid_o <= valid_i; @@ -51,23 +48,23 @@ module logic_analyzer_fsm_registers( // reads if(!rw_i) begin case (addr_i) - BASE_ADDR + 0: rdata_o <= state; - BASE_ADDR + 1: rdata_o <= trigger_mode; - BASE_ADDR + 2: rdata_o <= trigger_loc; - BASE_ADDR + 3: rdata_o <= request_start; - BASE_ADDR + 4: rdata_o <= request_stop; - BASE_ADDR + 5: rdata_o <= read_pointer; - BASE_ADDR + 6: rdata_o <= write_pointer; + BASE_ADDR + 0: data_o <= state; + BASE_ADDR + 1: data_o <= trigger_mode; + BASE_ADDR + 2: data_o <= trigger_loc; + BASE_ADDR + 3: data_o <= request_start; + BASE_ADDR + 4: data_o <= request_stop; + BASE_ADDR + 5: data_o <= read_pointer; + BASE_ADDR + 6: data_o <= write_pointer; endcase end // writes else begin case (addr_i) - BASE_ADDR + 1: trigger_mode <= wdata_i; - BASE_ADDR + 2: trigger_loc <= wdata_i; - BASE_ADDR + 3: request_start <= wdata_i; - BASE_ADDR + 4: request_stop <= wdata_i; + BASE_ADDR + 1: trigger_mode <= data_i; + BASE_ADDR + 2: trigger_loc <= data_i; + BASE_ADDR + 3: request_start <= data_i; + BASE_ADDR + 4: request_stop <= data_i; endcase end end diff --git a/src/manta/la_core/logic_analyzer_inst_tmpl.v b/src/manta/la_core/logic_analyzer_inst_tmpl.v index 1004ab3..eebb872 100644 --- a/src/manta/la_core/logic_analyzer_inst_tmpl.v +++ b/src/manta/la_core/logic_analyzer_inst_tmpl.v @@ -2,15 +2,13 @@ logic_analyzer /* INST_NAME */ ( .clk(clk), .addr_i(), - .wdata_i(), - .rdata_i(), + .data_i(), .rw_i(), .valid_i(), /* NET_CONNS */ .addr_o(), - .wdata_o(), - .rdata_o(), + .data_o(), .rw_o(), .valid_o()); \ No newline at end of file diff --git a/src/manta/la_core/trigger_block_def_tmpl.v b/src/manta/la_core/trigger_block_def_tmpl.v index 49bfbaa..39af04f 100644 --- a/src/manta/la_core/trigger_block_def_tmpl.v +++ b/src/manta/la_core/trigger_block_def_tmpl.v @@ -12,15 +12,13 @@ module trigger_block ( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o); @@ -38,11 +36,9 @@ module trigger_block ( // perform register operations always @(posedge clk) begin addr_o <= addr_i; - wdata_o <= wdata_i; - rdata_o <= rdata_i; + data_o <= data_i; rw_o <= rw_i; valid_o <= valid_i; - rdata_o <= rdata_i; if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + MAX_ADDR) ) begin diff --git a/src/manta/lut_mem_core/lut_mem.v b/src/manta/lut_mem_core/lut_mem.v index 7ba8335..741384c 100644 --- a/src/manta/lut_mem_core/lut_mem.v +++ b/src/manta/lut_mem_core/lut_mem.v @@ -6,15 +6,13 @@ module lut_mem ( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o); @@ -25,11 +23,9 @@ module lut_mem ( always @(posedge clk) begin addr_o <= addr_i; - wdata_o <= wdata_i; - rdata_o <= rdata_i; + data_o <= data_i; rw_o <= rw_i; valid_o <= valid_i; - rdata_o <= rdata_i; if(valid_i) begin @@ -37,8 +33,8 @@ module lut_mem ( if( (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + DEPTH - 1) ) begin // read/write - if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= wdata_i; - else rdata_o <= mem[addr_i - BASE_ADDR]; + if (rw_i && !READ_ONLY) mem[addr_i - BASE_ADDR] <= data_i; + else data_o <= mem[addr_i - BASE_ADDR]; end end end diff --git a/src/manta/lut_mem_core/lut_mem_inst_tmpl.v b/src/manta/lut_mem_core/lut_mem_inst_tmpl.v index 1effbff..9ddc38b 100644 --- a/src/manta/lut_mem_core/lut_mem_inst_tmpl.v +++ b/src/manta/lut_mem_core/lut_mem_inst_tmpl.v @@ -2,13 +2,11 @@ lut_mem #(.DEPTH(/* DEPTH */)) /* INST_NAME */ ( .clk(clk), .addr_i(), - .wdata_i(), - .rdata_i(), + .data_i(), .rw_i(), .valid_i(), .addr_o(), - .wdata_o(), - .rdata_o(), + .data_o(), .rw_o(), .valid_o()); \ No newline at end of file diff --git a/test/functional_sim/block_memory_tb.sv b/test/functional_sim/block_memory_tb.sv index 2ace56c..818ca3b 100644 --- a/test/functional_sim/block_memory_tb.sv +++ b/test/functional_sim/block_memory_tb.sv @@ -19,7 +19,7 @@ task read_reg_bus_side ( block_memory_tb.tb_bc_rw = 0; block_memory_tb.tb_bc_valid = 0; while (!block_memory_tb.bc_tb_valid) #`CP; - data = block_memory_tb.bc_tb_rdata; + data = block_memory_tb.bc_tb_data; $display(" -> bus read 0x%h from addr 0x%h", data, addr); endtask @@ -30,7 +30,7 @@ task write_reg_bus_side( ); block_memory_tb.tb_bc_addr = addr; - block_memory_tb.tb_bc_wdata = data; + block_memory_tb.tb_bc_data = data; block_memory_tb.tb_bc_rw = 1; block_memory_tb.tb_bc_valid = 1; #`CP @@ -85,15 +85,13 @@ module block_memory_tb; // tb -> bram_core bus logic [15:0] tb_bc_addr; - logic [15:0] tb_bc_wdata; - logic [15:0] tb_bc_rdata; + logic [15:0] tb_bc_data; logic tb_bc_rw; logic tb_bc_valid; // bram_core -> tb bus logic [15:0] bc_tb_addr; - logic [15:0] bc_tb_wdata; - logic [15:0] bc_tb_rdata; + logic [15:0] bc_tb_data; logic bc_tb_rw; logic bc_tb_valid; @@ -110,14 +108,12 @@ module block_memory_tb; .clk(clk), .addr_i(tb_bc_addr), - .wdata_i(tb_bc_wdata), - .rdata_i(tb_bc_rdata), + .data_i(tb_bc_data), .rw_i(tb_bc_rw), .valid_i(tb_bc_valid), .addr_o(bc_tb_addr), - .wdata_o(bc_tb_wdata), - .rdata_o(bc_tb_rdata), + .data_o(bc_tb_data), .rw_o(bc_tb_rw), .valid_o(bc_tb_valid), @@ -141,8 +137,7 @@ module block_memory_tb; test_num = 0; tb_bc_addr = 0; - tb_bc_rdata = 0; - tb_bc_wdata = 0; + tb_bc_data = 0; tb_bc_rw = 0; tb_bc_valid = 0; diff --git a/test/functional_sim/bridge_tx_tb.sv b/test/functional_sim/bridge_tx_tb.sv index 2cfc32b..b906e4e 100644 --- a/test/functional_sim/bridge_tx_tb.sv +++ b/test/functional_sim/bridge_tx_tb.sv @@ -12,7 +12,7 @@ logic clk; integer test_num; // tb -> bridge_tx signals -logic [15:0] tb_btx_rdata; +logic [15:0] tb_btx_data; logic tb_btx_valid; // uart_tx -> tb signals @@ -21,7 +21,7 @@ logic utx_tb_tx; bridge_tx btx ( .clk(clk), - .data_i(tb_btx_rdata), + .data_i(tb_btx_data), .rw_i(1'b1), .valid_i(tb_btx_valid), @@ -56,13 +56,13 @@ initial begin test_num = 0; tb_btx_valid = 0; - tb_btx_rdata = 0; + tb_btx_data = 0; #(10*`CP); /* ==== Test 1 Begin ==== */ $display("\n=== test 1: receive 0x0123 for baseline functionality ==="); test_num = 1; - tb_btx_rdata = 16'h0123; + tb_btx_data = 16'h0123; tb_btx_valid = 1; #`CP; @@ -74,7 +74,7 @@ initial begin /* ==== Test 2 Begin ==== */ $display("\n=== test 2: receive 0x4567 for baseline functionality ==="); test_num = 2; - tb_btx_rdata = 16'h4567; + tb_btx_data = 16'h4567; tb_btx_valid = 1; #`CP; @@ -86,7 +86,7 @@ initial begin /* ==== Test 3 Begin ==== */ $display("\n=== test 3: receive 0x89AB for baseline functionality ==="); test_num = 3; - tb_btx_rdata = 16'h89AB; + tb_btx_data = 16'h89AB; tb_btx_valid = 1; #`CP; @@ -98,7 +98,7 @@ initial begin /* ==== Test 4 Begin ==== */ $display("\n=== test 4: receive 0xCDEF for baseline functionality ==="); test_num = 4; - tb_btx_rdata = 16'hCDEF; + tb_btx_data = 16'hCDEF; tb_btx_valid = 1; #`CP; diff --git a/test/functional_sim/ethernet_rx_tb.sv b/test/functional_sim/ethernet_rx_tb.sv index 1ec1d49..89ee8d4 100644 --- a/test/functional_sim/ethernet_rx_tb.sv +++ b/test/functional_sim/ethernet_rx_tb.sv @@ -42,7 +42,7 @@ module ethernet_rx_tb(); assign crsdv = txen; logic [15:0] erx_addr; - logic [15:0] erx_wdata; + logic [15:0] erx_data; logic erx_rw; logic erx_valid; @@ -56,7 +56,7 @@ module ethernet_rx_tb(); .rxd(rxd), .addr_o(erx_addr), - .wdata_o(erx_wdata), + .data_o(erx_data), .rw_o(erx_rw), .valid_o(erx_valid)); diff --git a/test/functional_sim/ethernet_tx_tb.sv b/test/functional_sim/ethernet_tx_tb.sv index 80348d8..0146753 100644 --- a/test/functional_sim/ethernet_tx_tb.sv +++ b/test/functional_sim/ethernet_tx_tb.sv @@ -9,7 +9,7 @@ task send_on_etx_receive_on_mrx ( input [15:0] data ); - ethernet_tx_tb.etx_rdata = data; + ethernet_tx_tb.etx_data = data; ethernet_tx_tb.etx_rw = 0; ethernet_tx_tb.etx_valid = 0; #10; @@ -36,7 +36,7 @@ module ethernet_tx_tb(); logic [1:0] txd; // ethernet tx - reg [15:0] etx_rdata; + reg [15:0] etx_data; reg etx_rw; reg etx_valid; @@ -47,7 +47,7 @@ module ethernet_tx_tb(); ) etx ( .clk(clk), - .rdata_i(etx_rdata), + .data_i(etx_data), .rw_i(etx_rw), .valid_i(etx_valid), @@ -89,7 +89,7 @@ module ethernet_tx_tb(); $dumpfile("ethernet_tx_tb.vcd"); $dumpvars(0, ethernet_tx_tb); clk = 0; - etx_rdata = 16'h6970; + etx_data = 16'h6970; etx_rw = 0; etx_valid = 0; #50; diff --git a/test/functional_sim/io_core_tb/io_core.v b/test/functional_sim/io_core_tb/io_core.v index df52a8a..e4caa92 100644 --- a/test/functional_sim/io_core_tb/io_core.v +++ b/test/functional_sim/io_core_tb/io_core.v @@ -18,15 +18,13 @@ module io_core( // input port input wire [15:0] addr_i, - input wire [15:0] wdata_i, - input wire [15:0] rdata_i, + input wire [15:0] data_i, input wire rw_i, input wire valid_i, // output port output reg [15:0] addr_o, - output reg [15:0] wdata_o, - output reg [15:0] rdata_o, + output reg [15:0] data_o, output reg rw_o, output reg valid_o ); @@ -42,35 +40,32 @@ module io_core( always @(posedge clk) begin addr_o <= addr_i; - wdata_o <= wdata_i; - rdata_o <= rdata_i; + data_o <= data_i; rw_o <= rw_i; valid_o <= valid_i; - rdata_o <= rdata_i; - // check if address is valid if( (valid_i) && (addr_i >= BASE_ADDR) && (addr_i <= BASE_ADDR + 7)) begin if(!rw_i) begin // reads case (addr_i) - BASE_ADDR + 0: rdata_o <= {15'b0, picard}; - BASE_ADDR + 1: rdata_o <= {9'b0, data}; - BASE_ADDR + 2: rdata_o <= {6'b0, laforge}; - BASE_ADDR + 3: rdata_o <= {15'b0, troi}; - BASE_ADDR + 4: rdata_o <= {15'b0, kirk}; - BASE_ADDR + 5: rdata_o <= {11'b0, spock}; - BASE_ADDR + 6: rdata_o <= {13'b0, uhura}; - BASE_ADDR + 7: rdata_o <= {15'b0, chekov}; + BASE_ADDR + 0: data_o <= {15'b0, picard}; + BASE_ADDR + 1: data_o <= {9'b0, data}; + BASE_ADDR + 2: data_o <= {6'b0, laforge}; + BASE_ADDR + 3: data_o <= {15'b0, troi}; + BASE_ADDR + 4: data_o <= {15'b0, kirk}; + BASE_ADDR + 5: data_o <= {11'b0, spock}; + BASE_ADDR + 6: data_o <= {13'b0, uhura}; + BASE_ADDR + 7: data_o <= {15'b0, chekov}; endcase end else begin // writes case (addr_i) - BASE_ADDR + 4: kirk <= wdata_i[0]; - BASE_ADDR + 5: spock <= wdata_i[4:0]; - BASE_ADDR + 6: uhura <= wdata_i[2:0]; - BASE_ADDR + 7: chekov <= wdata_i[0]; + BASE_ADDR + 4: kirk <= data_i[0]; + BASE_ADDR + 5: spock <= data_i[4:0]; + BASE_ADDR + 6: uhura <= data_i[2:0]; + BASE_ADDR + 7: chekov <= data_i[0]; endcase end end diff --git a/test/functional_sim/io_core_tb/io_core_tb.sv b/test/functional_sim/io_core_tb/io_core_tb.sv index cc0226c..de350bc 100644 --- a/test/functional_sim/io_core_tb/io_core_tb.sv +++ b/test/functional_sim/io_core_tb/io_core_tb.sv @@ -23,15 +23,13 @@ module io_core_tb; // tb -> io bus logic [15:0] tb_io_addr; - logic [15:0] tb_io_wdata; - logic [15:0] tb_io_rdata; + logic [15:0] tb_io_data; logic tb_io_rw; logic tb_io_valid; // la -> io bus logic [15:0] la_tb_addr; - logic [15:0] la_tb_wdata; - logic [15:0] la_tb_rdata; + logic [15:0] la_tb_data; logic la_tb_rw; logic la_tb_valid; @@ -53,15 +51,13 @@ module io_core_tb; // input port .addr_i(tb_io_addr), - .wdata_i(tb_io_wdata), - .rdata_i(tb_io_rdata), + .data_i(tb_io_data), .rw_i(tb_io_rw), .valid_i(tb_io_valid), // output port .addr_o(la_tb_addr), - .wdata_o(la_tb_wdata), - .rdata_o(la_tb_rdata), + .data_o(la_tb_data), .rw_o(la_tb_rw), .valid_o(la_tb_valid)); @@ -79,8 +75,7 @@ module io_core_tb; test_num = 0; tb_io_addr = 0; - tb_io_rdata = 0; - tb_io_wdata = 0; + tb_io_data = 0; tb_io_rw = 0; tb_io_valid = 0; @@ -101,7 +96,7 @@ module io_core_tb; #`CP tb_io_valid = 0; while (!la_tb_valid) #`CP; - $display(" -> read 0x%h from state reg (addr 0x0000)", la_tb_rdata); + $display(" -> read 0x%h from state reg (addr 0x0000)", la_tb_data); #(10*`CP); diff --git a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv index 4a18616..36288de 100644 --- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv +++ b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv @@ -15,7 +15,7 @@ task read_reg ( #`CP logic_analyzer_tb.tb_la_valid = 0; while (!logic_analyzer_tb.la_tb_valid) #`CP; - data = logic_analyzer_tb.la_tb_rdata; + data = logic_analyzer_tb.la_tb_data; $display(" -> read 0x%h from addr 0x%h (%s)", data, addr, desc); endtask @@ -27,7 +27,7 @@ task write_reg( ); logic_analyzer_tb.tb_la_addr = addr; - logic_analyzer_tb.tb_la_wdata = data; + logic_analyzer_tb.tb_la_data = data; logic_analyzer_tb.tb_la_rw = 1; logic_analyzer_tb.tb_la_valid = 1; #`CP @@ -76,15 +76,13 @@ module logic_analyzer_tb; // tb -> la bus logic [15:0] tb_la_addr; - logic [15:0] tb_la_wdata; - logic [15:0] tb_la_rdata; + logic [15:0] tb_la_data; logic tb_la_rw; logic tb_la_valid; // la -> tb bus logic [15:0] la_tb_addr; - logic [15:0] la_tb_wdata; - logic [15:0] la_tb_rdata; + logic [15:0] la_tb_data; logic la_tb_rw; logic la_tb_valid; @@ -100,15 +98,13 @@ module logic_analyzer_tb; // input port .addr_i(tb_la_addr), - .wdata_i(tb_la_wdata), - .rdata_i(tb_la_rdata), + .data_i(tb_la_data), .rw_i(tb_la_rw), .valid_i(tb_la_valid), // output port .addr_o(la_tb_addr), - .wdata_o(la_tb_wdata), - .rdata_o(la_tb_rdata), + .data_o(la_tb_data), .rw_o(la_tb_rw), .valid_o(la_tb_valid)); @@ -128,8 +124,7 @@ module logic_analyzer_tb; test_num = 0; tb_la_addr = 0; - tb_la_rdata = 0; - tb_la_wdata = 0; + tb_la_data = 0; tb_la_rw = 0; tb_la_valid = 0; diff --git a/test/functional_sim/lut_mem_tb.sv b/test/functional_sim/lut_mem_tb.sv index a54c6b1..a93ae14 100644 --- a/test/functional_sim/lut_mem_tb.sv +++ b/test/functional_sim/lut_mem_tb.sv @@ -12,8 +12,7 @@ module lut_mem_tb; // tb --> mem_1 signals logic [15:0] tb_mem_1_addr; - logic [15:0] tb_mem_1_wdata; - logic [15:0] tb_mem_1_rdata; + logic [15:0] tb_mem_1_data; logic tb_mem_1_rw; logic tb_mem_1_valid; @@ -23,22 +22,19 @@ module lut_mem_tb; ) mem_1 ( .clk(clk), .addr_i(tb_mem_1_addr), - .wdata_i(tb_mem_1_wdata), - .rdata_i(tb_mem_1_rdata), + .data_i(tb_mem_1_data), .rw_i(tb_mem_1_rw), .valid_i(tb_mem_1_valid), .addr_o(mem_1_mem_2_addr), - .wdata_o(mem_1_mem_2_wdata), - .rdata_o(mem_1_mem_2_rdata), + .data_o(mem_1_mem_2_data), .rw_o(mem_1_mem_2_rw), .valid_o(mem_1_mem_2_valid) ); // mem_1 --> mem_2 signals logic [15:0] mem_1_mem_2_addr; - logic [15:0] mem_1_mem_2_wdata; - logic [15:0] mem_1_mem_2_rdata; + logic [15:0] mem_1_mem_2_data; logic mem_1_mem_2_rw; logic mem_1_mem_2_valid; @@ -48,22 +44,19 @@ module lut_mem_tb; ) mem_2 ( .clk(clk), .addr_i(mem_1_mem_2_addr), - .wdata_i(mem_1_mem_2_wdata), - .rdata_i(mem_1_mem_2_rdata), + .data_i(mem_1_mem_2_data), .rw_i(mem_1_mem_2_rw), .valid_i(mem_1_mem_2_valid), .addr_o(mem_2_mem_3_addr), - .wdata_o(mem_2_mem_3_wdata), - .rdata_o(mem_2_mem_3_rdata), + .data_o(mem_2_mem_3_data), .rw_o(mem_2_mem_3_rw), .valid_o(mem_2_mem_3_valid) ); // mem_2 --> mem_3 signals logic [15:0] mem_2_mem_3_addr; - logic [15:0] mem_2_mem_3_wdata; - logic [15:0] mem_2_mem_3_rdata; + logic [15:0] mem_2_mem_3_data; logic mem_2_mem_3_rw; logic mem_2_mem_3_valid; @@ -73,22 +66,19 @@ module lut_mem_tb; ) mem_3 ( .clk(clk), .addr_i(mem_2_mem_3_addr), - .wdata_i(mem_2_mem_3_wdata), - .rdata_i(mem_2_mem_3_rdata), + .data_i(mem_2_mem_3_data), .rw_i(mem_2_mem_3_rw), .valid_i(mem_2_mem_3_valid), .addr_o(mem_3_tb_addr), - .wdata_o(mem_3_tb_wdata), - .rdata_o(mem_3_tb_rdata), + .data_o(mem_3_tb_data), .rw_o(mem_3_tb_rw), .valid_o(mem_3_tb_valid) ); // mem_3 --> tb signals logic [15:0] mem_3_tb_addr; - logic [15:0] mem_3_tb_wdata; - logic [15:0] mem_3_tb_rdata; + logic [15:0] mem_3_tb_data; logic mem_3_tb_rw; logic mem_3_tb_valid; @@ -135,8 +125,7 @@ module lut_mem_tb; mem_3.mem[7] = 16'h0017; tb_mem_1_addr = 0; - tb_mem_1_wdata = 0; - tb_mem_1_rdata = 0; + tb_mem_1_data = 0; tb_mem_1_rw = 0; tb_mem_1_valid = 0; @@ -179,7 +168,7 @@ module lut_mem_tb; test_num = 3; tb_mem_1_addr = 16'h0012; - tb_mem_1_wdata = 16'h0069; + tb_mem_1_data = 16'h0069; tb_mem_1_valid = 1; tb_mem_1_rw = 1; #`CP;