From 1d9e643c053da7710e1831db6d2ec7512fe5a892 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 11 Jan 2024 09:32:36 -0800
Subject: [PATCH 1/4] fix bug in USB PID/VID reporting

---
 src/manta/__init__.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/manta/__init__.py b/src/manta/__init__.py
index 587e4d8..16768f3 100644
--- a/src/manta/__init__.py
+++ b/src/manta/__init__.py
@@ -332,7 +332,7 @@ Supported commands:
 
             # sometimes macOS will enumerate non-serial devices as serial ports,
             # in which case the PID/VID/serial/location/etc are all None
-            pid = f"0x{port.vid:04X}" if port.pid is not None else "None"
+            pid = f"0x{port.pid:04X}" if port.pid is not None else "None"
             vid = f"0x{port.vid:04X}" if port.vid is not None else "None"
 
             print(f" ->  pid: {pid}")

From 74de7f23242dc8e631bd7e7b43b3b9950afbfd02 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 29 Feb 2024 15:17:56 -0500
Subject: [PATCH 2/4] update README to match header

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index 3a02d2b..380eaa4 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 ![](doc/assets/logo.png)
 
-## Manta: An In-Situ Debugging Tool for Programmable Hardware
+## Manta: A configurable and approachable tool for FPGA debugging and rapid prototyping.
 ![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg)
 ![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg)
 ![build_examples](https://github.com/fischermoseley/manta/actions/workflows/build_examples.yml/badge.svg)
@@ -12,4 +12,4 @@
 Manta is a tool for getting information into and out of FPGAs over an interface like UART or Ethernet. It's primarily intended for debugging, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It lets you configure a series of cores on a shared bus via a YAML or JSON file, and then provides a Python API to each core, along with vendor-agnostic Verilog HDL to instantiate them on your FPGA.
 
 For more information check out the docs:
-[https://fischermoseley.github.io/manta](https://fischermoseley.github.io/manta)
\ No newline at end of file
+[https://fischermoseley.github.io/manta](https://fischermoseley.github.io/manta)

From 9a23a40d7e2e1477329f6e7074da5893a2f33060 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 29 Feb 2024 15:19:13 -0500
Subject: [PATCH 3/4] update README formatting

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 380eaa4..e35047a 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 ![](doc/assets/logo.png)
 
-## Manta: A configurable and approachable tool for FPGA debugging and rapid prototyping.
+## Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
 ![functional_simulation](https://github.com/fischermoseley/manta/actions/workflows/functional_simulation.yml/badge.svg)
 ![formal_verification](https://github.com/fischermoseley/manta/actions/workflows/formal_verification.yml/badge.svg)
 ![build_examples](https://github.com/fischermoseley/manta/actions/workflows/build_examples.yml/badge.svg)

From a4d549f6f1fb846889ebdaf4542ac0ea9f4648b2 Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Thu, 29 Feb 2024 15:20:11 -0500
Subject: [PATCH 4/4] update static site to match README formatting

---
 doc/index.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/doc/index.md b/doc/index.md
index b3c88f9..997bb11 100644
--- a/doc/index.md
+++ b/doc/index.md
@@ -1,6 +1,6 @@
 ![](assets/logo.png)
 
-## Manta: An In-Situ Debugging Tool for Programmable Hardware
+## Manta: A Configurable and Approachable Tool for FPGA Debugging and Rapid Prototyping
 
 Manta is a tool for getting information into and out of FPGAs over UART or Ethernet. It's primarily intended for debugging and experimentation, but it's robust enough to be a simple, reliable transport layer between a FPGA and a host machine. It works by letting you configure a series of cores, which live as digital logic on the FPGA and are represented with vendor-agnostic Verilog-2001. The information and behavior of these cores are accessible to the host machine, which presents a Python API to the user. Manta includes the following cores, any number and combination of which may be used at once:
 
@@ -55,4 +55,4 @@ Manta and its source code are released under a [GPLv3 license](https://github.co
     month={may}
     howpublished={\url{https://hdl.handle.net/1721.1/151223}}
 }
-```
\ No newline at end of file
+```