diff --git a/examples/icestick/io_core/run_io_core.py b/examples/icestick/io_core/blinky.py
similarity index 100%
rename from examples/icestick/io_core/run_io_core.py
rename to examples/icestick/io_core/blinky.py
diff --git a/examples/verilog/icestick/io_core_uart/.gitignore b/examples/verilog/icestick/io_core_uart/.gitignore
new file mode 100644
index 0000000..a670a87
--- /dev/null
+++ b/examples/verilog/icestick/io_core_uart/.gitignore
@@ -0,0 +1 @@
+!top_level.sv
\ No newline at end of file
diff --git a/examples/verilog/icestick/io_core_uart/blinky.py b/examples/verilog/icestick/io_core_uart/blinky.py
new file mode 100644
index 0000000..b1fd3d1
--- /dev/null
+++ b/examples/verilog/icestick/io_core_uart/blinky.py
@@ -0,0 +1,16 @@
+from manta import Manta
+from time import sleep
+
+manta = Manta('manta.yaml')
+
+i = 0
+while True:
+    # Turn each LED off
+    for j in range(5):
+        manta.my_io_core.set_probe(f"LED{j}", 0)
+
+    # Turn one LED back on
+    manta.my_io_core.set_probe(f"LED{i}", 1)
+
+    i = (i+1) % 5
+    sleep(0.1)
\ No newline at end of file
diff --git a/examples/verilog/icestick/io_core_uart/build.sh b/examples/verilog/icestick/io_core_uart/build.sh
new file mode 100755
index 0000000..a300d28
--- /dev/null
+++ b/examples/verilog/icestick/io_core_uart/build.sh
@@ -0,0 +1,4 @@
+python3 -m manta gen manta.yaml manta.v
+$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
+$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
+$ICEPACK top_level.asc top_level.bin
\ No newline at end of file
diff --git a/examples/verilog/icestick/io_core_uart/manta.yaml b/examples/verilog/icestick/io_core_uart/manta.yaml
new file mode 100644
index 0000000..162311e
--- /dev/null
+++ b/examples/verilog/icestick/io_core_uart/manta.yaml
@@ -0,0 +1,16 @@
+---
+cores:
+  my_io_core:
+    type: io
+
+    outputs:
+      LED0: 1
+      LED1: 1
+      LED2: 1
+      LED3: 1
+      LED4: 1
+
+uart:
+  port: "/dev/ttyUSB3"
+  baudrate: 115200
+  clock_freq: 12000000
\ No newline at end of file
diff --git a/examples/verilog/icestick/io_core_uart/top_level.pcf b/examples/verilog/icestick/io_core_uart/top_level.pcf
new file mode 100644
index 0000000..d042aa0
--- /dev/null
+++ b/examples/verilog/icestick/io_core_uart/top_level.pcf
@@ -0,0 +1,67 @@
+# Generic iCEstick placement constraints file
+
+# Red LEDs
+set_io LED0 99
+set_io LED1 98
+set_io LED2 97
+set_io LED3 96
+
+# Green LED
+set_io LED4 95
+
+# IrDA port
+#set_io RXD 106
+#set_io TXD 105
+#set_io SD 107
+
+# Pmod connector
+#set_io PIO1_02 78 # Pin 1
+#set_io PIO1_03 79 # Pin 2
+#set_io PIO1_04 80 # Pin 3
+#set_io PIO1_05 81 # Pin 4
+#set_io PIO1_06 87 # Pin 7
+#set_io PIO1_07 88 # Pin 8
+#set_io PIO1_08 90 # Pin 9
+#set_io PIO1_09 91 # Pin 10
+
+# Connector J1
+#set_io PIO0_02 112 # Pin 3
+#set_io PIO0_03 113 # Pin 4
+#set_io PIO0_04 114 # Pin 5
+#set_io PIO0_05 115 # Pin 6
+#set_io PIO0_06 116 # Pin 7
+#set_io PIO0_07 117 # Pin 8
+#set_io PIO0_08 118 # Pin 9
+#set_io PIO0_09 119 # Pin 10
+
+# Connector J3
+#set_io PIO2_17 62 # Pin 3
+#set_io PIO2_16 61 # Pin 4
+#set_io PIO2_15 60 # Pin 5
+#set_io PIO2_14 56 # Pin 6
+#set_io PIO2_13 48 # Pin 7
+#set_io PIO2_12 47 # Pin 8
+#set_io PIO2_11 45 # Pin 9
+#set_io PIO2_10 44 # Pin 10
+
+# FTDI Port B UART
+#set_io DCDn 1
+#set_io DSRn 2
+#set_io DTRn 3
+#set_io CTSn 4
+#set_io RTSn 7
+set_io rs232_tx_ttl 8
+set_io rs232_rx_ttl 9
+
+# SPI
+#set_io SPI_SCK 70
+#set_io SPI_SI 68
+#set_io SPI_SO 67
+#set_io SPI_SS_B 71
+
+# Configuration pins
+#set_io CDONE 65
+#set_io CRESET_B 66
+
+# 12 MHz clock
+set_io clk 21
diff --git a/examples/verilog/icestick/io_core_uart/top_level.sv b/examples/verilog/icestick/io_core_uart/top_level.sv
new file mode 100644
index 0000000..f0740f1
--- /dev/null
+++ b/examples/verilog/icestick/io_core_uart/top_level.sv
@@ -0,0 +1,33 @@
+`default_nettype none
+`timescale 1ns / 1ps
+
+`include "manta.v"
+
+module top_level (
+	input wire clk,
+
+    output logic LED0,
+    output logic LED1,
+    output logic LED2,
+    output logic LED3,
+    output logic LED4,
+
+	input wire rs232_rx_ttl,
+	output logic rs232_tx_ttl
+	);
+
+    manta manta_inst (
+        .clk(clk),
+        .rst(0),
+
+        .rx(rs232_rx_ttl),
+        .tx(rs232_tx_ttl),
+
+        .LED0(LED0),
+        .LED1(LED1),
+        .LED2(LED2),
+        .LED3(LED3),
+        .LED4(LED4));
+endmodule
+
+`default_nettype wire
\ No newline at end of file
diff --git a/examples/verilog/icestick/logic_analyzer_uart/.gitignore b/examples/verilog/icestick/logic_analyzer_uart/.gitignore
new file mode 100644
index 0000000..a670a87
--- /dev/null
+++ b/examples/verilog/icestick/logic_analyzer_uart/.gitignore
@@ -0,0 +1 @@
+!top_level.sv
\ No newline at end of file
diff --git a/examples/verilog/icestick/logic_analyzer_uart/build.sh b/examples/verilog/icestick/logic_analyzer_uart/build.sh
new file mode 100755
index 0000000..a300d28
--- /dev/null
+++ b/examples/verilog/icestick/logic_analyzer_uart/build.sh
@@ -0,0 +1,4 @@
+python3 -m manta gen manta.yaml manta.v
+$YOSYS -p 'synth_ice40 -top top_level -json top_level.json' top_level.sv
+$NEXTPNR_ICE40 --hx1k --json top_level.json --pcf top_level.pcf --asc top_level.asc
+$ICEPACK top_level.asc top_level.bin
\ No newline at end of file
diff --git a/examples/verilog/icestick/logic_analyzer_uart/manta.yaml b/examples/verilog/icestick/logic_analyzer_uart/manta.yaml
new file mode 100644
index 0000000..6422e2e
--- /dev/null
+++ b/examples/verilog/icestick/logic_analyzer_uart/manta.yaml
@@ -0,0 +1,19 @@
+---
+cores:
+  my_logic_analyzer:
+    type: logic_analyzer
+    sample_depth: 256
+
+    probes:
+      probe0: 1
+      probe1: 4
+      probe2: 8
+      probe3: 16
+
+    triggers:
+      - probe2 EQ 3
+
+uart:
+  port: "/dev/ttyUSB3"
+  baudrate: 115200
+  clock_freq: 12000000
\ No newline at end of file
diff --git a/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf b/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf
new file mode 100644
index 0000000..d042aa0
--- /dev/null
+++ b/examples/verilog/icestick/logic_analyzer_uart/top_level.pcf
@@ -0,0 +1,67 @@
+# Generic iCEstick placement constraints file
+
+# Red LEDs
+set_io LED0 99
+set_io LED1 98
+set_io LED2 97
+set_io LED3 96
+
+# Green LED
+set_io LED4 95
+
+# IrDA port
+#set_io RXD 106
+#set_io TXD 105
+#set_io SD 107
+
+# Pmod connector
+#set_io PIO1_02 78 # Pin 1
+#set_io PIO1_03 79 # Pin 2
+#set_io PIO1_04 80 # Pin 3
+#set_io PIO1_05 81 # Pin 4
+#set_io PIO1_06 87 # Pin 7
+#set_io PIO1_07 88 # Pin 8
+#set_io PIO1_08 90 # Pin 9
+#set_io PIO1_09 91 # Pin 10
+
+# Connector J1
+#set_io PIO0_02 112 # Pin 3
+#set_io PIO0_03 113 # Pin 4
+#set_io PIO0_04 114 # Pin 5
+#set_io PIO0_05 115 # Pin 6
+#set_io PIO0_06 116 # Pin 7
+#set_io PIO0_07 117 # Pin 8
+#set_io PIO0_08 118 # Pin 9
+#set_io PIO0_09 119 # Pin 10
+
+# Connector J3
+#set_io PIO2_17 62 # Pin 3
+#set_io PIO2_16 61 # Pin 4
+#set_io PIO2_15 60 # Pin 5
+#set_io PIO2_14 56 # Pin 6
+#set_io PIO2_13 48 # Pin 7
+#set_io PIO2_12 47 # Pin 8
+#set_io PIO2_11 45 # Pin 9
+#set_io PIO2_10 44 # Pin 10
+
+# FTDI Port B UART
+#set_io DCDn 1
+#set_io DSRn 2
+#set_io DTRn 3
+#set_io CTSn 4
+#set_io RTSn 7
+set_io rs232_tx_ttl 8
+set_io rs232_rx_ttl 9
+
+# SPI
+#set_io SPI_SCK 70
+#set_io SPI_SI 68
+#set_io SPI_SO 67
+#set_io SPI_SS_B 71
+
+# Configuration pins
+#set_io CDONE 65
+#set_io CRESET_B 66
+
+# 12 MHz clock
+set_io clk 21
diff --git a/examples/verilog/icestick/logic_analyzer_uart/top_level.sv b/examples/verilog/icestick/logic_analyzer_uart/top_level.sv
new file mode 100644
index 0000000..620be4b
--- /dev/null
+++ b/examples/verilog/icestick/logic_analyzer_uart/top_level.sv
@@ -0,0 +1,38 @@
+`default_nettype none
+`timescale 1ns / 1ps
+
+`include "manta.v"
+
+module top_level (
+	input wire clk,
+
+	input wire rs232_rx_ttl,
+	output logic rs232_tx_ttl
+	);
+
+    logic probe0;
+    logic [3:0] probe1;
+    logic [7:0] probe2;
+    logic [15:0] probe3;
+
+    always @(posedge clk) begin
+        probe0 <= probe0 + 1;
+        probe1 <= probe1 + 1;
+        probe2 <= probe2 + 1;
+        probe3 <= probe3 + 1;
+    end
+
+    manta manta_inst (
+        .clk(clk),
+        .rst(0),
+
+        .rx(rs232_rx_ttl),
+        .tx(rs232_tx_ttl),
+
+        .probe0(probe0),
+        .probe1(probe1),
+        .probe2(probe2),
+        .probe3(probe3));
+endmodule
+
+`default_nettype wire
\ No newline at end of file