From 0132d8fab09f92caf7aca7fec61e0d435891213e Mon Sep 17 00:00:00 2001
From: Fischer Moseley <42497969+fischermoseley@users.noreply.github.com>
Date: Wed, 19 Jul 2023 19:27:12 -0700
Subject: [PATCH] update roadmap

---
 doc/roadmap.md | 18 ++++++++++++++++++
 doc/todo.md    | 41 -----------------------------------------
 mkdocs.yml     |  2 +-
 3 files changed, 19 insertions(+), 42 deletions(-)
 create mode 100644 doc/roadmap.md
 delete mode 100644 doc/todo.md

diff --git a/doc/roadmap.md b/doc/roadmap.md
new file mode 100644
index 0000000..6415503
--- /dev/null
+++ b/doc/roadmap.md
@@ -0,0 +1,18 @@
+# Roadmap
+
+## Prior to v1.0.0 release:
+_targeting August 2023_
+- Clean up UART testbenches, make them actually test things
+- Pull text from thesis into documentation site
+- Update docs with API reference
+- Make super super sure everything works (need hardware for that)
+- Port logic analyzer examples to the icestick
+- __IO Core:__ Clock domain crossing
+- __Logic Analyzer Core:__ CDC, trigger modes, external trigger
+
+## Prior to v1.1.0 release:
+- Fix Ethernet packet format
+- Switch from Scapy to Python sockets library
+
+## Prior to v1.2.0 release:
+- [FuseSoC](https://github.com/fusesoc/fusesoc.github.io) Integration
\ No newline at end of file
diff --git a/doc/todo.md b/doc/todo.md
deleted file mode 100644
index a3d770e..0000000
--- a/doc/todo.md
+++ /dev/null
@@ -1,41 +0,0 @@
-# ToDo
-
-# Deadlines
-- _04/12_ - BRAM Core
-- _04/13_ - Logic Analyzer working with >16 bit inputs. Currently held up by the sample memory, but will be resolved once BRAM core is ruggedized.
-- _04/14_ - CDC in the Logic Analyzer. Should be handled automatically, but just need to test it - probably with a SD card example.
-- _04/15_ - _fischer's day off_
-- _04/16_ - VCD export and .mem export for hardware-in-the-loop
-
-__release to PyPI lists - manta v0.0.1 out__
-
-- _04/17_ - write logic analyzer lab
-- _04/18_ - beta tester round 2, run logic analyzer lab. ethernet tx if there's time
-- _04/19_ - Ethernet TX
-- _04/20_ - Ethernet TX
-- _04/21_ - Ethernet TX
-- _04/22_ - _fischer's day off_
-- _04/23_ - _fischer's day off_
-
-- _04/28/23_ - start writing docs site, move appropriate bits into thesis
-- _05/05/23_ - slack week
-- _05/12/23_ - thesis due
-- _05/19/23_ - thesis actually due
-
-
-## IO Core
-- clock domain crossing
-- add logic for ports >16 bits in width
-
-## Logic Analyzer Core
-- clock domain crossing
-- trigger modes
-- external trigger
-
-
-## Meta
-- consider making manta pass verilator lint - or at least as much of it as possible
-- [opencores](https://opencores.org/projects) listing
-- [fusesoc](https://github.com/fusesoc/fusesoc.github.io)
-- port more examples to the icestorm FPGA
-- hardware-in-the-loop testing?
\ No newline at end of file
diff --git a/mkdocs.yml b/mkdocs.yml
index a95d81f..0d38056 100644
--- a/mkdocs.yml
+++ b/mkdocs.yml
@@ -70,4 +70,4 @@ nav:
     - Developer Reference:
       - System Architecture: system_architecture.md
       - Tools Used: tools_used.md
-      - To Do: todo.md
+      - Roadmap: roadmap.md