with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
simple FET device in extresist. Also: Extended the bloat-all CIF operator
again, allowing the trigger layer for the bloat operation to include both
CIF layers and magic layers (previously only magic layers were supported).
This extension is possible due to the previous extension allowing the
trigger layer and bloating layers to be on separate planes. This operator
extension is useful for tagging geometry that is in the proximity of, but
not overlapping, geometry on another plane.
use name (not part of an array in magic). This was failing in
ext2spice due to code in extflat dealing incorrectly with the
array delimiters. The correction fixes the problem but leaves
the possibility that there could be a conflict between a use
name that is an array and a use name that has the array index
as part of the name.
while reading DEF. To preserve names as much as possible, such
names are now kept. To avoid problems, EFbuild.c and ext2hier
behavior has been changed to only parse entries in a .ext file as
instance arrays if the array notation follows the specific syntax
of [ax:bx:cx][ay:by:cy], letting all other uses of brackets pass
through unaffected.
64 because I overran the 64 array with too many resistclasses in
a techfile. This really should be dynamically allocated; this
requires parsing the line to count tokens and reallocating as
needed (to be done).
a scaling issue in extract) which was caused by the addition of
hierarchical netlist generation. Finding hierarchical connections
requires finding instances by name, so it is vastly better to create a
hash table of instances instead of a linked list.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
8.2.74. Top-level port names are now flagged independently of
any subcircuit port, so they are easier to identify when determining
naming precedence for the net. This makes the code cleaner and
removes the problems arising from non-top-level ports and global
names overriding the subcircuit port names.
the patch was attempting to fix. For node naming, ports were given
precedence over globals. However, this failed to distinguish between
ports on the top level and ports down in the hierarchy. This has now
been fixed. Ports on the hierarchy top level have naming precedence
over everything else; otherwise, the traditional rules of node
naming precedence apply.
Tim Edwards