diff --git a/ext2spice/ext2hier.c b/ext2spice/ext2hier.c index cb4b2b28..8cebd42b 100644 --- a/ext2spice/ext2hier.c +++ b/ext2spice/ext2hier.c @@ -805,6 +805,7 @@ spcdevHierVisit( case DEV_SUBCKT: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: case DEV_MSUBCKT: devchar = 'X'; break; @@ -842,6 +843,7 @@ spcdevHierVisit( case DEV_VERILOGA: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: case DEV_MSUBCKT: fprintf(esSpiceF, "%d", esSbckNum++); break; @@ -884,6 +886,7 @@ spcdevHierVisit( break; case DEV_MSUBCKT: + case DEV_DSUBCKT: /* msubcircuit is "Xnnn drain gate [source [sub]]]" */ /* to more conveniently handle situations where MOSFETs */ /* are modeled by subcircuits with the same pin ordering. */ diff --git a/ext2spice/ext2spice.c b/ext2spice/ext2spice.c index 335c7de0..c9c3ef6f 100644 --- a/ext2spice/ext2spice.c +++ b/ext2spice/ext2spice.c @@ -2697,6 +2697,7 @@ spcdevVisit( case DEV_VERILOGA: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: case DEV_MSUBCKT: break; case DEV_DIODE: @@ -2794,6 +2795,7 @@ spcdevVisit( case DEV_SUBCKT: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: case DEV_MSUBCKT: devchar = 'X'; break; @@ -2835,6 +2837,7 @@ spcdevVisit( case DEV_VERILOGA: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: case DEV_MSUBCKT: fprintf(esSpiceF, "%d", esSbckNum++); break; @@ -2874,6 +2877,7 @@ spcdevVisit( break; case DEV_MSUBCKT: + case DEV_DSUBCKT: /* MOS-like subcircuit is "Xnnn drain gate [source [sub]]" */ /* to more conveniently handle cases where MOS devices are */ @@ -4439,6 +4443,7 @@ parallelDevs( case DEV_VERILOGA: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: break; case DEV_VOLT: diff --git a/extflat/EFbuild.c b/extflat/EFbuild.c index c596c041..56a67118 100644 --- a/extflat/EFbuild.c +++ b/extflat/EFbuild.c @@ -895,6 +895,7 @@ efBuildDevice( case DEV_MSUBCKT: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: argstart = 0; } @@ -976,6 +977,7 @@ efBuildDevice( case DEV_CAPREV: case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: case DEV_MSUBCKT: case DEV_SUBCKT: case DEV_VERILOGA: diff --git a/extflat/EFread.c b/extflat/EFread.c index 11571b41..68a74b76 100644 --- a/extflat/EFread.c +++ b/extflat/EFread.c @@ -50,7 +50,7 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/ const char * const extDevTable[] = {"fet", "mosfet", "asymmetric", "bjt", "devres", "devcap", "devcaprev", "vsource", "diode", "pdiode", "ndiode", "subckt", "rsubckt", "msubckt", "csubckt", - "veriloga", NULL}; + "dsubckt", "veriloga", NULL}; #endif /* @@ -376,6 +376,7 @@ readfile: case DEV_VERILOGA: case DEV_MSUBCKT: case DEV_RSUBCKT: + case DEV_DSUBCKT: case DEV_CSUBCKT: ac = 7; /* Actually can have many arguments, which */ break; /* we will deal with in efBuildDevice(). */ diff --git a/extflat/EFvisit.c b/extflat/EFvisit.c index c7de1040..c10a2d24 100644 --- a/extflat/EFvisit.c +++ b/extflat/EFvisit.c @@ -189,6 +189,7 @@ EFGetLengthAndWidth(dev, lptr, wptr) case DEV_VERILOGA: case DEV_MSUBCKT: case DEV_RSUBCKT: + case DEV_DSUBCKT: case DEV_CSUBCKT: case DEV_DIODE: case DEV_PDIODE: diff --git a/extract/ExtBasic.c b/extract/ExtBasic.c index ad0e3019..5bcbe284 100644 --- a/extract/ExtBasic.c +++ b/extract/ExtBasic.c @@ -57,7 +57,7 @@ static char sccsid[] = "@(#)ExtBasic.c 4.13 MAGIC (Berkeley) 12/5/85"; #ifdef MAGIC_WRAPPER const char * const extDevTable[] = {"fet", "mosfet", "asymmetric", "bjt", "devres", "devcap", "devcaprev", "vsource", "diode", "pdiode", "ndiode", - "subckt", "rsubckt", "msubckt", "csubckt", "veriloga", NULL}; + "subckt", "rsubckt", "msubckt", "csubckt", "dsubckt", "veriloga", NULL}; #endif /* --------------------- Data local to this file ---------------------- */ @@ -2719,6 +2719,7 @@ extOutputDevices(def, transList, outFile) case DEV_DIODE: /* Only handle the optional substrate node */ case DEV_NDIODE: case DEV_PDIODE: + case DEV_DSUBCKT: /* Diode length and width are computed like capacitor */ /* length and width. This operation is expensive, so */ /* do this ONLY if length and width are specified as */ diff --git a/extract/ExtTech.c b/extract/ExtTech.c index fb47d718..8e333a48 100644 --- a/extract/ExtTech.c +++ b/extract/ExtTech.c @@ -205,7 +205,7 @@ static const keydesc keyTable[] = { /* * Table used for parsing the "device" keyword types * - * (Note: "10" for max types in subcircuit is arbitrary---the parser + * (Note: "11" for max types in subcircuit is arbitrary---the parser * ignores max types for DEV_SUBCKT, DEV_MSUBCKT, and DEV_VERILOGA). */ @@ -248,6 +248,9 @@ static const keydesc devTable[] = { {"csubcircuit", DEV_CSUBCKT, 4, 7, "name dev-types terminal-types [sub-types|None sub-node] [options]"}, + {"dsubcircuit", DEV_DSUBCKT, 4, 7, +"name dev-types terminal-types [sub-types|None sub-node] [options]"}, + {"veriloga", DEV_VERILOGA, 3, 11, "name dev-types [N] [term1-types ... termN-types [sub-types|None sub-node]] [options]"}, @@ -2815,6 +2818,7 @@ ExtTechLine(sectionName, argc, argv) case DEV_RSUBCKT: case DEV_CSUBCKT: + case DEV_DSUBCKT: nterm = (dv->k_key == DEV_RSUBCKT) ? 2 : 1; DBTechNoisyNameMask(argv[4], &termtypes[0]); /* terminals */ TTMaskSetMask(allExtractTypes, &termtypes[0]); diff --git a/extract/extract.h b/extract/extract.h index 142b22f6..72748778 100644 --- a/extract/extract.h +++ b/extract/extract.h @@ -55,7 +55,8 @@ extern int ExtDoWarn; /* Bitmask of above */ #define DEV_RSUBCKT 12 /* Resistor-like subcircuit. */ #define DEV_MSUBCKT 13 /* MOSFET-like subcircuit. */ #define DEV_CSUBCKT 14 /* Capacitor-like subcircuit. */ -#define DEV_VERILOGA 15 /* Verilog-A model ("N" component) */ +#define DEV_DSUBCKT 15 /* Diode-like subcircuit. */ +#define DEV_VERILOGA 16 /* Verilog-A model ("N" component) */ /* Device names for .ext file output (new in version 7.2) */ /* (defined in extract/ExtBasic.c *and* extflat/EFread.c) */