From 3b44dacab5cbd7ebe88792a843cb75a2ca2fc4ba Mon Sep 17 00:00:00 2001
From: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon, 28 Mar 2022 22:34:12 -0400
Subject: [PATCH] Corrected a minor issue in "def write" that will ignore a
 wire completely if the width does not match the wire minimum width, rather
 than attempt to cope with it gracefully.

---
 VERSION        | 2 +-
 lef/defWrite.c | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 7f9ff1d6..7129a9fd 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-8.3.281
+8.3.282
diff --git a/lef/defWrite.c b/lef/defWrite.c
index ffe3528b..eccd1ba2 100644
--- a/lef/defWrite.c
+++ b/lef/defWrite.c
@@ -974,6 +974,13 @@ defNetGeometryFunc(tile, plane, defdata)
 	    TxPrintf("Net at (%d, %d) has width %d, default width is %d\n",
 			r.r_xbot, r.r_ybot,
 			(h < w) ? h : w, routeWidth);
+
+	    /* Set orientation based on longest side */
+	    if (h > w)
+	    {
+		orient = GEO_NORTH;
+		midlinex2 = (r.r_xtop + r.r_xbot);
+	    }
 	}
 
 	/* Find the route orientation and centerline endpoint coordinates */