diff --git a/magic/Makefile b/magic/Makefile index 4dc62515..bb38fdcc 100644 --- a/magic/Makefile +++ b/magic/Makefile @@ -39,7 +39,7 @@ tclmagic${SHDLIB_EXT}: ${EXTRA_LIBS} -lc ${LIBS} ${LIB_SPECS} ${LDFLAGS} proto.magicrc: proto.magicrc.in - ${SCPP} ${GR_DFLAGS} ${DFLAGS} proto.magicrc.in > proto.magicrc + ${MCPP} ${GR_DFLAGS} ${DFLAGS} proto.magicrc.in > proto.magicrc install: $(DESTDIR)${INSTALL_BINDIR}/${MODULE}${EXEEXT} $(DESTDIR)${INSTALL_SYSDIR}/.magicrc \ $(DESTDIR)${INSTALL_SYSDIR}/magicps.pro diff --git a/scmos/Makefile b/scmos/Makefile index dd513e1a..dc30a1e8 100644 --- a/scmos/Makefile +++ b/scmos/Makefile @@ -17,9 +17,7 @@ MAGICDIR = .. include ${MAGICDIR}/defs.mak -SC_M4 = ${M4} -#SC_CPP = ${MCPP} -I./extract_template -SC_CPP = ${SCPP} -I./extract_template +SC_PP = ${MCPP} -I./extract_template FILES = mos.7bit.dstyle mos.7bit.std.cmap \ mos.24bit.dstyle mos.24bit.std.cmap \ @@ -61,30 +59,33 @@ install: all ${CP} $$i $(DESTDIR)${INSTALL_SYSDIR}; done scmos.tech: $(OBJS) - sed -e 's/\\/\\\\/' scmos.tech.in > scmos.tech.out - $(SC_CPP) -DV5 -DSTANDARD scmos.tech.out > scmos.tech + $(MSED) scmos.tech.in > scmos.tech.out + $(SC_PP) -DV5 -DSTANDARD scmos.tech.out > scmos.tech $(RM) scmos.tech.out scmos-tm.tech: $(OBJS) - sed -e 's/\\/\\\\/' scmos.tech.in > scmos.tech.out - $(SC_CPP) -DV5 -DHPTECH -DTIGHTMETAL scmos.tech.out > scmos-tm.tech + $(MSED) scmos.tech.in > scmos.tech.out + cat scmos.tech.in > scmos.tech.out + $(SC_PP) -DV5 -DHPTECH -DTIGHTMETAL scmos.tech.out > scmos-tm.tech $(RM) scmos.tech.out scmos-sub.tech: $(OBJS) - sed -e 's/\\/\\\\/' scmos.tech.in > scmos.tech.out - $(SC_CPP) -DV5 -DSUBMICRON scmos.tech.out > scmos-sub.tech + $(MSED) scmos.tech.in > scmos.tech.out + cat scmos.tech.in > scmos.tech.out + $(SC_PP) -DV5 -DSUBMICRON scmos.tech.out > scmos-sub.tech $(RM) scmos.tech.out scmosWR.tech: $(OBJS) - sed -e 's/\\/\\\\/' scmos.tech.in > scmos.tech.out - $(SC_CPP) -DV5 -DSTANDARD -DWELL_ROUTE_CHECK scmos.tech.out > scmosWR.tech + $(MSED) scmos.tech.in > scmos.tech.out + cat scmos.tech.in > scmos.tech.out + $(SC_PP) -DV5 -DSTANDARD -DWELL_ROUTE_CHECK scmos.tech.out > scmosWR.tech $(RM) scmos.tech.out minimum.tech: minimum.tech.in - $(SC_M4) minimum.tech.in > minimum.tech + $(SC_PP) minimum.tech.in > minimum.tech gdsquery.tech: gdsquery.tech.in - $(SC_M4) gdsquery.tech.in > gdsquery.tech + $(SC_PP) gdsquery.tech.in > gdsquery.tech $(CIFin): $(CIFout): diff --git a/scmos/extract_template/scmosExt.tech.in b/scmos/extract_template/scmosExt.tech.in index 9492f356..942cf189 100644 --- a/scmos/extract_template/scmosExt.tech.in +++ b/scmos/extract_template/scmosExt.tech.in @@ -23,8 +23,7 @@ || defined (M1Res) \ || defined (PolyRes) \ || defined (M2Res) \ - || defined (M3Res) \ - || defined (nothing) + || defined (M3Res) THERE_IS_AN_ERROR_SOME_LOCAL_CAPACITANCE_DEFINITIONS_HAVE_ALREADY_BEEN_DEFINED #endif @@ -45,21 +44,20 @@ THERE_IS_AN_ERROR_SOME_LOCAL_CAPACITANCE_DEFINITIONS_HAVE_ALREADY_BEEN_DEFINED #define M3Res (metal3,pad/m3,via2/m3) -#define nothing - /* Use macros for planeorder and sideoverlap for backwards compatibility */ #if defined(V5) -#define planeOrder(l,ord) planeorder l ord +#define planeOrder(name,idx) planeorder name idx #define noplaneOrdering noplaneordering -#define sideOverlap(l1,sep,l2,cap,shield)\ +#define sideOverlap(l1,sep,l2,cap,shield) \ sideoverlap l1 sep l2 cap shield +#define Comma , #else /* V5 */ -#define planeOrder(l,ord) +#define planeOrder(name,idx) #define noplaneOrdering -#define sideOverlap(l1,sep,l2,cap,shield)\ +#define sideOverlap(l1,sep,l2,cap,shield) \ sideoverlap l1 sep l2 cap #endif /* V5 */ diff --git a/scmos/extract_template/scmosExt060_orb.tech.in b/scmos/extract_template/scmosExt060_orb.tech.in index 9620ffad..265e6223 100644 --- a/scmos/extract_template/scmosExt060_orb.tech.in +++ b/scmos/extract_template/scmosExt060_orb.tech.in @@ -52,8 +52,8 @@ style lambda_irsim=0.6(orb_scne12) overlap M1Cap PolyCap 19 perimc M1Cap ~M1Cap 41 - sideOverlap(M1Cap, ~M1Cap, allWell, 41, (PolyCap,PNplusCap)) - sideOverlap(M1Cap, ~M1Cap, PNplusCap, 41, nothing) + sideOverlap(M1Cap, ~M1Cap, allWell, 41, PolyCapCommaPNplusCap) + sideOverlap(M1Cap, ~M1Cap, PNplusCap, 41, ) /* ------------------------------------------------- */ @@ -65,7 +65,7 @@ style lambda_irsim=0.6(orb_scne12) overlap M2Cap M1Cap 14 perimc M2Cap ~M2Cap 42 - sideOverlap(M2Cap, ~M2Cap, allWell, 42, (M1Cap,PolyCap,PNplusCap) ) + sideOverlap(M2Cap, ~M2Cap, allWell, 42, M1CapCommaPolyCapCommaPNplusCap ) sideOverlap(M2Cap, ~M2Cap, PNplusCap, 42, M1Cap) /* ------------------------------------------------- */ diff --git a/scmos/extract_template/scmosExt100.tech.in b/scmos/extract_template/scmosExt100.tech.in index 1ba88042..17a1d823 100644 --- a/scmos/extract_template/scmosExt100.tech.in +++ b/scmos/extract_template/scmosExt100.tech.in @@ -43,7 +43,7 @@ style lambda_irsim=1.0(scna20_orb) areacap poly2,ec/a 50 perimc PolyCap ~PolyCap 80 - sideOverlap(PolyCap, ~PolyCap, allWell, 80, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 80, ) /* ------------------------------------------------- */ @@ -172,7 +172,7 @@ style lambda=1.0(scpe20_orb) overlap PolyCap allWell 57 perimc PolyCap ~PolyCap 168 - sideOverlap(PolyCap, ~PolyCap, allWell, 168, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 168, ) /* ------------------------------------------------- */ diff --git a/scmos/extract_template/scmosExt14b-sub.tech.in b/scmos/extract_template/scmosExt14b-sub.tech.in index 0099dcad..400fc3a6 100644 --- a/scmos/extract_template/scmosExt14b-sub.tech.in +++ b/scmos/extract_template/scmosExt14b-sub.tech.in @@ -56,10 +56,10 @@ style lambda_irsim=0.30 overlap PolyCap allWell 8.2 perimc PolyCap ~PolyCap 12.6 - sideOverlap(PolyCap, ~PolyCap, allWell, 12.6, nothing) - sideOverlap(PolyCap, ~PolyCap, M1Cap, 5.7, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 12.6, ) + sideOverlap(PolyCap, ~PolyCap, M1Cap, 5.7, ) sideOverlap(PolyCap, ~PolyCap, M2Cap, 2.7, M1Cap) - sideOverlap(PolyCap, ~PolyCap, M3Cap, 1.8, (M1Cap,M2Cap)) + sideOverlap(PolyCap, ~PolyCap, M3Cap, 1.8, M1CapCommaM2Cap) sidewall PolyCap ~PolyCap ~PolyCap PolyCap 7.2 /* ------------------------------------------------- */ @@ -72,10 +72,10 @@ style lambda_irsim=0.30 overlap M1Cap PolyCap 5.7 perimc M1Cap ~M1Cap 15 - sideOverlap(M1Cap, ~M1Cap, allWell, 15, (PolyCap,PNplusCap)) - sideOverlap(M1Cap, ~M1Cap, PNplusCap, 17.4, nothing) - sideOverlap(M1Cap, ~M1Cap, PolyCap, 17.4, nothing) - sideOverlap(M1Cap, ~M1Cap, M2Cap, 8.7, nothing) + sideOverlap(M1Cap, ~M1Cap, allWell, 15, PolyCapCommaPNplusCap) + sideOverlap(M1Cap, ~M1Cap, PNplusCap, 17.4, ) + sideOverlap(M1Cap, ~M1Cap, PolyCap, 17.4, ) + sideOverlap(M1Cap, ~M1Cap, M2Cap, 8.7, ) sideOverlap(M1Cap, ~M1Cap, M3Cap, 4.8, M2Cap) sidewall M1Cap ~M1Cap ~M1Cap M1Cap 19.2 @@ -90,11 +90,11 @@ style lambda_irsim=0.30 overlap M2Cap M1Cap 3.5 perimc M2Cap ~M2Cap 12.3 - sideOverlap(M2Cap, ~M2Cap, allWell, 12.3, (M1Cap,PolyCap,PNplusCap) ) + sideOverlap(M2Cap, ~M2Cap, allWell, 12.3, M1CapCommaPolyCapCommaPNplusCap ) sideOverlap(M2Cap, ~M2Cap, PNplusCap, 12.9, M1Cap) sideOverlap(M2Cap, ~M2Cap, PolyCap, 12.9, M1Cap) - sideOverlap(M2Cap, ~M2Cap, M1Cap, 15, nothing) - sideOverlap(M2Cap, ~M2Cap, M3Cap, 10.8, nothing) + sideOverlap(M2Cap, ~M2Cap, M1Cap, 15, ) + sideOverlap(M2Cap, ~M2Cap, M3Cap, 10.8, ) sidewall M2Cap ~M2Cap ~M2Cap M2Cap 21.6 /* ------------------------------------------------- */ @@ -109,11 +109,11 @@ style lambda_irsim=0.30 overlap M3Cap M2Cap 3.3 perimc M3Cap ~M3Cap 12.3 - sideOverlap(M3Cap, ~M3Cap, allWell, 12.3, (PNplusCap,PolyCap,M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PNplusCap, 12.9, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PolyCap, 12.9, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M1Cap, 15.3, (M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M2Cap, 19.2, nothing) + sideOverlap(M3Cap, ~M3Cap, allWell, 12.3, PNplusCapCommaPolyCapCommaM1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PNplusCap, 12.9, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PolyCap, 12.9, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, M1Cap, 15.3, M2Cap) + sideOverlap(M3Cap, ~M3Cap, M2Cap, 19.2, ) sidewall M3Cap ~M3Cap ~M3Cap M3Cap 34.3 /* ------------------------------------------------- */ diff --git a/scmos/extract_template/scmosExt14b-tm.tech.in b/scmos/extract_template/scmosExt14b-tm.tech.in index 3de6d854..8937cdeb 100644 --- a/scmos/extract_template/scmosExt14b-tm.tech.in +++ b/scmos/extract_template/scmosExt14b-tm.tech.in @@ -56,10 +56,10 @@ style lambda_irsim=0.35 overlap PolyCap allWell 11.1 perimc PolyCap ~PolyCap 14.7 - sideOverlap(PolyCap, ~PolyCap, allWell, 14.7, nothing) - sideOverlap(PolyCap, ~PolyCap, M1Cap, 6.7, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 14.7, ) + sideOverlap(PolyCap, ~PolyCap, M1Cap, 6.7, ) sideOverlap(PolyCap, ~PolyCap, M2Cap, 3.2, M1Cap) - sideOverlap(PolyCap, ~PolyCap, M3Cap, 2.1, (M1Cap,M2Cap)) + sideOverlap(PolyCap, ~PolyCap, M3Cap, 2.1, M1CapCommaM2Cap) sidewall PolyCap ~PolyCap ~PolyCap PolyCap 8.4 /* ------------------------------------------------- */ @@ -72,10 +72,10 @@ style lambda_irsim=0.35 overlap M1Cap PolyCap 7.7 perimc M1Cap ~M1Cap 17.5 - sideOverlap(M1Cap, ~M1Cap, allWell, 17.5, (PolyCap,PNplusCap)) - sideOverlap(M1Cap, ~M1Cap, PNplusCap, 20.3, nothing) - sideOverlap(M1Cap, ~M1Cap, PolyCap, 20.3, nothing) - sideOverlap(M1Cap, ~M1Cap, M2Cap, 10.2, nothing) + sideOverlap(M1Cap, ~M1Cap, allWell, 17.5, PolyCapCommaPNplusCap) + sideOverlap(M1Cap, ~M1Cap, PNplusCap, 20.3, ) + sideOverlap(M1Cap, ~M1Cap, PolyCap, 20.3, ) + sideOverlap(M1Cap, ~M1Cap, M2Cap, 10.2, ) sideOverlap(M1Cap, ~M1Cap, M3Cap, 5.6, M2Cap) sidewall M1Cap ~M1Cap ~M1Cap M1Cap 22.4 @@ -90,11 +90,11 @@ style lambda_irsim=0.35 overlap M2Cap M1Cap 4.7 perimc M2Cap ~M2Cap 14.4 - sideOverlap(M2Cap, ~M2Cap, allWell, 14.4, (M1Cap,PolyCap,PNplusCap) ) + sideOverlap(M2Cap, ~M2Cap, allWell, 14.4, M1CapCommaPolyCapCommaPNplusCap ) sideOverlap(M2Cap, ~M2Cap, PNplusCap, 15.1, M1Cap) sideOverlap(M2Cap, ~M2Cap, PolyCap, 15.1, M1Cap) - sideOverlap(M2Cap, ~M2Cap, M1Cap, 17.5, nothing) - sideOverlap(M2Cap, ~M2Cap, M3Cap, 12.6, nothing) + sideOverlap(M2Cap, ~M2Cap, M1Cap, 17.5, ) + sideOverlap(M2Cap, ~M2Cap, M3Cap, 12.6, ) sidewall M2Cap ~M2Cap ~M2Cap M2Cap 25.2 /* ------------------------------------------------- */ @@ -109,11 +109,11 @@ style lambda_irsim=0.35 overlap M3Cap M2Cap 4.5 perimc M3Cap ~M3Cap 14.4 - sideOverlap(M3Cap, ~M3Cap, allWell, 14.4, (PNplusCap,PolyCap,M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PNplusCap, 15.1, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PolyCap, 15.1, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M1Cap, 17.9, (M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M2Cap, 22.4, nothing) + sideOverlap(M3Cap, ~M3Cap, allWell, 14.4, PNplusCapCommaPolyCapCommaM1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PNplusCap, 15.1, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PolyCap, 15.1, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, M1Cap, 17.9, M2Cap) + sideOverlap(M3Cap, ~M3Cap, M2Cap, 22.4, ) sidewall M3Cap ~M3Cap ~M3Cap M3Cap 40 /* ------------------------------------------------- */ diff --git a/scmos/extract_template/scmosExt26b-sub.tech.in b/scmos/extract_template/scmosExt26b-sub.tech.in index 9bf9de6a..a636b162 100644 --- a/scmos/extract_template/scmosExt26b-sub.tech.in +++ b/scmos/extract_template/scmosExt26b-sub.tech.in @@ -47,10 +47,10 @@ style lambda_irsim=0.4 overlap PolyCap allWell 10 perimc PolyCap ~PolyCap 18 - sideOverlap(PolyCap, ~PolyCap, allWell, 18, nothing) - sideOverlap(PolyCap, ~PolyCap, M1Cap, 8, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 18, ) + sideOverlap(PolyCap, ~PolyCap, M1Cap, 8, ) sideOverlap(PolyCap, ~PolyCap, M2Cap, 5, M1Cap) - sideOverlap(PolyCap, ~PolyCap, M3Cap, 3, (M1Cap,M2Cap)) + sideOverlap(PolyCap, ~PolyCap, M3Cap, 3, M1CapCommaM2Cap) sidewall PolyCap ~PolyCap ~PolyCap PolyCap 9 /* ------------------------------------------------- */ @@ -63,10 +63,10 @@ style lambda_irsim=0.4 overlap M1Cap PolyCap 9 perimc M1Cap ~M1Cap 18 - sideOverlap(M1Cap, ~M1Cap, allWell, 18, (PolyCap,PNplusCap)) - sideOverlap(M1Cap, ~M1Cap, PNplusCap, 20, nothing) - sideOverlap(M1Cap, ~M1Cap, PolyCap, 20, nothing) - sideOverlap(M1Cap, ~M1Cap, M2Cap, 10, nothing) + sideOverlap(M1Cap, ~M1Cap, allWell, 18, PolyCapCommaPNplusCap) + sideOverlap(M1Cap, ~M1Cap, PNplusCap, 20, ) + sideOverlap(M1Cap, ~M1Cap, PolyCap, 20, ) + sideOverlap(M1Cap, ~M1Cap, M2Cap, 10, ) sideOverlap(M1Cap, ~M1Cap, M3Cap, 6, M2Cap) sidewall M1Cap ~M1Cap ~M1Cap M1Cap 22 @@ -81,11 +81,11 @@ style lambda_irsim=0.4 overlap M2Cap M1Cap 6 perimc M2Cap ~M2Cap 15 - sideOverlap(M2Cap, ~M2Cap, allWell, 15, (M1Cap,PolyCap,PNplusCap) ) + sideOverlap(M2Cap, ~M2Cap, allWell, 15, M1CapCommaPolyCapCommaPNplusCap ) sideOverlap(M2Cap, ~M2Cap, PNplusCap, 16, M1Cap) sideOverlap(M2Cap, ~M2Cap, PolyCap, 16, M1Cap) - sideOverlap(M2Cap, ~M2Cap, M1Cap, 18, nothing) - sideOverlap(M2Cap, ~M2Cap, M3Cap, 8, nothing) + sideOverlap(M2Cap, ~M2Cap, M1Cap, 18, ) + sideOverlap(M2Cap, ~M2Cap, M3Cap, 8, ) sidewall M2Cap ~M2Cap ~M2Cap M2Cap 26 /* ------------------------------------------------- */ @@ -100,11 +100,11 @@ style lambda_irsim=0.4 overlap M3Cap M2Cap 6 perimc M3Cap ~M3Cap 14 - sideOverlap(M3Cap, ~M3Cap, allWell, 14, (PNplusCap,PolyCap,M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PNplusCap, 14, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PolyCap, 14, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M1Cap, 16, (M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M2Cap, 20, nothing) + sideOverlap(M3Cap, ~M3Cap, allWell, 14, PNplusCapCommaPolyCapCommaM1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PNplusCap, 14, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PolyCap, 14, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, M1Cap, 16, M2Cap) + sideOverlap(M3Cap, ~M3Cap, M2Cap, 20, ) sidewall M3Cap ~M3Cap ~M3Cap M3Cap 40 /* ------------------------------------------------- */ diff --git a/scmos/extract_template/scmosExt26b.tech.in b/scmos/extract_template/scmosExt26b.tech.in index f9d22162..3d7ebe59 100644 --- a/scmos/extract_template/scmosExt26b.tech.in +++ b/scmos/extract_template/scmosExt26b.tech.in @@ -52,10 +52,10 @@ style lambda_irsim=0.5 overlap PolyCap allWell 15 perimc PolyCap ~PolyCap 22 - sideOverlap(PolyCap, ~PolyCap, allWell, 22, nothing) - sideOverlap(PolyCap, ~PolyCap, M1Cap, 10, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 22, ) + sideOverlap(PolyCap, ~PolyCap, M1Cap, 10, ) sideOverlap(PolyCap, ~PolyCap, M2Cap, 6, M1Cap) - sideOverlap(PolyCap, ~PolyCap, M3Cap, 4, (M1Cap,M2Cap)) + sideOverlap(PolyCap, ~PolyCap, M3Cap, 4, M1CapCommaM2Cap) sidewall PolyCap ~PolyCap ~PolyCap PolyCap 11 /* ------------------------------------------------- */ @@ -68,10 +68,10 @@ style lambda_irsim=0.5 overlap M1Cap PolyCap 14 perimc M1Cap ~M1Cap 22 - sideOverlap(M1Cap, ~M1Cap, allWell, 22, (PolyCap,PNplusCap)) - sideOverlap(M1Cap, ~M1Cap, PNplusCap, 25, nothing) - sideOverlap(M1Cap, ~M1Cap, PolyCap, 25, nothing) - sideOverlap(M1Cap, ~M1Cap, M2Cap, 12, nothing) + sideOverlap(M1Cap, ~M1Cap, allWell, 22, PolyCapCommaPNplusCap) + sideOverlap(M1Cap, ~M1Cap, PNplusCap, 25, ) + sideOverlap(M1Cap, ~M1Cap, PolyCap, 25, ) + sideOverlap(M1Cap, ~M1Cap, M2Cap, 12, ) sideOverlap(M1Cap, ~M1Cap, M3Cap, 7, M2Cap) sidewall M1Cap ~M1Cap ~M1Cap M1Cap 27 @@ -86,11 +86,11 @@ style lambda_irsim=0.5 overlap M2Cap M1Cap 9 perimc M2Cap ~M2Cap 18 - sideOverlap(M2Cap, ~M2Cap, allWell, 18, (M1Cap,PolyCap,PNplusCap) ) + sideOverlap(M2Cap, ~M2Cap, allWell, 18, M1CapCommaPolyCapCommaPNplusCap ) sideOverlap(M2Cap, ~M2Cap, PNplusCap, 19, M1Cap) sideOverlap(M2Cap, ~M2Cap, PolyCap, 20, M1Cap) - sideOverlap(M2Cap, ~M2Cap, M1Cap, 23, nothing) - sideOverlap(M2Cap, ~M2Cap, M3Cap, 10, nothing) + sideOverlap(M2Cap, ~M2Cap, M1Cap, 23, ) + sideOverlap(M2Cap, ~M2Cap, M3Cap, 10, ) sidewall M2Cap ~M2Cap ~M2Cap M2Cap 33 /* ------------------------------------------------- */ @@ -105,11 +105,11 @@ style lambda_irsim=0.5 overlap M3Cap M2Cap 9 perimc M3Cap ~M3Cap 17 - sideOverlap(M3Cap, ~M3Cap, allWell, 17, (PNplusCap,PolyCap,M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PNplusCap, 17, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, PolyCap, 17, (M1Cap,M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M1Cap, 20, (M2Cap)) - sideOverlap(M3Cap, ~M3Cap, M2Cap, 25, nothing) + sideOverlap(M3Cap, ~M3Cap, allWell, 17, PNplusCapCommaPolyCapCommaM1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PNplusCap, 17, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, PolyCap, 17, M1CapCommaM2Cap) + sideOverlap(M3Cap, ~M3Cap, M1Cap, 20, M2Cap) + sideOverlap(M3Cap, ~M3Cap, M2Cap, 25, ) sidewall M3Cap ~M3Cap ~M3Cap M3Cap 50 /* ------------------------------------------------- */ diff --git a/scmos/extract_template/scmosExt34.tech.in b/scmos/extract_template/scmosExt34.tech.in index 2909f0db..c0dca915 100644 --- a/scmos/extract_template/scmosExt34.tech.in +++ b/scmos/extract_template/scmosExt34.tech.in @@ -43,8 +43,8 @@ style lambda_irsim=0.6(hp) overlap PolyCap allWell 28 perimc PolyCap ~PolyCap 38 - sideOverlap(PolyCap, ~PolyCap, allWell, 38, nothing) - sideOverlap(PolyCap, ~PolyCap, M1Cap, 34, nothing) + sideOverlap(PolyCap, ~PolyCap, allWell, 38, ) + sideOverlap(PolyCap, ~PolyCap, M1Cap, 34, ) sideOverlap(PolyCap, ~PolyCap, M2Cap, 27, M1Cap) sidewall PolyCap ~PolyCap ~PolyCap PolyCap 15 @@ -57,10 +57,10 @@ style lambda_irsim=0.6(hp) overlap M1Cap PolyCap 46 perimc M1Cap ~M1Cap 33 - sideOverlap(M1Cap, ~M1Cap, allWell, 33, (PolyCap,PNplusCap)) - sideOverlap(M1Cap, ~M1Cap, PNplusCap, 33, nothing) - sideOverlap(M1Cap, ~M1Cap, PolyCap, 33, nothing) - sideOverlap(M1Cap, ~M1Cap, M2Cap, 28, nothing) + sideOverlap(M1Cap, ~M1Cap, allWell, 33, PolyCapCommaPNplusCap) + sideOverlap(M1Cap, ~M1Cap, PNplusCap, 33, ) + sideOverlap(M1Cap, ~M1Cap, PolyCap, 33, ) + sideOverlap(M1Cap, ~M1Cap, M2Cap, 28, ) sidewall M1Cap ~M1Cap ~M1Cap M1Cap 27 /* ------------------------------------------------- */ @@ -74,10 +74,10 @@ style lambda_irsim=0.6(hp) overlap M2Cap M1Cap 30 perimc M2Cap ~M2Cap 22 - sideOverlap(M2Cap, ~M2Cap, allWell, 22, (M1Cap,PolyCap,PNplusCap) ) + sideOverlap(M2Cap, ~M2Cap, allWell, 22, M1CapCommaPolyCapCommaPNplusCap ) sideOverlap(M2Cap, ~M2Cap, PNplusCap, 20, M1Cap) sideOverlap(M2Cap, ~M2Cap, PolyCap, 22, M1Cap) - sideOverlap(M2Cap, ~M2Cap, M1Cap, 28, nothing) + sideOverlap(M2Cap, ~M2Cap, M1Cap, 28, ) sidewall M2Cap ~M2Cap ~M2Cap M2Cap 33 /* ------------------------------------------------- */ diff --git a/scmos/test.out b/scmos/test.out index 5213039d..e69de29b 100644 --- a/scmos/test.out +++ b/scmos/test.out @@ -1,3256 +0,0 @@ -/* --------------------------------------------------------------------* - * * - * scmos.tech -- MOSIS Scalable CMOS (SCMOS) Magic technology file. * - * * - * MOSIS distribution Version 8.2 * - * * - * Defines the MOSIS 0.6/0.8/1.0/1.2/2.0 micron Scalable CMOS * - * (SCMOS) technology. * - * * - * (C) Copyright 1992, 1993, 1994, 1995 by * - * * - * Jen-I Pi pi@isi.edu * - * The MOSIS Service * - * USC Information Sciences Institute * - * 4676 Admiralty Way * - * Marina del Rey, CA 90292 * - * voice: (310) 822-1511 x640, fax: (310)823-5624 * - * * - * All Rights Reserved. * - * Last Modified Date: 04/26/1995 * - * * - * Permission to use, copy, modify, and distribute this technology * - * file and its associated documentation for any purpose and without * - * fee is hereby granted, provided that the above copyright notice * - * appears in all copies and that both that copyright notice and this * - * permission notice appear in supporting documentation, and that the * - * name of the University of Southern California not be used in * - * advertising or publicity pertaining to distribution of this * - * technology file without specific, written prior permission. * - * The University of Southern California makes no representations * - * about the suitability of this technology file for any purpose. * - * This technology file is provided "as is" without express or implied * - * warranty and the University of Southern California retains the * - * right to change its content at any time without notice any other * - * party. * - * * - * THE UNIVERSITY OF SOUTHERN CALIFORNIA DISCLAIMS ALL WARRANTIES WITH * - * REGARD TO THIS TECHNOLOGY FILE, INCLUDING ALL IMPLIED WARRANTIES OF * - * MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE UNIVERSITY OF * - * SOUTHERN CALIFORNIA BE LIABLE FOR ANY SPECIAL, INDIRECT OR * - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS * - * OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, * - * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * - * CONNECTION WITH THE USE OR PERFORMANCE OF THIS TECHNOLOGY FILE. * - * * - * ------------------------------------------------------------------- */ - -/* --------------------------------------------------------------------* - * Some of the characteristics of this technology are: * - * * - * 1. 3 levels of metal - for HP's CMOS26B (lambda=0.5) and CMOS26G * - * (lambda=0.4) and CMOS14TB (lambda=0.35 or 0.3) processes * - * 3 levels of metal stack via - for IBM's CMSX2185 (lambda=0.4) * - * process * - * 2 levels of metal interconnection for all other technologies * - * 2. 2 levels of poly - for ORBIT's low-noise analog process * - * second poly is used for poly-capacitor or electrode fet (efet) * - * 3. Vertical NPN transistor, BCCD device, Floating-gate device for * - * ORBIT's low-noise anaolog process * - * 4. All contacts are composite (with the necessary enclosure) * - * 5. No stacked contacts (all contacts are to 1st-level metal) * - * 6. An open layer is added for fabrication of micromachined devices * - * as in Janet C. Marshall's paper in IEEE Circuit and Devices, * - * Vol. 8, N0. 6, 1992. * - * This layer is currently NOT available for standard MOSIS SCMOS * - * techonology installation. You need to define OPEN with the C- * - * preprocessor for installation. See README file for detail... * - * 7 A pstop layer is used also in micromachineing device fabrication * - * to stop the EDP etchant as used in Marshall's article. * - * 8 A Cap-well (cwell) for HP's CMOS34 (lambda=0.6) process, It is * - * used for consctruction of linear capacitors * - * Must be drawn explicitly * - * 9. Wells (Pwell or Nwell) can be implicit or explicit in the layout * - * and both types of diffusion must have well contacts * - *10. Painting Nwell over N-type diffusion will result in P-type * - * diffusion * - *11. Scalable with Default to be 2.0 micron rules for Nwell process * - *12. Substrate contacts must be 3 units away from gates * - *13. Stacked via supported through special compiled option -DSTACKVIA * - * for IBM process. * - * * - * Revision 8.2.8 (pi) * - * fix CCD CIF input style for "bd" layer. * - * 12/13/95 pi@isi.edu * - * Revision 8.2.7 (pi) * - * Add Magic 6.4.4 new extraction plane orders. * - * 07/25/95 pi@isi.edu * - * Revision 8.2.5 (pi) * - * Fix some typos... * - * 05/12/95 pi@isi.edu * - * Revision 8.2.4 (pi) * - * Fix CBA generation for pbase and add extension rules for pbase * - * as resistors. * - * Gratitude goes to Tetsuya Kajita (kaj@ssac.yamatake.co.jp) * - * 04/26/95 pi@isi.edu * - * Revision 8.2.3 (pi) * - * fix for SUBMICRON DRC rule. * - * Thanks goes to Toby Schaffer (jtschaff@eos.ncsu.edu) * - * 04/06/95 pi@isi.edu * - * Revision 8.2.2 (pi) * - * add XP GDS official number to fix CIF input problem for "pad". * - * Thanks goes to Brian Kingsbury (bedk@ICSI.Berkeley.EDU). * - * 04/03/95 pi@isi.edu * - * Revision 8.2.1 (pi) * - * Some fixes for CMOS14B CIF output section. * - * 03/21/95 pi@isi.edu * - * Revision 8.2.0 (pi) * - * support for HP CMOS26G and CMOS14TB process. * - * 03/15/95 pi@isi.edu * - * Revision 8.1.1 (pi) * - * add connection of "ndiff" to "psd". Thank goes to Alireza Moini* - * (moini@eleceng.adelaide.edu.au). * - * 12/21/94 pi@isi.edu * - * Revision 8.1.0 (pi) * - * major revision of bipolar transistor rules. It now support * - * both ORBIT 2.0 and 1.2 micron processes. NOTE: active layer * - * for pbase is now generated in CIF file explicitly. * - * 10/31/94 pi@isi.edu * - * Revision 8.0.7 (pi) * - * remove both VTI and IBM support * - * 10/10/94 pi@isi.edu * - * Revision 8.0.7 (pi) * - * compose for high-voltage transistors corrected. Thank goes to * - * Bob Durie (bobd@ee.cornell.edu) * - * 8/25/94 pi@isi.edu * - * Revision 8.0.6 (pi) * - * DRC rule 2.2 add allNOhmic to allNOhmic and allPOhmic to * - * allPOhmic rule. Thank goes to Shih-Lien Lu. * - * (sllu@caleb.ECE.ORST.EDU) * - * 6/28/94 pi@isi.edu * - * Revision 8.0.5 (pi) * - * DRC rule 3.5 reverse back to old style to avoid a mischeck on * - * corners. Thank goes to Wen-King Su. * - * (wen-king@vlsi.cs.caltech.edu) * - * 4/20/94 pi@isi.edu * - * Revision 8.0.4 (pi) * - * SCPE20(ORB) extraction P-well sheet resistance fixed. Thank * - * goes to Nagendra Shivakumar (nshivaku@phyast.nhn.uoknor.edu). * - * 3/04/94 pi@isi.edu * - * Revision 8.0.3 (pi) * - * Wellcap drawing problem fixed. Thank goes to Mario Aranha * - * (mario@cad4.lbl.gov). * - * 2/03/94 pi@isi.edu * - * Revision 8.0.2 (pi) * - * CIF read fix for linear capacitor. Thank goes to Issy Kipnis * - * (kipnis@cad4.lbl.gov). * - * 2/03/94 pi@isi.edu * - * Revision 8.0.1 (pi) * - * DRC updates for separate diffusion width check. Thank goes to * - * John Poulton (jp@cs.unc.edu). * - * 10/04/93 pi@isi.edu * - * Revision 8.0.0 (pi) * - * DRC revision 8 installed and layer support for High-Voltage * - * MOSFETs for SCNA16 process. * - * 10/04/93 pi@isi.edu * - * Revision 7.4.0 (pi) * - * Brand new extraction section and other fixes :-) * - * 10/01/93 pi@isi.edu * - * Revision 7.3.3 (pi) * - * pbc surrounding rule fixed. 4.1.c fixed also * - * 6/01/93 pi@isi.edu * - * Revision 7.3.2 (pi) * - * exchnage CCD and CBA calma (GDS) number to the correct setting * - * 4/27/93 pi@isi.edu * - * Revision 7.3.1 (pi) * - * Various DRC rule changes contributed by Barry Boes at AuE * - * (boes@corona.AuE.com). * - * allNDiff/allPOhmic in connection section update, thanks go to * - * Brian Kingsbury from Bekerley (bedk@icsi.berkeley.edu). * - * 3/30/93 pi@isi.edu * - * Revision 7.3.0 (pi) * - * add three new layers intended for ESD preotection devices * - * remove the temporary "pad2" layer, now all pads use "pad" * - * CIFin and CIFout now in templates, thank goes to Shih-Lien Lu * - * at Origon State Univ. sllu@caleb.ECE.ORST.EDU. * - * Some design rule changes (relabeling for doc)... * - * 3/19/93 pi@isi.edu * - * Revision 7.2.2 (pi) * - * change all "bloat-min" select generation back to "bloat-or" * - * restore all lambda=0.8 style since some people use ORBIT's run * - * though MOSIS does NOT provide HP's process anymore * - * 3/09/93 pi@isi.edu * - * Revision 7.2.1 (pi) * - * add missing Cifinput "pbase" layer for lambda=1.0(oldnwell) * - * style. Thank goes to Brian Von Herzen at Synaptics, Inc. * - * 2/18/93 pi@isi.edu * - * Revision 7.2.0 (pi) * - * A serious bug in CIF well generation is fixed... * - * 1/14/93 pi@isi.edu * - * Revision 7.1.4 (pi) * - * Remove lambda=1.5 and lambda=0.8 technology which are not * - * provided by MOSIS any more. * - * 1/12/93 pi@isi.edu * - * Revision 7.1.3 (pi) * - * Add pstop layer and the corresponding CIFin CIFout stuff * - * Reverse the last change about CCA layer under pad for CMOS26B * - * 1/08/93 pi@isi.edu * - * Revision 7.1.2 (pi) * - * Various problem fix... and make the "open" layer as an option * - * Reverse the last change about CCA layer under pad for CMOS26B * - * 12/29/92 pi@isi.edu * - * Revision 7.1.1 (pi) * - * A series bug fix for HP's CMOS26B pad layers - remove CCA CIF * - * layer. Thank goes to ndu@aue.com * - * 12/12/92 pi@isi.edu * - * Revision 7.1.0 (pi) * - * A new layer "open" for micromachined device fabracation. * - * Thanks goes to Janet Marchall from NIST. * - * (marshall@sed.eeel.nist.gov) * - * 12/15/92 pi@isi.edu * - * Revision 7.0.4 (pi) * - * C-preprocessing fix. Thanks goes to Jeffrey C. Gealow form * - * MIT (jgealow@mtl.mit.edu). * - * 10/20/92 pi@isi.edu * - * Revision 7.0.3 (pi) * - * Colorversatec support. Thanks got to Jeffrey C. Gealow form * - * MIT (jgealow@mtl.mit.edu). * - * 10/8/92 pi@isi.edu * - * Revision 7.0.2 (pi) * - * Separate 'spacing allWell...' rule into two rules to avoid * - * well adjacency problem... * - * 10/2/92 pi@isi.edu * - * Revision 7.0.1 (pi) * - * CIFoutput for "pad2" layer, CCA contact fix, CIFinput for HP's * - * 1.0 um process... * - * 9/28/92 pi@isi.edu * - * Revision 7.0 (pi) * - * Major revision which includes * - * HP's cap_well and well-capacitance, NPN & BCCD DRC rules... * - * 9/22/92 pi@isi.edu * - * Revision 6.2.0 (pi) * - * Merging 'scmos26.tech' into scmos.tech * - * 9/7/92 pi@isi.edu * - * Revision 6.1.4 (pi) * - * Select CIF layers generation is revised based on Brian * - * Kingsbury's (bedk@icsi.berkeley.edu) notice of inconsistency * - * 9/4/92 pi@isi.edu * - * Revision 6.1.3 (pi) * - * Install MITRE's (Mike Butler) fix for CIFinput "cap" layer and * - * poly1/poly2 crossing in DRC section * - * 9/3/92 pi@isi.edu * - * Revision 6.1.2 (pi) * - * Fixed metal2 contact on falt surface bug for poly2 layer * - * 8/3/92 pi@lepton.isi.edu * - * Revision 6.1.1 (pi) * - * fixed CIFoutput CSP layer bug for lambda=0.8(gen) technology * - * 4/13/92 pi@lepton.isi.edu * - * Revision 6.1.0 (pi) * - * add implant plane for Buried CCD devices * - * both cifin and cifoutput are changed correspondingly * - * Revision 6.0.2 (pi) * - * remove bug for nbdc not generate CMF in cifoutput section * - * Revision 6.0.1 (sllu) * - * added CX for collector layer * - * Revised for Magic Version 6. * - * Revision 6.0 90/05/11 20:12:34 pi * - * include color versatech support * - * eliminated active2 plane * - * (rule version # 5.01 (S. Lu) = rule 5.0 + mod. for cc spacing * - * (rule version # 5.0 (Shih-Lien Lu sllu@MOSIS.EDU) 8/15/89) * - * (rule 5.0 = rule 4.01 + new layers for analog process * - * (rule 4.01 = rule 4.0 + comments + cifout style lambda=0.8(pwell) * - * (correction made by L. McMurchie of UW) * - * (rule 4.0 = rule 3.1 + new layer : electrode) * - * (rule 3.1 = rule 3.0 + new cifout method for select layers ) * - * (design can be more compact now with this version ) * - * (layout should be upward compatible:: you old layout will not) * - * (flag any drc violations) * - * (rule 3.0 = rule 2.0 + rev #6 + new cifin section for new nwell) * - * * - * (rule version # 2.0 10/28/87) * - * (rule 2.0 = rule 1.9 + modification to extract section * - * (rule 1.9 = rule 1.82 + additions of two more CIF in/output styles * - * (rule 1.82 = rule 1.81+ modification of drc #4.1 & cifoutput of * - * wells * - * (rule 1.81 = rule 1.8 + modification on line 1761 * - * (rule 1.8 = rule 1.7 + Rev 5 of the SCMOS rules) * - * (difference from rule 1.7: * - * (1) well width = 9 lambda * - * (2) N well process accepts both N and P selects * - * ------------------------------------------------------------------- */ - -/* Definition for actives */ -/* NOTE: Some version of cpp may have problem with two consective tabs - * or even two consective space... So we put only single space - * here... */ -#define allNDiff ndiff,ndc/a -#define allPDiff pdiff,pdc/a -#define allNActive ndiff,ndc/a,nfet,enfet,nffet,wcap -#define allPActive pdiff,pdc/a,pfet,epfet,pffet -#define allNOhmic nsd,nsc/a -#define allPOhmic psd,psc/a -#define allOhmic allNOhmic,allPOhmic -#define allBiNDiff emit,emc/a,col,clc/a -#define allBiPDiff pbase,pbc/a -#define allBiDiff allBiNDiff,allBiPDiff -#define allCCDiff bd,nbd,nbdc/a -#define allDiff allNDiff,allPDiff -#define allActive allNActive,allPActive,allOhmic -#define PNplus ndiff,pdiff,ndc/a,pdc/a -#define allHVNDiff hndiff,hndc/a -#define allHVPDiff hpdiff,hpdc/a -#define allHVNOhmic hnsd,hnsc/a -#define allHVPOhmic hpsd,hpsc/a -#define allHVDiff allHVNDiff,allHVPDiff -#define allHVOhmic allHVNOhmic,allHVPOhmic - -/* first poly without those overlapped with the second */ -#define allP poly,pc/a -#define allP1 poly,pc/a,nfet,pfet,wcap -/* all first poly */ -#define allPoly allP1,cap,capc/a,nffet,pffet -/* second poly without those overlapped with the first */ -#define allP2 poly2,ec/a,enfet,epfet -/* all second poly */ -#define allPoly2 allP2,cap,capc/a,nffet,pffet,hnfet,hpfet - -/* MOSFETs */ -#define NFet nfet,enfet,nffet -#define PFet pfet,epfet,pffet -#define allFet NFet,PFet - -/* Definitions for contacts */ -#define DiffCut pdc,ndc,psc,nsc -#define HVDiffCut hpdc,hndc,hpsc,hnsc -#define PolyCut pc -#define CapCut ec,capc -#define BiCut clc,emc,pbc -#define allCut DiffCut,HVDiffCut,PolyCut,CapCut,nbdc - -/* Definitions for metals */ -#define DiffMetal pdc/m1,ndc/m1,psc/m1,nsc/m1 -#define HVDiffMetal hpdc/m1,hndc/m1,hpsc/m1,hnsc/m1 -#define PolyMetal pc/m1,ec/m1,capc/m1 -#define BiMetal clc/m1,emc/m1,pbc/m1 -#define CCDMetal nbdc/m1 -#define allMetal1 DiffMetal,HVDiffMetal,PolyMetal,BiMetal,CCDMetal,m1,m2c/m1,gc -#define allMetal2 m2,m2c/m2,m3c/m2,pad -#define allMetal3 m3,m3c/m3 - -/* All types containing metal, on their respective home planes */ -#define homeMetal1 allCut,m1,m2c,gc - -/* Definitions for wells */ -#define allWell nwell,pwell -#define allNwell nwell,nsc,nsd -#define allPwell pwell,psc,psd -#define allHVNwell hnwell,hnsc,hnsd -#define allHVPwell hpwell,hpsc,hpsd - - -tech - format 28 - scmos -end - -#if V4 || V5 -version - version 8.2.8 -#ifdef SUBMICRON - description "MOSIS Scalable CMOS Technology for HP CMOS26G and CMOS14B processes" -#else /* TIGHTMETAL */ -#ifdef IBMTECH - description "MOSIS Scalable CMOS Technology for IBM" -#else /* IBMTECH */ -#ifdef HPTECH - description "MOSIS Scalable CMOS Technology for Tight Metal Rules" -#else -#ifndef WELL_ROUTE_CHECK - description "MOSIS Scalable CMOS Technology for Standard Rules" -#else - description "MOSIS Scalable CMOS Technology for Standard Rules (No routing through wells)" -#endif -#endif /* HPTECH */ -#endif /* IBMTECH */ -#endif /* TIGHTMETAL */ -end -#endif /* V4 */ - -planes - well,w - implant,i - active,a - metal1,m1 - metal2,m2 -#ifdef STACKVIA - v2oxide,v2x -#endif - metal3,m3 - oxide,ox -end - - -types - /* primary layers -16 */ - - well pwell,pw - well nwell,nw - well capwell,cwell,cw - well highvoltnwell,hvnwell,hnwell,hnw - well highvoltpwell,hvpwell,hpwell,hpw - active polysilicon,red,poly,p - active electrode,poly2,el,p2 - active capacitor,polycap,pcap,cap - active wellcapacitor,wellcap,wcap - active ndiffusion,ndiff,green - active pdiffusion,pdiff,brown - active highvoltndiffusion,hvndiff,hndiff - active highvoltpdiffusion,hvpdiff,hpdiff - metal1 metal1,m1,blue - metal2 metal2,m2,purple - metal3 metal3,m3,cyan - - /* MOSFETs -8 */ - - active ntransistor,nfet - active ptransistor,pfet - active entransistor,enfet - active eptransistor,epfet - active doublentransistor,nfloating-gate,nfloatg,nfg,nffet - active doubleptransistor,pfloating-gate,pfloatg,pfg,pffet - active highvoltntransistor,hvnfet,hnfet - active highvoltptransistor,hvpfet,hpfet - - /* NPN transistor layers -3 */ - - active collector,coll,col,co,cl - active emitter,emit,em - active pbase,pb - - /* layers for BCCD devices -2 */ - - implant bccdiffusion,bd - active nbccdiffusion,nbd - - /* Contacts between interconnection layers -13 */ - - active polycontact,pcontact,polycut,pc - active ndcontact,ndiffcut,ndc - active pdcontact,pdiffcut,pdc - active highvoltndcontact,hndiffcut,hndc - active highvoltpdcontact,hpdiffcut,hpdc - active capcontact,ccontact,capc,cc - active electrodecontact,econtact,ec,poly2contact,p2c - active collectorcontact,colcontact,colc,coc,clc - active emittercontact,emitcontact,emc - active pbasecontact,pbcontact,pbc - active nbccdiffcontact,nbdc - metal1 m2contact,m2cut,m2c,via,v -#ifdef STACKVIA - v2x m3contact,m3cut,m3c,via2,v2 -#else - metal2 m3contact,m3cut,m3c,via2,v2 -#endif - - /* Well contacts -8 */ - /* pohmic and nohmic are included for compatibility */ - /* nwc, pwc, etc ... are included for compatibility */ - - active psubstratepcontact,ppcontact,ppc,pwcontact,pwc,psc - active nsubstratencontact,nncontact,nnc,nwcontact,nwc,nsc - active psubstratepdiff,ppdiff,pohmic,ppd,psd - active nsubstratendiff,nndiff,nohmic,nnd,nsd - - active highvoltpsubcontact,hpwcontact,hpsc - active highvoltnsubcontact,hnwcontact,hnsc - active highvoltpsubdiff,hpohmic,hpsd - active highvoltnsubdiff,hnohmic,hnsd - - /* Special tiles needed for ESD protection design -3 */ - active nplusdoping,ndoping,ndop - active pplusdoping,pdoping,pdop - metal1 genericcontact,gcontact,gc - - /* Special tiles needed for micromachine fab. in CMOS -2 */ - oxide substrateopen,subopen,open - oxide pdiffusionstop,pdiffstop,pstop - - /* Additional stuff, used in pads. -2 */ - - metal2 pad - oxide glass -end - -contact - /* polys */ - ec poly2 metal1 - cc cap metal1 - pc poly metal1 - /* active contacts */ - ndc ndiff metal1 - pdc pdiff metal1 - nsc nsd metal1 - psc psd metal1 - hndc hndiff metal1 - hpdc hpdiff metal1 - hnsc hnsd metal1 - hpsc hpsd metal1 - /* bipolar contacts */ - clc col metal1 - emc emit metal1 - pbc pbase metal1 - /* BCCD contact */ - nbdc nbd metal1 - /* vias */ - m2c metal1 metal2 -#ifdef STACKVIA - m3c metal2 m3c metal3 -#else - m3c metal2 metal3 -#endif -/* - pad metal1 metal2 metal3 - */ - -end - -styles - styletype mos - - /* wells */ - cwell 10 - nwell 12 - pwell 13 - hnwell 18 - hpwell 11 - /* poly */ - poly 1 - poly2 14 - /* diffusions */ - ndiff 2 - pdiff 4 - psd 5 - nsd 3 - hndiff 2 - hndiff 11 - hpdiff 4 - hpdiff 18 - hpsd 5 - hpsd 11 - hnsd 3 - hnsd 18 - ndop 2 - ndop 38 - pdop 4 - pdop 38 - /* transistors */ - nfet 6 - nfet 7 - pfet 8 - pfet 9 - - enfet 6 - enfet 30 -/* enfet 14 */ - epfet 8 - epfet 31 -/* epfet 14 */ - - nffet 6 - nffet 7 -/* nffet 14 */ - nffet 30 - pffet 8 - pffet 9 -/* pffet 14 */ - pffet 31 - - hnfet 6 - hnfet 7 - hnfet 30 - - hpfet 8 - hpfet 9 - hpfet 31 - /* base */ - pbase 15 - pbc 15 - pbc 20 - pbc 32 - /* emitter */ - emit 16 - emc 16 - emc 20 - emc 32 - /* collector */ - col 3 - clc 3 - clc 20 - clc 32 - /* capacitors */ - cap 1 - cap 14 - wcap 6 - wcap 10 - cc 1 - cc 14 - cc 20 - cc 32 - /* metals */ - metal1 20 - metal2 21 - metal3 22 - /* generic contact */ - gc 19 - /* poly contacts */ - pcontact 26 - pcontact 32 - ec 14 - ec 20 - ec 32 - /* diffusion contacts */ - ndc 2 - ndc 20 - ndc 32 - pdc 4 - pdc 20 - pdc 32 - psc 5 - psc 20 - psc 32 - nsc 3 - nsc 20 - nsc 32 - /* high-voltage diffusion contacts */ - hndc 2 - hndc 20 - hndc 32 - hndc 11 - hpdc 4 - hpdc 20 - hpdc 32 - hpdc 18 - hpsc 5 - hpsc 20 - hpsc 32 - hpsc 11 - hnsc 3 - hnsc 20 - hnsc 32 - hnsc 18 - /* vias */ - m2contact 20 - m2contact 21 - m2contact 33 - m3contact 21 - m3contact 22 - m3contact 37 - /* pads and overglass */ - pad 20 - pad 21 - pad 33 - pad 34 - glass 34 - /* CCDs */ - bd 17 - nbd 17 - nbd 3 - nbdc 3 - nbdc 17 - nbdc 20 - nbdc 32 - /* MEMs */ - open 2 - open 20 - pstop 8 - /* System */ - error_p 42 - error_s 42 - error_ps 42 -end - -compose - /* MOSFET combination rules */ - compose nfet poly hndiff - compose pfet poly hpdiff - compose nfet poly ndiff - compose pfet poly pdiff - compose hnfet poly2 hndiff - compose hpfet poly2 hpdiff - compose enfet poly2 ndiff - compose epfet poly2 pdiff - compose nffet nfet poly2 - compose pffet pfet poly2 - compose nffet enfet poly - compose pffet epfet poly - compose cap poly poly2 - /* Transistor combination rules */ - paint clc col clc - paint emc emit emc - paint emc pbase emc - /* Poly2 capacitor combination rules */ - paint poly2 poly cap - paint poly poly2 cap - paint poly cap cap - paint poly2 cap cap - paint cap poly cap - paint cap poly2 cap -/* ILLEGAL declaration by 7.3 standards */ -/* paint poly ec cc */ - paint ec poly cc - /* These rules allow nwell to be painted over an area to - * flip all the p-well types to n-well types. Pwell can be - * painted to flip in the reverse. */ - paint pdc pwell ndc - paint pfet pwell nfet - paint epfet pwell enfet - paint pffet pwell nffet - paint pdiff pwell ndiff - paint nsd pwell psd - paint nsc pwell psc - paint ndc nwell pdc - paint nfet nwell pfet - paint enfet nwell epfet - paint nffet nwell pffet - paint ndiff nwell pdiff - paint psd nwell nsd - paint psc nwell nsc - - paint pdc hpwell hndc - paint epfet hpwell hnfet - paint pffet hpwell hnfet - paint pdiff hpwell hndiff - paint nsd hpwell hpsd - paint nsc hpwell hpsc - paint ndc hnwell hpdc - paint enfet hnwell hpfet - paint nffet hnwell hpfet - paint ndiff hnwell hpdiff - paint psd hnwell hnsd - paint psc hnwell hnsc - /* BCCD layers combination rules */ -/* paint bd ndiff 0 implant */ -/* - erase nbd bd ndiff - erase nbd ndiff bd - erase nbdc/a bd ndc/a -*/ - /* Well capacitor combination rules */ - paint nfet cwell wcap - paint poly wcap wcap - paint ndiff wcap wcap - paint wcap poly wcap - paint wcap ndiff wcap - erase wcap poly ndiff - erase wcap ndiff poly - erase wcap cwell nfet - paint cwell nfet wcap active - erase wcap nfet cwell well - - /* Generic contact */ - paint gc m1 gc - - /* For pads */ - paint pad m1 pad - paint pad m2 pad - paint pad m3 pad - paint pad m2c pad - - /* These rules allow nwell to be painted over an area to - * flip all the p-well types to n-well types. Pwell can be - * painted to flip in the reverse. */ - paint hpdc hpwell hndc - paint hpfet hpwell hnfet - paint hpdiff hpwell hndiff - paint hnsd hpwell hpsd - paint hnsc hpwell hpsc - paint hndc hnwell hpdc - paint hnfet hnwell hpfet - paint hndiff hnwell hpdiff - paint hpsd hnwell hnsd - paint hpsc hnwell hnsc - - paint hpdc pwell ndc - paint hpfet pwell enfet - paint hpdiff pwell ndiff - paint hnsd pwell psd - paint hnsc pwell psc - paint hndc nwell pdc - paint hnfet nwell epfet - paint hndiff nwell pdiff - paint hpsd nwell nsd - paint hpsc nwell nsc - -end - -connect -#ifndef WELL_ROUTE_CHECK -/* This creates a tech file where the wells are not connected therefore - enabling extractions to check whether the wells are used accidentaly - to route signals or power. To check for these cases you have to compare - the netlists generated with the normal tech file with those generated - with the special one (eg. using gemini). -*/ - allNwell allNwell - allPwell allPwell -#endif - allHVNwell allHVNwell - allHVPwell allHVPwell - /* for capacitor-well */ - allNDiff cwell - /* for all metals */ - allMetal1 allMetal1 - allMetal2 allMetal2 - allMetal3 allMetal3 - /* for all polys */ - allP1 allP1 - allPoly2 allPoly2 - /* for all diffusions/well plugs */ - /* Ndiffusion and Ohmic wells dont connect !! */ - /* you get a diode instead */ - allNDiff,ndop allPOhmic,pdop,pstop - allPDiff,pdop,pstop allNOhmic,ndop - allHVNDiff,ndop allHVPOhmic,pdop,pstop - allHVPDiff,pdop,pstop allHVNOhmic,ndop - ndiff ndc - pdiff pdc - hndiff hndc - hpdiff hpdc - /* for BCCD device */ - nbd nbdc - /* for NPN transistor */ - pbase pbc - collector clc,nwell - emitter emc - /* for new generic contact */ - gc allActive,allOhmic,allHVDiff,metal1 - gc allP1 - gc allPoly2 - /* for pad */ - pad allMetal1 - pad allMetal2 - pad allMetal3 - -end - -/* WARNING ::::: automatic generation of wells does not guarantee */ -/* rules on width and spacing of wells are followed !! */ -/* It is strongly recommanded that designers layout their own wells */ - -/* PWELL styles cannot generate CBA and CCD correctly */ -/* BOTH NWELL and GEN can do CCD and CBA */ -/* ONLY GEN can be used for micro-machining fabrication */ - -cifoutput -/* default: fab on 2.0 micron (Nwell) rules each magic unit is 100 */ -/* centimicrons */ -/* SCN technology : Both CSN and CSP are generated to reduce field */ -/* poly sheet resistance */ - -#ifdef STANDARD -#include "cif_template/objs/CIFout" -#endif /* STANDARD */ - -#ifdef TIGHTMETAL -#include "cif_template/objs/TMCIFout" -#endif /* TIGHTMETAL */ - -#ifdef SUBMICRON -#include "cif_template/objs/SUBCIFout" -#endif /* SUBMICRON */ - -#ifdef IBMTECH -#include "cif_template/objs/IBMCIFout" -#endif /* IBMTECH */ - -style plot /* pplot output style */ - scalefactor 100 50 - layer CM2 m2,m2c/m2,pad/m2 - labels m2 - layer CM1 pad - grow 100 - or m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1 - labels m1,m2c/m1,pc/m1,ndc/m1,pdc/m1,ppcont/m1,nncont/m1,pad/m1 - layer CP poly,pc/active,nfet,pfet - labels poly,nfet,pfet - layer CND ndiff,ndc,nfet,pwc,psd - labels ndiff - layer CPD pdiff,pdc,pfet,nwc,nsd - labels pdiff - layer CNP - bloat-or nsd,nwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0 - layer CPP - bloat-or psd,pwc * 150 ndiff,pdiff,ndc/active,pdc/active,ppcont/active,nncont/active,pfet,nfet,psd,nsd 0 - layer CV m2c - squares 100 200 300 - layer CC ndc,pdc,pc,pwc,nwc - squares 200 - layer CNW nwell - grow 400 - shrink 400 - layer CG pad - shrink 600 - or glass - labels glass - - -end - -/* -------------------------------------------------------------------- * - * In the CIFinput section, the order of layer specifications is very * - * important. Each layer overrides any of the previous layers. There * - * are places where one layer is generated over an area that is too * - * large, but with the knowledge that later layers will "take over" * - * the extraneous area, leaving the first layer only where it belongs. * - * This happens for various flavors of diffusion, for example. * - * Note: when reading in CMOS, wells are created in the Magic files. * - * They can be eliminated manually if desired. * - * ---------------------------------------------------------------------*/ -cifinput - -#ifdef STANDARD -#include "cif_template/objs/CIFin" -#endif /* STANDARD */ - -#ifdef TIGHTMETAL -#include "cif_template/objs/TMCIFin" -#endif /* TIGHTMETAL */ - -#ifdef SUBMICRON -#include "cif_template/objs/SUBCIFin" -#endif /* SUBMICRON */ - -#ifdef IBMTECH -#include "cif_template/objs/IBMCIFin" -#endif /* IBMTECH */ - -end - -mzrouter - style irouter - layer m2 32 64 256 1 - layer m1 64 32 256 1 - layer poly 128 128 512 1 - contact m2contact metal1 metal2 1024 - contact pcontact metal1 poly 2056 - notactive poly pcontact - style garouter - layer m2 32 64 256 1 - layer m1 64 32 256 1 - contact m2contact metal1 metal2 1024 -end - - -/* SCMOS rules revision 7 */ -drc -/* ---------------------------------------------------------------- */ -/* Well */ -/* ---------------------------------------------------------------- */ - -/* 1.1 */ -/* Now use "edge" for width DRC... A test only for rule1 */ -/* Other rules may follow in the near future... */ -#ifdef SUBMICRON - edge4way (~nwell)/w nwell 12 nwell nwell 12\\ - "N-Well width must be at least 12 (MOSIS rule #1.1)" - edge4way (~pwell)/w pwell 12 pwell pwell 12\\ - "P-Well width must be at least 12 (MOSIS rule #1.1)" -#else - edge4way (~nwell)/w nwell 10 nwell nwell 10\\ - "N-Well width must be at least 10 (MOSIS rule #1.1)" - edge4way (~pwell)/w pwell 10 pwell pwell 10\\ - "P-Well width must be at least 10 (MOSIS rule #1.1)" -#endif - -/* original "width" rule which use 'width'command: - width allWell 10 \\ - "Well width must be at least 10 (MOSIS rule #1.1)" - */ - -/* 1.2 */ -/* Now use "edge4way" for spacing DRC... A test only for rule1 */ -/* Other rules may follow in the near future... */ -#ifdef SUBMICRON - edge4way nwell ~(nwell)/w 18 (~nwell)/w (~nwell)/w 18\\ - "N-Well spacing must be at least 18 (MOSIS rule #1.2)" - edge4way pwell (~pwell)/w 18 (~pwell)/w (~pwell)/w 18\\ - "P-Well spacing must be at least 18 (MOSIS rule #1.2)" -#else - edge4way nwell (~nwell)/w 9 (~nwell)/w (~nwell)/w 9\\ - "N-Well spacing must be at least 9 (MOSIS rule #1.2)" - edge4way pwell (~pwell)/w 9 (~pwell)/w (~pwell)/w 9\\ - "P-Well spacing must be at least 9 (MOSIS rule #1.2)" -#endif - -/* original spacing rule which use 'spacing' command: - spacing allWell allWell 9 touching_ok \\ - "Well spacing must be at least 9 (MOSIS rule #1.2)" - */ - -/* NOTE: rule 1.2 is equivalent to the following three rules where - the third is a new one. This rule is added to force designers - to be cautious about the wells... - - spacing nwell nwell 9 touching_ok \\ - "N-well spacing must be at least 9 (MOSIS rule #1.2)" - spacing pwell pwell 9 touching_ok \\ - "P-well spacing must be at least 9 (MOSIS rule #1.2)" - spacing nwell pwell 9 touching_ok \\ - "Well spacing must be at least 9 (MOSIS rule #1.2)" -*/ - -/* 1.3 is not checked */ -/* NOTE: for digital ckts where wells are not explicitly put, * - * auto-generation may not ensure the minimul spacing and width * - * rule: this happens usually when two geometries are in diagonal * - * positions. * - * NOTE: when both pwell and nwell are submitted they cannot * - * overlap this is assured with the compose section - painting one * - * well over another will erase the original well. */ - -/* ---------------------------------------------------------------- */ -/* Active */ -/* ---------------------------------------------------------------- */ - -/* 2.1 */ -/* Test active width separately... */ - width allNActive 3 \\ - "N-type Diffusion width must be at least 3 (MOSIS rule #2.1a)" - width allPActive 3 \\ - "P-type Diffusion width must be at least 3 (MOSIS rule #2.1b)" - width allOhmic 3 \\ - "Ohmic diffusion width must be at least 3 (MOSIS rule #2.1c)" - -/* 2.2 */ - spacing allNActive allNActive 3 touching_ok \\ - "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" - spacing allPActive allPActive 3 touching_ok \\ - "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" - spacing allNOhmic allNOhmic 3 touching_ok \\ - "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" - spacing allPOhmic allPOhmic 3 touching_ok \\ - "Diffusion spacing must be at least 3 (MOSIS rule #2.2)" - -/* 2.3 without explicit well definition: 6+6 and 5+5 respectively */ -#ifdef SUBMICRON - spacing allNDiff allPDiff 12 touching_illegal \\ - "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #2.3b)" -#else - spacing allNDiff allPDiff 10 touching_illegal \\ - "P-type diffusion must be 10 away from N-type diffusion (MOSIS rule #2.3a)" -#endif - -/* 2.3 + 2.4 without explicit well definition: 6+3 and 5+3 respectively */ -#ifdef SUBMICRON - spacing allNDiff allNOhmic 9 touching_illegal \\ - "N-type diffusion must be 9 away from N-substrate contact (MOSIS rule #2.3b,4b)" - spacing allPDiff allPOhmic 9 touching_illegal \\ - "P-type diffusion must be 9 away from P-substrate contact (MOSIS rule #2.3b,4b)" -#else - spacing allNDiff allNOhmic 8 touching_illegal \\ - "N-type diffusion must be 8 away from N-substrate contact (MOSIS rule #2.3a,4a)" - spacing allPDiff allPOhmic 8 touching_illegal \\ - "P-type diffusion must be 8 away from P-substrate contact (MOSIS rule #2.3a,4a)" -#endif - -/* 2.4 3 + 3 */ - spacing allNOhmic allPOhmic 6 touching_illegal \\ - "Opposite well contacts must be separated by 6 (MOSIS rule #2.4)" - -/* 2.3 with explicit well: 6 and 5 respectively */ -#ifdef SUBMICRON - spacing allNActive nwell 6 touching_illegal \\ - "N-diffusion and N-well must be separated by 6 (MOSIS rule #2.3b)" - spacing allPActive pwell 6 touching_illegal \\ - "P-diffusion and P-well must be separated by 6 (MOSIS rule #2.3b)" -#else - spacing allNActive nwell 5 touching_illegal \\ - "N-diffusion and N-well must be separated by 5 (MOSIS rule #2.3a)" - spacing allPActive pwell 5 touching_illegal \\ - "P-diffusion and P-well must be separated by 5 (MOSIS rule #2.3a)" -#endif - -/* 2.4 with explicit well */ - spacing allNOhmic pwell 3 touching_illegal \\ - "N-substrate diffusion and P-well must be separated by 3 (MOSIS rule #2.4)" - spacing allPOhmic nwell 3 touching_illegal \\ - "P-substrate diffusion and N-well must be separated by 3 (MOSIS rule #2.4)" - -/* MOSIS extension rule for diffusion and substrate contact of */ -/* opposite type. We could do without this rule, but it is now */ -/* added for safety reason. */ - spacing allNActive allPOhmic 4 touching_ok \\ - "Opposite diffusion spacing must be at least 4 (MOSIS extension rule)" - spacing allPActive allNOhmic 4 touching_ok \\ - "Opposite diffusion spacing must be at least 4 (MOSIS extension rule)" - -/* ---------------------------------------------------------------- */ -/* Poly */ -/* ---------------------------------------------------------------- */ - -/* 3.1 */ - width allPoly 2 \\ - "Polysilicon width must be at least 2 (MOSIS rule #3.1)" - -/* 3.2 */ -#ifdef SUBMICRON - spacing allPoly allPoly 3 touching_ok \\ - "Polysilicon spacing must be at least 3 (MOSIS rule #3.2b)" -#else - spacing allPoly allPoly 2 touching_ok \\ - "Polysilicon spacing must be at least 2 (MOSIS rule #3.2a)" -#endif - -/* 3.3 */ - edge4way nfet,pfet poly,pc/act 2 poly,pc/act 0 0 \\ - "Poly must overhang transistor by at least 2 (MOSIS rule #3.3)" - -/* 3.4 */ - edge4way nfet,enfet ndiff,ndc/a 3 allNActive ndiff,ndc/a 3 \\ - "Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)" - edge4way pfet,epfet pdiff,pdc/a 3 allPActive ndiff,ndc/a 3 \\ - "Diffusion must overhang transistor by at least 3 (MOSIS rule #3.4)" - -/* 3.3 + 3.4 */ - edge4way nfet,pfet space 1 poly 0 0 \\ - "Transistor overhang is missing (MOSIS rule #3.3,4)" - edge4way enfet,epfet space 1 poly2 0 0 \\ - "Transistor overhang is missing (MOSIS rule #3.3,4)" - edge4way nffet,pffet space 1 poly 0 0 \\ - "Transistor overhang is missing (MOSIS rule #3.3,4)" - edge4way nffet,pffet space 1 poly2 0 0 \\ - "Transistor overhang is missing (MOSIS rule #3.3,4)" - -/* 3.5 */ - edge4way allDiff,allOhmic poly,pc 1 space/a 0 1 \\ - "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" - edge4way poly,pc allDiff,allOhmic 1 space/a 0 1 \\ - "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" - edge poly,pc space/a 1 space/a space/a 1 \\ - "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" - edge allOhmic,allDiff space/a 1 space/a space/a 1 \\ - "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5)" -/* - These following checks will miss the corner, so we add something above - - edge4way allDiff,allOhmic poly,pc 1 space space 1 \\ - "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5.a)" - spacing allDiff,allOhmic poly,pc 1 touching_illegal \\ - "Poly and diffusion must be separated by at least 1 (MOSIS rule #3.5.b)" - */ - -/* Extra transistor rules */ -/* These rules is really NOT necessary because others have already - taken care of it. It is here for future reference... - - edge4way poly,pc/act pfet 3 pfet 0 0 \\ - "Transistors must be at least 3 units wide (MOSIS rule #2)" - edge4way poly,pc/act nfet 3 nfet 0 0 \\ - "Transistors must be at least 3 units wide (MOSIS rule #2)" -*/ - -/* ---------------------------------------------------------------- */ -/* Select */ -/* ---------------------------------------------------------------- */ -/* 4.1 */ - spacing PFet allNOhmic 3 touching_illegal \\ - "Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.a)" - spacing NFet allPOhmic 3 touching_illegal \\ - "Transistors must be separated from substrate contacts by 3 (MOSIS rule #4.1.b)" - - edge4way allPOhmic space/act 3 ~(NFet)/act allPOhmic,allNDiff 3 \\ - "Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.c)" - - edge4way allNOhmic space/act 3 ~(PFet)/act allNOhmic,allPDiff 3 \\ - "Transistors must be separated from selects(generated by well cont) by 3 (MOSIS rule #4.1.d)" - - edge4way allPOhmic ~(ndiff,ndc,psc,psd)/act 4 ~(nfet,enfet)/act ~(ndiff,ndc,psc,psd)/act 4 \\ - "Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.e)" - - edge4way allNOhmic ~(pdiff,pdc,nsc,nsd)/act 4 ~(pfet,epfet)/act ~(pdiff,pdc,nsc,nsd)/act 4 \\ - "Transistors must be separated from selects(generated by well cont) by 4 (MOSIS rule #4.1.f)" - -/* 4.2 */ -/* This one is very difficult.... Most likely done by CIF output */ - edge4way ~(allPActive)/act pdiff,pdc,pfet 4 ~(allNOhmic)/act allPActive 2 \\ - "Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.a)" - edge4way ~(allNActive)/act ndiff,ndc,nfet 4 ~(allPOhmic)/act allNActive 2 \\ - "Backedge of diffusion must be 4 from substrate diff (MOSIS rule #4.2.b)" - -/* 4.3 -- guaranteed automatically by CIF generator. */ -/* 4.4 -- guaranteed automatically by CIF generator except diag. where - this rule is not crucial */ - - -/* ---------------------------------------------------------------- */ -/* Contact to Poly */ -/* ---------------------------------------------------------------- */ - -/* 5B.1 + 5B.2 + 5B.3 */ - width pc 4 \\ - "Poly contact width must be at least 4 (MOSIS rule #5B.1,2,3)" - -/* 5B.4 is guaranteed by 5B.1,2,3 with rule 7.2 (metal1 spacing) */ - -/* 5B.5 -- - * Watch out here: a spacing "touching_ok" rule CANNOT be used here: - * it will miss certain checks. - */ - edge4way allPoly ~(allPoly)/act 3 ~pc/act ~(allPoly)/act 3 \\ - "Poly contact must be at least 3 from other poly (MOSIS rule #5B.4,5)" - -/* 5B.6 -- - * This is mostly handled by 3.5 already, but need rule here to handle - * case of pc abutting transistor. - */ - spacing pc allActive 1 touching_illegal \\ - "Poly contact must be 1 unit from diffusion (MOSIS rule #5B.6)" - -/* 5B.7 -- not implemented */ - -/* ---------------------------------------------------------------- */ -/* Contact to Active */ -/* ---------------------------------------------------------------- */ - -/* 6B.1 + 6B.2 + 6B.3 */ - width ndc,pdc 4 \\ - "Diffusion contact width must be at least 4 (MOSIS rule #6B.1,2,3)" - width nsc,psc 4 \\ - "Substrate contact width must be at least 4 (MOSIS rule #6B.1,2,3)" - -/* 6B.2 this is here to explicit check the contact spacing rule 3. */ -#ifdef SUBMICRON - spacing nsc pdc 1 touching_illegal \\ - "Substrate contact must be 1 unit from diffusion contact (MOSIS rule #6B.2b)" - spacing psc ndc 1 touching_illegal \\ - "Substrate contact must be 1 unit from diffusion contact (MOSIS rule #6B.2b)" -#endif - -/* - edge4way psc (~psc)/a 1 psd psd 1 \\ - "Substrate contact must overlapped by diffusion by at least 1 (MOSIS 26G rule)" - edge4way nsc (~nsc)/a 1 nsd nsd 1 \\ - "Substrate contact must overlapped by diffusion by at least 1 (MOSIS 26G rule)" -*/ - -/* 6B.4 & 6B.5 -- - * Watch out here: a spacing "touching_ok" rule CANNOT be used here: - * it will miss certain checks. - */ - edge4way allActive ~(allActive)/act 4 ~(ndc,pdc,nsc,psc)/act \\ - ~(allActive)/act 4 \\ - "Diffusion contacts must be 4 from other diffusions (MOSIS rule #6B.4,5)" - -/* 6B.6 */ - spacing DiffCut allFet 1 touching_illegal \\ - "Diffusion contacts cannot touch transistors (MOSIS rule #6B.6)" - -/* 6B.7 */ - spacing DiffCut poly 1 touching_illegal \\ - "Diffusion contact to field poly must be at least 1 (MOSIS rule #6B.7)" - -/* 6.8 -- not implemented */ - -/* 6B.9 */ - spacing DiffCut pc/act 2 touching_illegal \\ - "Poly contacts must be 2 away from diffusion contacts (MOSIS rule #6B.9)" - -/* ---------------------------------------------------------------- */ -/* Contacts must all be rectangular (no adjacent contacts */ -/* of same type) because of the way their contact is generated by */ -/* CIFoutput section rules. This is handled using the corner checks */ -/* in the rules below. Overlaps between contacts must be exact */ -/* overlaps. The only exception is overpad, which doesn't matter. */ - - edge4way m3c/m3 ~m3c/m3 1 ~m3c/m3 (~m3c,m3c)/m3 1 \\ - "Metal3 contacts must be rectangular (Magic rules)" - edge4way m2c/m2 ~m2c/m2 1 ~m2c/m2 (~m2c,m2c)/m2 1 \\ - "Metal2 contacts must be rectangular (Magic rules)" - - edge4way ndc/m1 ~ndc/m1 1 ~ndc/m1 (~ndc,ndc)/m1 1 \\ - "N-diffusion contacts must be rectangular (Magic rules)" - edge4way pdc/m1 ~pdc/m1 1 ~pdc/m1 (~pdc,pdc)/m1 1 \\ - "P-diffusion contacts must be rectangular (Magic rules)" - edge4way psc/m1 ~psc/m1 1 ~psc/m1 (~psc,psc)/m1 1 \\ - "P-substrate contacts must be rectangular (Magic rules)" - edge4way nsc/m1 ~nsc/m1 1 ~nsc/m1 (~nsc,nsc)/m1 1 \\ - "N-substrate contacts must be rectangular (Magic rules)" - - edge4way pc/m1 ~pc/m1 1 ~pc/m1 (~pc,pc)/m1 1 \\ - "Polysilicon contacts must be rectangular (Magic rules)" - edge4way ec/m1 ~ec/m1 1 ~ec/m1 (~ec,ec)/m1 1 \\ - "Electrode contacts must be rectangular (Magic rules)" - edge4way cc/m1 ~cc/m1 1 ~cc/m1 (~cc,cc)/m1 1 \\ - "Capacitor contacts must be rectangular (Magic rules)" - - edge4way emc/m1 ~emc/m1 1 ~emc/m1 (~emc,emc)/m1 1 \\ - "Emitter contacts must be rectangular (Magic rules)" - edge4way clc/m1 ~clc/m1 1 ~clc/m1 (~clc,clc)/m1 1 \\ - "Collector contacts must be rectangular (Magic rules)" - edge4way pbc/m1 ~pbc/m1 1 ~pbc/m1 (~pbc,pbc)/m1 1 \\ - "P-base Contacts must be rectangular (Magic rules)" - edge4way nbdc/m1 ~nbdc/m1 1 ~nbdc/m1 (~nbdc,nbdc)/m1 1 \\ - "CCD-diffusion Contacts must be rectangular (Magic rules)" - -/* ---------------------------------------------------------------- */ -/* Metal 1 */ -/* ---------------------------------------------------------------- */ -/* 7.1 + 7.2 */ - width allMetal1,pad/m1 3 \\ - "First-level metal width must be at least 3 (MOSIS rule #7.1)" -#ifdef TIGHTMETAL - spacing allMetal1,pad/m1 allMetal1,pad/m1 2 touching_ok \\ - "First-level metal spacing must be at least 2 (MOSIS rule #7.2)" -#else - spacing allMetal1,pad/m1 allMetal1,pad/m1 3 touching_ok \\ - "First-level metal spacing must be at least 3 (MOSIS rule #7.2)" -#endif /* TIGHTMETAL */ - -/* 7.3 + 7.4 */ -/* guaranteed with 4x4 poly and diffusion contacts */ - - -/* ---------------------------------------------------------------- */ -/* Via */ -/* ---------------------------------------------------------------- */ - -/* 8.1 + 8.2 + 8.3 */ - width m2c 4 \\ - "Contact width must be at least 4 (MOSIS rule #8.1,2,3)" - -/* 8.4 + 8.5 */ -/* Vias have to be on flat surface */ -/* Don't allow poly or diffusion edges underneath metal2 contacts: */ -/* this rule is only valid for standard processes, not for those */ -/* processes use planarized interconnection technology. */ -#ifdef STANDARD - edge4way allPoly ~(allPoly)/a 1 ~m2c/m2 ~(allPoly)/a 1 \\ - "Via must be on a flat surface (MOSIS rule #8.4,5)" metal2 - edge4way allPoly2 ~(allPoly2)/a 1 ~m2c/m2 ~(allPoly2)/a 1 \\ - "Via must be on a flat surface (MOSIS rule #8.4,5)" metal2 - edge4way allActive ~(allActive)/a 1 ~m2c/m2 ~(allActive)/a 1 \\ - "Via must be on a flat surface (MOSIS rule #8.4,5)" metal2 - - edge4way ~(allPoly)/a allPoly 1 ~m2c/m2 allPoly 1 \\ - "Via must be on a flat surface (MOSIS rule #8.4,5)" metal2 - edge4way ~(allPoly2)/a allPoly2 1 ~m2c/m2 allPoly2 1 \\ - "Via must be on a flat surface (MOSIS rule #8.4,5)" metal2 - edge4way ~(allActive)/a allActive 1 ~m2c/m2 allActive 1 \\ - "Via must be on a flat surface (MOSIS rule #8.4,5)" metal2 -#endif /* STANDARD */ - - -/* ---------------------------------------------------------------- */ -/* Metal 2 */ -/* ---------------------------------------------------------------- */ -/* 9.1 */ - width allMetal2 3 \\ - "Second-level metal width must be at least 3 (MOSIS rule #9.1)" - -/* 9.2 */ -#ifdef TIGHTMETAL - spacing allMetal2 allMetal2 3 touching_ok \\ - "Second-level metal spacing must be at least 3 (MOSIS rule #9.2b)" -#else -#ifdef SUBMICRON - spacing allMetal2 allMetal2 3 touching_ok \\ - "Second-level metal spacing must be at least 3 (MOSIS rule #9.2b)" -#else - spacing allMetal2 allMetal2 4 touching_ok \\ - "Second-level metal spacing must be at least 4 (MOSIS rule #9.2a)" -#endif /* SUBMICRON */ -#endif /* TIGHTMETAL */ - -/* 9.3 */ -/* achieved with via size of 4x4 */ - - -/* ---------------------------------------------------------------- */ -/* Overglass */ -/* ---------------------------------------------------------------- */ -/* Rules for overglass (10.1-5) are not check because they are */ -/* either */ -/* 1. absolute micron rules, and */ -/* 2. vender/process dependent. */ -/* except the metal overlap of overglass rule (10.3) can be handled */ -/* case by case in CIFoutput section. */ -/* NOTE: glass layer is NOT usually used. Use "pad" layer for pad */ -/* and the corresponding overglass will be generated automatically. */ - -/* MOSIS rules to make sure there are m2 under glass - for those */ -/* users who like to use explicit "glass" layer... */ -/* */ -/* edge4way space glass 1 allMetal2 0 0 \ */ -/* "There must be metal 2 under the glass opening" metal2 */ -/* */ -/* I am removing this rule simply we have metal3 now and there's no */ -/* way to tell which process the pad is intended for. Basically, I */ -/* am enforcing the use of "pad" layer... */ - - - -/* ---------------------------------------------------------------- */ -/* Open and Pstop */ -/* ---------------------------------------------------------------- */ -/* The open layer is actually a combination of overglass and */ -/* contacts to expose the intrinsic silicon surface for future */ -/* etchimg process for micromachining device fabrication. */ -/* Since lots of applications are possible, there is no rules */ -/* enforced by Magic. Designers aimed at micromachining devices */ -/* must do DRC themself :-) */ -/* See the following reference for detail: */ -/* "High-Level CAD Melds Micromachined Devices with Foundaries", */ -/* Janet C. Marshall, M. Parameswaran, Mona E. Zaghloul, and */ -/* Michael Gaitan, IEEE Circuit and Devices, Vol. 8, No. 6, */ -/* pp. 10-17, 1992 */ - - - -/* ---------------------------------------------------------------- */ -/* Poly2 as Capacitor */ -/* ---------------------------------------------------------------- */ -/* 11.1 */ -/* The exact rule asks for 3 lambda minimum width for 'capacitor'. */ -/* But there are overlaps of poly/eletrode structures such that 2 */ -/* is fine, such as the overlaps in floating gates. So we are risk- */ -/* ing a little here... */ - width cap,capc/a 2 \\ - "Electrode capacitor width must be at least 3 (MOSIS rule #11.1)" - -/* 11.2 + 12.2 */ - spacing allPoly2 allPoly2 3 touching_ok \\ - "Second-level poly spacing must be at least 3 (MOSIS rule #11.2,12.2)" - -/* 11.3 */ - edge4way cap,cc space 1 0 0 0 \\ - "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" - edge4way cap,cc poly 2 poly poly 2 \\ - "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" - edge4way cap,cc poly2 2 poly2 poly2 2 \\ - "Cap must be overlapped by poly or poly2 (MOSIS rule #11.3)" - -/* 11.4 */ - edge4way nw,pw,cw ~(nw,pw,cw)/w 2 ~(cap,cc)/a ~(nw,pw,cw)/w 2 \\ - "Cap must be on a flat surface (MOSIS rule #11.4)" active - edge4way ~(nw,pw,cw)/w nw,pw,cw 2 ~(cap,cc)/a nw,pw,cw 2 \\ - "Cap must be on a flat surface (MOSIS rule #11.4)" active - edge4way cap ~(cap)/a 2 allFet,poly,poly2,space/a,cc/a \\ - allDiff,poly 2 "Cap must be on a flat surface (MOSIS rule #11.4)" active - -/* 11.5 */ -/* Done by 11.3 and 11.4 */ - - -/* ---------------------------------------------------------------- */ -/* Poly2 as Transistor */ -/* ---------------------------------------------------------------- */ -/* 12.1 */ - width allPoly2 2 \\ - "Electrode width must be at least 2 (MOSIS rule #12.1)" - -/* 12.2 */ -/* Done by 11.2 */ - -/* 12.3 */ - edge4way enfet,epfet poly2,ec/a 2 poly2,ec/a 0 0 \\ - "Poly2 must overhang transistor by at least 2 (MOSIS rule #12.3)" - edge4way nffet,pffet cap 2 cap 0 0 \\ - "Cap must overhang transistor by at least 2 (MOSIS rule #12.3)" - edge4way nffet ~(cap,nffet,enfet,nfet)/a 2 cap 0 0 \\ - "Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)" - edge4way pffet ~(cap,pffet,epfet,pfet)/a 2 cap 0 0 \\ - "Cap must overhang doubletransistor by at least 2 (MOSIS rule #12.3)" - -/* 12.4 */ - edge4way allDiff,allOhmic el 1 space/a 0 1 \\ - "Poly2 and diffusion must be separated by at least 1 (MOSIS rule #12.4)" - -/* 12.5 */ - -/* 12.6 */ - spacing allPoly2 pc,ndc,pdc 2 touching_illegal \\ - "Poly2 spacing to poly or diffusion contact must be at least 3 (MOSIS rule #12.6)" -/* - edge4way poly2,ec/a epfet 3 epfet 0 0 \\ - "Transistors must be at least 3 units wide (MOSIS rule #2)" - edge4way poly2,ec/a enfet 3 enfet 0 0 \\ - "Transistors must be at least 3 units wide (MOSIS rule #2)" - edge4way cap,capc/a pffet 3 pffet 0 0 \\ - "Transistors must be at least 3 units wide (MOSIS rule #2)" - edge4way cap,capc/a nffet 3 nffet 0 0 \\ - "Transistors must be at least 3 units wide (MOSIS rule #2)" -*/ - - -/* ---------------------------------------------------------------- */ -/* Poly2 Contact */ -/* ---------------------------------------------------------------- */ -/* 13.1 + 13.2 */ - width ec,capc 4 \\ - "Electrode contact width must be at least 4 (MOSIS rule #13.1)" - -/* 13.3 */ -/* Done by 11.3 */ - -/* 13.4 */ - edge4way ec/a space 1 poly2 poly2 1 \\ - "Electrode contact must be overlaped by poly2 (MOSIS rule #13.4)" - edge4way ec/a poly2 1 poly2 poly2 1 \\ - "Electrode contact must be overlaped by poly2 by 1 (MOSIS rule #13.4)" - -/* 13.5 */ - edge4way allDiff,allOhmic ec 2 space/a 0 2 \\ - "Poly2 and diffusion contact must be separated by at least 2 (MOSIS rule #13.5)" - - -/* ---------------------------------------------------------------- */ -/* Via 2 */ -/* ---------------------------------------------------------------- */ -/* 14.1 + 14.2 + 14.3 */ -/* By CIF output generation */ - width m3c 4 \\ - "Third-level metal contact width must be at least 4 (MOSIS rule #14.1,2,3)" - -/* 14.4 */ -/* guaranteed by 4x4 m2c and 4x4 m3c */ -/* Via2, i.e "m3c" can overlap anything except m2c layer */ - - -/* ---------------------------------------------------------------- */ -/* Metal 3 */ -/* ---------------------------------------------------------------- */ -/* 15.1 */ -#ifdef SUBMICRON - width allMetal3 5 \\ - "Third-level metal width must be at least 5 (MOSIS rule #15.1b)" -#else - width allMetal3 6 \\ - "Third-level metal width must be at least 6 (MOSIS rule #15.1a)" -#endif - -/* 15.2 */ -#ifdef SUBMICRON - spacing allMetal3 allMetal3 3 touching_ok \\ - "Third-level metal spacing must be at least 3 from other third-level metal (MOSIS rule #15.2b)" -#else - spacing allMetal3 allMetal3 4 touching_ok \\ - "Third-level metal spacing must be at least 4 from other third-level metal (MOSIS rule #15.2a)" -#endif - -/* 15.3 */ - edge4way m3c/m3 ~m3c/m3 1 m3 m3 1 \\ - "Mimimum metal3 overlap of via must be at least 1 (MOSIS rule #15.3)" - - -/* ---------------------------------------------------------------- */ -/* NPN Bipolar */ -/* ---------------------------------------------------------------- */ -/* 16.1 */ -/* As always, composite contacts are 4x4, where the actual */ -/* transistor contacts are 2x2 by CIF output generator */ - width clc,pbc,emc 4 \\ - "Transistor contact width must be at least 4 (MOSIS rule #16.1)" - -/* 16.2 */ -/* Done by 16.1 4x4 emc and CIF output generation */ - -/* 16.3 */ -/* This rule is guaranteed by the way the CIF output generates */ -/* N-Select for emitter (expand by 2 lambda), so we have Pbase */ -/* overlap of emitter(or emc) by 2+2 =4 */ - edge4way emc/a,emit pbase 4 pbase pbase 4 \\ - "Pbase overlap of emitter must be at least 4 (MOSIS rule #16.3)" - -/* 16.4 */ -/* NOTE; NO need to make this an edge rule... */ - spacing pbc emc/a,emit 7 touching_illegal \\ - "Base must be 7 (4+2+1) away from emitter (MOSIS rule #16.3,4,11)" - -/* 16.5 */ -/* This rule is guaranteed by requiring that base contact has */ -/* at least 3 (1+2) lambda base enclosure... */ -/* edge4way pbc/a pb,space 3 pb pb,space 3 */ - edge4way pbc (~pbc)/a 3 pb,pbc/a pb,pbc/a 3 \\ - "Pbase overlap of base contact must be at least 3 (MOSIS rule #16.5)" - -/* 16.6 */ -/* This rule is guaranteed by the CIF output generation of P-select */ - -/* 16.6 */ -/* This rule is enforced by checking whether collector is out of */ -/* Nwell and the fact that collector width is required to be at */ -/* least 6 */ - width col,clc/a 6 \\ - "Collector width must be at least 6 (MOSIS rule #16.6)" - -/* 16.7 */ -/* Explicit Nwell required for Bipolar transistors... */ - edge4way pbase space/a 6 nwell space/a 6 \\ - "Nwell overlap of Pbase must be at least 6 (MOSIS rule #16.7)" well - -/* 16.8 */ - edge4way pbase (~pbase)/a 4 ~(col,clc)/a ~(col,clc)/a 4 \\ - "Pbase must be at least 4 away from collector (MOSIS rule #16.8)" - -/* 16.9 */ - edge4way clc (~clc)/a 1 col col 1 \\ - "Collector overlap of contact must be at least 1 (MOSIS rule #16.9)" - -/* 16.10 */ -/* This rule is guaranteed by making sure that collector is within */ -/* PBase and the corresponding CIF output generation */ - -/* 16.11 */ - edge4way nw ~(nw)/w 3 ~(col,clc)/a ~(nw)/w 3 \\ - "N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active - edge4way ~(nw)/w nw 3 ~(col,clc)/a nw 3 \\ - "N-well overlap of collector must be at least 3 (MOSIS rule #16.11)" active - -/* This is a special rule to guarantee the emitter width */ - width em,emc/a 4 \\ - "Emitter width must be at least 4 (Magic Bipolar Transistor rule)" - -/* This is a special rule for multi-emitters transistor according */ -/* to rule 16.2 and 2.2 */ - spacing em,emc/a em,emc/a 7 touching_ok \\ - "Unrelated emitter must be at least 7 apart (Magic Bipolar transistor rule)" - -/* The following rules are added for pbase resistor implementation. */ -/* They are not in the official SCMOS design rules since I have no */ -/* foundry rules available at this moment and the numbers here is */ -/* considered to be conservative... */ - width pbase,pbc/a 4 \\ - "Pbase width must be at least 4 (MOSIS extension rule)" - - spacing pbase,pbc/a pbase,pbc/a 4 touching_ok \\ - "Pbase spacing must be at least 4 (MOSIS extension rule)" - -/* ---------------------------------------------------------------- */ -/* Capacitor Well */ -/* ---------------------------------------------------------------- */ -/* These are DRC rules for Capacitor Well (CWell) according to HP's */ -/* 1.2um linear capacitor process pi@isi.edu 9/18/92 */ -/* ---------------------------------------------------------------- */ - -/* 17.1 */ - width cwell 10 \\ - "Cap-well width must be at least 10 (MOSIS rule #17.1)" - -/* 17.2 */ - spacing cwell cwell 9 touching_ok \\ - "Cap-well spacing must be at least 9 (MOSIS rule #17.2)" - spacing cwell nwell 9 touching_illegal \\ - "Cap-well spacing must be at least 9 (MOSIS rule #17.2)" - -/* 17.3 */ - edge4way cwell space 5 ~(allNActive)/a ~(allNActive)/w 5 \\ - "Cap-well spacing to external active must be at least 5 (MOSIS rule #17.3)" active - edge4way cwell space 3 ~(allPOhmic)/a ~(allPOhmic)/w 3 \\ - "P-substrate diffusion and Cap-well must be separated by 3 (MOSIS rule #17.3)" active - - -/* 17.4 */ -/* Need to do this check from the Cap-well plane - in order Not */ -/* to conflict with the general rules for N-diffusion */ - edge4way space cwell 3 (space,poly,pc)/a 0 0 \\ - "Cap-well overlap of diffusion must be at least 3 (MOSIS rule #17.4)" active - -/* ---------------------------------------------------------------- */ -/* Well-capacitor */ -/* ---------------------------------------------------------------- */ -/* These are DRC rules for Well-capacitor (wcap) according to HP's */ -/* 1.2um linear capacitor process pi@isi.edu 9/18/92 */ -/* Rule 18.5 and 18.6 are preliminary, they are conservative here! */ -/* ---------------------------------------------------------------- */ -/* 18.1 */ - width wcap 3 \\ - "Well-capacitor must be at least 3 (MOSIS rule #18.1)" - -/* 18.2 */ -/* achieved by rule 3.5 */ - -/* 18.3 */ - edge4way wcap space 1 poly poly 1 \\ - "Well-capacitor overhang is missing (MOSIS rule #18.3)" - -/* 18.4 */ - edge4way wcap ndiff 3 ndiff ndiff 3 \\ - "N-diffusion overlap of well-capacitor must be at least 3 (MOSIS rule #18.4)" - -/* 18.5 */ -/* achieved by rule 5B.6 */ - spacing wcap pc 2 touching_illegal \\ - "Well-capacitor spacing to poly contact must be at least 2 (MOSIS rule #18.5)" - - -/* 18.6 */ -/* similar to rule 6A.4 or 6B.6 */ - spacing wcap ndc 4 touching_illegal \\ - "Well-capacitor spacing to diffusion contact must be at least 4 (MOSIS rule #18.6)" - - -/* ---------------------------------------------------------------- */ -/* Buried CCD */ -/* ---------------------------------------------------------------- */ -/* 19.1 */ -/* Have to do it seperately... */ - width nbd,nbdc,bd/a 4 \\ - "CCD channel width must be at least 4 (MOSIS rule #19.1)" - width nbdc 4 \\ - "CCD contact width must be at least 4 (MOSIS rule #19.1)" - - -/* 19.2 */ -/* The 4 lambda spacing is a conservative guess here... */ -/* This following rule will NOT work! Need to check 2 planes */ -/* separately.... */ -/* - spacing bd/a,nbd,nbdc bd/a,nbd,nbdc 4 touching_ok \\ - "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" -*/ - edge4way nbd,nbdc ~(bd,nbd,nbdc)/a 4 (bd,space)/i 0 0 \\ - "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" implant - edge4way nbd,nbdc ~(poly,nbd,nbdc)/a 4 ~(poly,nbd,nbdc)/a ~(poly,nbd,nbdc)/a 4 \\ - "CCD channel spacing must be at least 4 (MOSIS rule #19.2)" active - -/* 19.3 + 19.4 + 19.5 */ -/* guaranteed by the CIF output generation */ - -/* 19.6 */ -/* This first one check poly and electrode overhang */ - edge4way bd space 2 nbd,poly,cap,el 0 0 \\ - "CCD channel overhang is missing (MOSIS rule #19.6)" active -/* There is a problem with capacitor overhang, I have no way to do */ -/* it now... */ - -/* MOSIS extension BCCD layout rule */ - spacing nbdc poly,el 1 touching_illegal \\ - "CCD-diffusion contact spacing to poly must be at least 1 (MOSIS CCD rule)" - edge4way nbd poly,el 1 bd 0 0 \\ - "Missing Buried CCD Difussion layer (MOSIS CCD rule)" implant - -/* ---------------------------------------------------------------- */ -/* High-Voltage MOSFETs */ -/* ---------------------------------------------------------------- */ -/* These are DRC rules for AMI 1.5 micron process for high-voltage */ -/* MOSFETs pi@isi.edu 10/01/92 */ -/* */ -/* ---------------------------------------------------------------- */ -/* 20.1 */ -/* Well spacing for different potential must be 12 lambda away now. */ -/* These rules correspond to 1.1 + 1.2 rules */ -/* width rule is as usual */ - edge (~hnwell)/w hnwell 10 hnwell hnwell 10\\ - "High-Voltage N-Well width must be at least 10 (MOSIS rule #1.1)" - edge (~hpwell)/w hpwell 10 hpwell hpwell 10\\ - "High-Voltage P-Well width must be at least 10 (MOSIS rule #1.1)" -/* spacing rules are new */ - edge hnwell space,pw,hpw 9 space,pw,hpw space,pw,hpw 9\\ - "High-Voltage N-Well spacing to N-Well must be at least 9 (MOSIS rule #1.2)" - edge hpwell space,nw,hnw 9 space,nw,hnw space,nw,hnw 9\\ - "High-Voltage P-Well spacing to P-Well must be at least 9 (MOSIS rule #1.2)" - edge hnwell space,pw,hpw,nw 12 space,pw,hpw,nw space,pw,hpw,nw 12\\ - "High-Voltage N-Well spacing must be at least 12 (MOSIS rule #20.1)" - edge hpwell space,nw,hnw,pw 12 space,nw,hnw,pw space,nw,hnw,pw 12\\ - "High-Voltage P-Well spacing must be at least 12 (MOSIS rule #20.1)" - -/* 20.2 */ -/* High-Voltage Active spacing must be at least 5 lambda away */ -/* This rule corresponds to 2.2 rule */ -#define allHVNActive hndiff,hndc/a,hnfet -#define allHVPActive hpdiff,hpdc/a,hpfet - edge4way ~(allHVDiff)/a allHVDiff 3 allHVDiff allHVDiff 3\\ - "High-Voltage Diffusion width must be at least 3 (MOSIS rule #2.1)" - spacing allHVNActive allHVNActive 5 touching_ok \\ - "High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)" - spacing allHVPActive allHVPActive 5 touching_ok \\ - "High-Voltage Diffusion spacing must be at least 5 (MOSIS rule #20.2)" - -/* 20.3 */ -/* High-Voltage transistors spacing to Well edge must be 7 lambda */ -/* This rule corresponds to rule 2.3 */ -/* without explicit well definition */ - spacing hndiff,hndc/a hpdiff,hpdc/a 14 touching_illegal \\ - "P-type diffusion must be 14 away from N-type diffusion (MOSIS rule #20.3)" - spacing hndiff,hndc/a allPDiff 12 touching_illegal \\ - "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)" - spacing hpdiff,hpdc/a allNDiff 12 touching_illegal \\ - "P-type diffusion must be 12 away from N-type diffusion (MOSIS rule #20.3+2.3)" - -/* with explicit well definition */ - spacing hndiff,hnfet,hndc/a hnwell 7 touching_illegal \\ - "HVN-diffusion and HVN-well must be separated by 7 (MOSIS rule #20.3)" - spacing hpdiff,hpfet,hpdc/a hpwell 7 touching_illegal \\ - "HVP-diffusion and HVP-well must be separated by 7 (MOSIS rule #20.3)" - spacing allNOhmic hpwell 3 touching_illegal \\ - "N-substrate diffusion and HVP-well must be separated by 3 (MOSIS rule #2.4+20.3)" - spacing allPOhmic hnwell 3 touching_illegal \\ - "P-substrate diffusion and HVN-well must be separated by 3 (MOSIS rule #2.4+20.3)" - -/* 20.4 */ -/* Poly1 must not be used as an transistor for high-voltage design */ -/* guaranteed by the composition rules */ - -/* 20.5 */ -/* High-Voltage Active overlap of contact is now 2 lambda */ -/* This rule corresponds to rule 6B.2 */ - edge (~hndc)/a hndc/a 6 hndc/a hndc/a 6\\ - "High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)" - edge (~hpdc)/a hpdc/a 6 hpdc/a hpdc/a 6\\ - "High-Voltage Diffusion contact width must be at least 6 (MOSIS rule #20.5)" - -/* 20.6 */ -/* High-Voltage transistor channel length must be at least 4 lambda */ - edge hpdiff,hpdc/a hpfet 4 hpfet 0 0 \\ - "High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)" - edge hndiff,hndc/a hnfet 4 hnfet 0 0 \\ - "High-Voltage transistor must be at least 4 units long (MOSIS rule #20.6)" - - - -/* ---------------------------------------------------------------- */ -/* overlapping rules */ - exact_overlap m3c,m2c,ndc,pdc,pc,psc,nsc,ec,capc,clc,emc,pbc,hndc,hpdc,hnsc,hpsc - no_overlap pfet,nfet pfet,nfet - no_overlap epfet,enfet epfet,enfet - no_overlap pffet,nffet pffet,nffet - no_overlap hpfet,hnfet hpfet,hnfet - -end - - -extract - - - -#ifndef OLD_EXTRACT_STYLE - -#include "scmosExt.tech.in" - -#else -/* In the following, MOSIS provides 9 extraction styles as follows: - - SCNA20(ORB) - ORBIT 2.0 micron low-noise analog N-well CMOS/BJT - process. *default* - SCPE20(ORB) - ORBIT 2.0 micron P-well CMOS/Bulk process. - SCNA16(AMI) - AMI 1.6 micron N-well CMOS/Junction-isolated BJT - process. - SCN12LC(HP) - HP CMOS34 1.2 micron N-well CMOS/Bulk process with - linear capacitor option. - SCNE12(ORB) - ORBIT 1.2 micron 2 poly N/P-well CMOS process. - SCN10(MOT) - MOTOROLA 1.0 micron N-well/P-epi CMOS process. - * Not Available at this moment * - SCN08(HP) - HP CMOS26B 1.0 micron N-well CMOS/Bulk process. - SCN08(IBM) - IBM 0.8 micron N-well CMOS/Bulk process. - * Not Available at this moment * - - Whenever it is available, measured data on MOSIS test structures - is used. Data is obtained from a representitive run (usually the - latest run at the time). If not available, typical (or nominal) - data from vendor wafer specification is used if not specifically - noted. - -*/ - -/* Have to redefine allMetal1 to make it pure metal line here... */ - -#undef allMetal1 -#define allMetal1 m1,m2c/m1 - - -#ifdef STANDARD -style SCNA20(ORB) -/* The following data is obtained from MOSIS run 'n34o' */ -/* Last modified by pi@isi.edu, 9/29/93 */ - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - cscale 1 - lambda 100 - step 100 - /* No parallel wire coupling capacitances */ - sidehalo 0 - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 27260 - resist pdiff,psd,pdc/a,psc/a 59550 - resist allPoly 23430 - resist allPoly2 19690 - resist em,emc/a 27260 - resist pbase,pbc/a 2000000 - resist metal1,m2c/metal1 52 - resist metal2,pad 26 - resist nwell 2505830 - - /* Contact resistance (in milliohms per square) */ - contact pc/a 4 11000 - contact ec/a,capc/a 4 9000 - contact ndc/a,nsc/a 4 18710 - contact pdc/a,psc/a 4 100560 - - /* Area parasitic capacitance to substrate (in attofarads per - lambda square) - [ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ] - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, remove the - following comment. */ - areacap poly,pc/a 39 - areacap metal1,pad,m2c/metal1 24 - areacap metal2 19 -/* - areacap ndiff,ndc/a 220 - areacap pdiff,pdc/a 270 -*/ - areacap cc/a,cap 39 - areacap poly2,ec/a 50 - - /* Inter-layer capacitance */ - overlap metal1 pdiff,ndiff,psd,nsd 47 - overlap metal2 pdiff,ndiff,psd,nsd 22 metal1 - overlap metal1 poly 30 - overlap metal2 poly 19 metal1 - overlap metal2 metal1 45 - overlap metal1 poly2 40 - - /* Perimeter parasitic capacitances (in attofarads per lambda) - [ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ] */ -/* - perimc ndiff,ndc/a space,pwell 559 - perimc pdiff,pdc/a space,nwell 402 -*/ - perimc poly,pc/a space,pwell,nwell 80 - - /* Active devices: N-Well process */ - fet pfet pdiff,pdc,pffet 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc,nffet 2 nfet GND! pwell 0 0 - fet epfet pdiff,pdc,pffet 2 epfet Vdd! 0 0 - fet enfet ndiff,ndc,nffet 2 enfet GND! 0 0 - - /* Kludge for MOS capacitance extraction, where source and drain - are connected together */ - fet pfet pdiff,pdc,pffet 1 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc,nffet 1 nfet GND! pwell 0 0 - - /* Electrode capacitance extraction */ - device capacitor None cap,capc/a poly,pc 120 735 - - /* DRAM capacitance extraction */ - device capacitor None wcap ndiff,ndc 300 0 - - /* bipolar NPN extraction */ - device bjt npn emit,emc/a pbase,pbc/a nwell - -style SCPE20(ORB) - -/* The following data is obtained from MOSIS run 'n35s', 6/93 */ -/* Last modified by pi@isi.edu, 9/29/93 */ - - cscale 1 - lambda 100 - step 100 - /* No parallel wire coupling capacitances */ - sidehalo 0 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 26670 - resist pdiff,psd,pdc/a,psc/a 72860 - resist allPoly 23860 - resist allPoly2 18540 - resist metal1,m2c/metal1 49 - resist metal2,pad 26 - resist pwell 2128280 - - /* Contact resistance (in milliohm per contact) */ - contact pc/a 4 12800 - contact ec/a,capc/a 4 8420 - contact ndc/a,nsc/a 4 36660 - contact pdc/a,psc/a 4 56300 - contact m2c/m1 5 30 - - /* Area parasitic capacitance to substrate (in attofarads per - lambda square) - [ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ] - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, remove the - following comment. */ - areacap poly,pc/a 57 - areacap allMetal1,DiffMetal,HVDiffMetal 41 - areacap PolyMetal,BiMetal,CCDMetal 41 - areacap allMetal2 21 -/* - areacap ndiff,ndc/a 398 - areacap pdiff,pdc/a 230 -*/ - - /* Inter-layer capacitance */ - overlap metal1 pdiff,ndiff,psd,nsd 36 - overlap metal2 pdiff,ndiff,psd,nsd 16 metal1 - overlap metal1 poly 33 - overlap metal2 poly 15 metal1 - overlap metal2 metal1 29 - overlap metal1 poly2,cap 33 - - /* Perimeter parasitic capacitances (in attofarads per lambda) - [ 1 lambda = 1.0 micron ---> multiplication factor 1.0 ] */ -/* - perimc ndiff,ndc/a space,pwell 423 - perimc pdiff,pdc/a space,nwell 85 -*/ - perimc poly,pc/a space,pwell,nwell 168 - - /* Active devices: P-Well process */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - - -style SCNA16(AMI) - -/* The following data is obtained from MOSIS run 'n34l', 6/93 */ -/* Last modified by pi@isi.edu, 9/29/93 */ - - cscale 1 - lambda 80 - step 100 - /* No parallel wire coupling capacitances */ - sidehalo 0 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 51680 - resist pdiff,psd,pdc/a,psc/a 74800 - resist allPoly 34780 - resist allPoly2 22400 - resist allMetal1 48 - resist allMetal2 28 - resist nwell 1446400 - - /* Contact resistance (in milliohm per contact) */ - contact pc 4 61560 - contact ec 4 12010 - contact ndc,nsc 4 45780 - contact pdc,psc 4 32310 - contact m2c 5 37570 - - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.8 micron ---> multiplication factor 0.64 ] - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, remove the - following comment. */ - /* areacap nfet 709 */ - /* areacap pfet 669 */ - areacap poly,pc/a 22 - areacap allMetal1,DiffMetal,HVDiffMetal 15 - areacap PolyMetal,BiMetal,CCDMetal 15 - areacap allMetal2 10 - - /* Inter-layer capacitance */ - overlap allMetal1 ndiff,nsd 27 - overlap allMetal1 pdiff,psd 27 - overlap allMetal2 pdiff,psd 12 metal1 - overlap allMetal1 allPoly 25 - overlap allMetal1 allP2 25 - overlap allMetal2 allPoly 11 metal1 - overlap metal2 metal1 23 - /* Junction capacitance */ -/* - overlap ndiff,ndc/a space,pwell 172 - overlap pdiff,pdc/a space,nwell 200 -*/ - - /* Perimeter parasitic capacitances (in attofarads per lambda) - [ 1 lambda = 0.8 micron ---> multiplication factor 0.8 ] */ -/* - perimc ndiff,ndc/a space,allWell 6 - perimc pdiff,pdc/a space,allWell 68 -*/ - - /* Active devices: N-Well process, */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - - -style SCNE12(ORB) - -/* The following data is obtained from MOSIS run 'n37d', 7/93 */ -/* Last modified by pi@isi.edu, 9/29/93 */ - - cscale 1 - lambda 60 - step 100 - /* No parallel wire coupling capacitances */ - sidehalo 0 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistances (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 43180 - resist pdiff,psd,pdc/a,psc/a 79770 - resist allPoly 22160 - resist allPoly2 21140 - resist allMetal1 51 - resist allMetal2 26 - resist nwell 1195000 - - /* Contact resistances (in milliohm per contact) */ - contact pc 4 13230 - contact ec 4 13510 - contact ndc,nsc 4 56490 - contact pdc,psc 4 181400 - contact m2c 5 43330 - - - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.6 micron ---> multiplication factor 0.36 ] - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, remove the - following comment. */ - /* areacap nfet 454 */ - /* areacap pfet 368 */ - areacap poly,pc/a 29 - areacap allMetal1,DiffMetal,HVDiffMetal 16 - areacap PolyMetal,BiMetal,CCDMetal 16 - areacap allMetal2 10 - - overlap allMetal1 ndiff,ndc/a 22 - overlap allMetal1 allPoly 19 - overlap allMetal1 allP2 21 - overlap allMetal2 ndiff,ndc/a 8 - overlap allMetal2 allPoly 7 - overlap metal2 metal1 12 - /* Junction capacitance */ - overlap ndiff,ndc/a space,pwell 185 - overlap pdiff,pdc/a space,nwell 148 - - /* Perimeter parasitic capacitances (in attofarads per lambda) - [ 1 lambda = 0.6 micron ---> multiplication factor 0.6 ] */ - perimc allMetal1 space,allWell 41 - perimc allMetal2 space,allWell 42 - /* Junction capacitances */ -/* - perimc ndiff,ndc/a space,pwell 236 - perimc pdiff,pdc/a space,nwell 147 -*/ - - /* No measurements for this run, but leave here for future... - sideoverlap allMetal1 space,allWell PNplus 60 - sideoverlap allMetal2 space,allWell allPoly 60 - sideoverlap allMetal2 space,allWell PNplus 57 - sideoverlap allMetal2 space,allWell allPoly 57 - sideoverlap allMetal2 space,allWell allMetal1 64 - */ - - /* Nwell process, so PMOS has "nwell" defined for analog - designs... */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - - -#endif /* STANDARD */ - -#ifdef TIGHTMETAL -style SCN12LC(HP) - -/* The following data is obtained from MOSIS run 'n36y', 7/93 */ -/* Last modified by pi@isi.edu, 9/29/93 */ - - cscale 1 - lambda 60 - step 100 - /* No parallel wire coupling capacitances */ - sidehalo 0 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nnd,ndc/a,nsc/a 74630 - resist pdiff,ppd,pdc/a,psc/a 109590 - resist poly,pc/a,pfet,nfet 26620 - resist allMetal1 60 - resist allMetal2 39 - resist nwell 1500000 - - /* Contact resistance (in milliohm per contact) */ - contact ndc 4 77000 - contact pdc 4 44260 - contact pc 4 16210 - contact m2c 5 86560 - - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.6 micron ---> multiplication factor 0.36 ] - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, remove the - following comment. */ - /* areacap nfet 556 */ - /* areacap pfet 489 */ - areacap poly,pc/a 22 - areacap allMetal1,DiffMetal,HVDiffMetal 14 - areacap PolyMetal,BiMetal,CCDMetal 14 - areacap allMetal2 9 - - /* Inter-layer capacitance */ - overlap allMetal1 allPoly 24 - overlap allMetal2 allPoly 7 metal1 - overlap metal2 metal1 14 - /* Junction capacitance */ -/* - overlap ndiff,ndc/a space,pwell 106 - overlap pdiff,pdc/a space,nwell 183 -*/ - - /* Perimeter parasitic capacitances (in attofarads per lambda) - [ 1 lambda = 0.6 micron ---> multiplication factor 0.6 ] */ - /* perimc nfet ndiff 90 */ - /* perimc pfet pdiff 817 */ - /* Junction capacitances */ -/* - perimc ndiff,ndc/a space,allWell 102 - perimc pdiff,pdc/a space,allWell 2 -*/ - - /* Active devices: Nwell process, so PMOS has "nwell" defined - for analog designs... */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - /* Kludge for DRAM capacitance extraction */ - fet wcap ndiff,ndc 1 wcap GND! 300 0 - -/* These stuff are experimental..... - fake npn: - fet emit,emc/a pbase 1 d1np XSLLU! nwell 0 0 - fet fpb nwell 1 d2pn YSLLU! col,clc 0 0 - */ - -/* saturation :: R = V (5V) / Idss - fetresist nfet saturation 12000 - fetresist pfet saturation 28000 - fetresist enfet saturation 12000 - fetresist epfet saturation 28000 - - I am not sure how to do this yet, so I give the same value as - saturation! - - fetresist nfet linear 12000 - fetresist pfet linear 28000 - fetresist enfet linear 12000 - fetresist epfet linear 28000 - */ - - -style SCN08(HP) - -/* The following data is obtained from MOSIS run 'n33h', 7/93 */ -/* Last modified by pi@isi.edu, 9/29/93 */ - - cscale 1 - lambda 50 - step 100 - /* Parallel wire coupling capacitance enabled */ - sidehalo 8 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 2280 - resist pdiff,psd,pdc/a,psc/a 1990 - resist poly 3480 - resist allMetal1 67 - resist allMetal2 65 - resist allMetal3 29 - resist nwell 1265560 - - /* Contact resistance (in milliohm per contact) */ - contact pc 4 1680 - contact ndc,pdc,nsc,psc 4 1100 - contact m2c 5 305 - contact m3c 5 259 - - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.5 micron ---> multiplication factor 0.25 ] - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, remove the - following comment. */ - /* areacap nfet 457 */ - /* areacap pfet 403 */ - areacap poly,pc/a 16 - areacap allMetal1,DiffMetal,HVDiffMetal 9 - areacap PolyMetal,BiMetal,CCDMetal 9 - areacap allMetal2 5 - areacap allMetal3 4 - - /* Inter-layer capacitance */ - overlap allMetal1 PNplus 13 - overlap allMetal1 allPoly 13 - overlap allMetal2 PNplus 4 - overlap allMetal2 allPoly 4 - overlap allMetal2 allMetal1 6 - overlap allMetal3 PNplus 2 - overlap allMetal3 allPoly 2 - overlap allMetal3 allMetal1 3 - overlap allMetal3 allMetal2 7 - /* Junction capacitance */ - overlap ndiff,ndc/a space,pwell 27 - overlap pdiff,pdc/a space,nwell 148 - - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.5 micron ---> multiplication factor 0.5 ] */ - perimc allMetal1 space,allWell 43 - perimc allMetal2 space,allWell 36 - perimc allMetal3 space,allWell 36 - - sideoverlap allMetal1 space,allWell allPoly 14 - sideoverlap allMetal2 space,allWell allPoly 5 - /* no such data for m2-to-m1, use data from specification file */ - sideoverlap allMetal2 space,allWell allMetal1 13 - sideoverlap allMetal3 space,allWell allPoly 1 - sideoverlap allMetal3 space,allWell allMetal1 4 - sideoverlap allMetal3 space,allWell allMetal2 13 - - /* Active devices: N-well process */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - -#endif /* TIGHTMETAL */ - -#ifdef IBMTECH -style SCN08(IBM) - -/* The following data is obtained from MOSIS run 'n42s', 1/94 */ -/* Last modified by pi@isi.edu, 6/27/94 */ - - cscale 1 - lambda 40 - step 100 - /* Parallel wire coupling capacitance disabled */ - sidehalo 0 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 3300 - resist pdiff,psd,pdc/a,psc/a 3180 - resist poly 3630 - resist allMetal1 43 - resist allMetal2 36 - resist allMetal3 36 - /* not monitored on PCM, use specification value */ - resist nwell 520000 - - /* Contact resistance (in milliohm per contact) */ - contact ndc,nsc 4 2530 - contact pc 4 7510 - contact pdc,psc 4 2160 - contact m2c 5 330 - contact m3c 5 292 - - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.4 micron ---> multiplication factor 0.16 ] */ -#endif /* IBMTECH */ - -#ifdef SUBMICRON -style SCN08(HP26G) - -/* The following data is obtained from MOSIS run 'n48r', 10/94 */ -/* Last modified by pi@isi.edu, 11/02/94 */ - - cscale 1 - lambda 40 - step 100 - /* Parallel wire coupling capacitance enabled */ - sidehalo 8 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 2375 - resist pdiff,psd,pdc/a,psc/a 2000 - resist allPoly 2350 - resist allMetal1 70 - resist allMetal2 67 - resist allMetal3 30 - resist nwell 1265000 - - /* Contact resistance (in milliohm per contact) */ - contact pc 4 1250 - contact ndc,nsc 4 1300 - contact pdc,psc 4 1125 - contact m2c 5 430 - contact m3c 5 300 - - /* The following are 10 types of capacitance extracted: - 1. poly to substrate. - 2. metal1 to substrate. - 3. metal1 to poly. - 4. metal2 to substrate. - 5. metal2 to poly. - 6. metal2 to metal1. - 7. metal3 to substrate. - 8. metal3 to poly. - 9. metal3 to metal1. - 10. metal3 to metal2. - - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, - remove the following comment. */ - /* areacap nfet 334 */ - /* areacap pfet 315 */ - - /* Type 1,2,4,7 (to substrate) */ - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.4 micron ---> multiplication factor 0.16 ] */ - areacap poly,pc/a 13 - areacap allMetal1,DiffMetal,HVDiffMetal 6 - areacap PolyMetal,BiMetal,CCDMetal 6 - areacap allMetal2 3 - areacap allMetal3 2 - - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.4 micron ---> multiplication factor 0.4 ] */ - perimc poly,pc/a ~(poly,pc/a) 19 - perimc allMetal1 ~(allMetal1) 20 - perimc allMetal2 ~(allMetal2) 16 - perimc allMetal3 ~(allMetal3) 14 - - /* Inter-layer capacitance, type 3,5,6,8,9,10 */ - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.4 micron ---> multiplication factor 0.16 ] */ - overlap allMetal1 allPoly 9 - overlap allMetal2 allPoly 3 - overlap allMetal2 allMetal1 5 - overlap allMetal3 allPoly 2 - overlap allMetal3 allMetal1 3 - overlap allMetal3 allMetal2 5 - - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.4 micron ---> multiplication factor 0.4 ] */ - sideoverlap allMetal1 space,allWell allPoly 23 - sideoverlap allMetal2 space,allWell allPoly 17 - sideoverlap allMetal2 space,allWell allMetal1 19 - sideoverlap allMetal3 space,allWell allPoly 15 - sideoverlap allMetal3 space,allWell allMetal1 17 - sideoverlap allMetal3 space,allWell allMetal2 21 - - /* Cross-couple capacitance */ - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.4 micron ---> multiplication factor 0.4 ] */ - sidewall allP ~(allP) ~(allP) allP 11 - sidewall allMetal1 ~(allMetal1) ~(allMetal1) allMetal1 24 - sidewall allMetal2 ~(allMetal2) ~(allMetal2) allMetal2 27 - sidewall allMetal3 ~(allMetal3) ~(allMetal3) allMetal3 39 - - /* Active devices: N-well process */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - - -style SCN06(HP14B) - -/* Not yet.... */ -/* Last modified by pi@isi.edu, 03/10/95 */ - - cscale 1 - lambda 30 - step 100 - /* Parallel wire coupling capacitance enabled */ - sidehalo 8 - - /* Define plane order first */ -#ifdef V5 - planeorder well 0 - planeorder implant 1 - planeorder active 2 - planeorder metal1 3 - planeorder metal2 4 - planeorder metal3 5 - planeorder oxide 6 -#endif - - /* Sheet resistance (in milliohms per square) */ - resist ndiff,nsd,ndc/a,nsc/a 2375 - resist pdiff,psd,pdc/a,psc/a 2000 - resist allPoly 2350 - resist allMetal1 70 - resist allMetal2 67 - resist allMetal3 30 - resist nwell 1265000 - - /* Contact resistance (in milliohm per contact) */ - contact pc 4 1250 - contact ndc,nsc 4 1300 - contact pdc,psc 4 1125 - contact m2c 5 430 - contact m3c 5 300 - - /* The following are 10 types of capacitance extracted: - 1. poly to substrate. - 2. metal1 to substrate. - 3. metal1 to poly. - 4. metal2 to substrate. - 5. metal2 to poly. - 6. metal2 to metal1. - 7. metal3 to substrate. - 8. metal3 to poly. - 9. metal3 to metal1. - 10. metal3 to metal2. - - NOTE: Since most of the simulation tools have already - included the gate-oxide capacitance, it is NOT - extracted here. If you need it explictly, - remove the following comment. */ - /* areacap nfet 334 */ - /* areacap pfet 315 */ - - /* Type 1,2,4,7 (to substrate) */ - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.3 micron ---> multiplication factor 0.09 ] */ - areacap poly,pc/a 7 - areacap allMetal1,DiffMetal,HVDiffMetal 3 - areacap PolyMetal,BiMetal,CCDMetal 3 - areacap allMetal2 1 - areacap allMetal3 1 - - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.3 micron ---> multiplication factor 0.3 ] */ - perimc poly,pc/a ~(poly,pc/a) 14 - perimc allMetal1 ~(allMetal1) 15 - perimc allMetal2 ~(allMetal2) 12 - perimc allMetal3 ~(allMetal3) 10 - - /* Inter-layer capacitance, type 3,5,6,8,9,10 */ - /* Area parasitic capacitances (in attofarads per lambda square) - [ 1 lambda = 0.3 micron ---> multiplication factor 0.09 ] */ - overlap allMetal1 allPoly 5 - overlap allMetal2 allPoly 2 - overlap allMetal2 allMetal1 3 - overlap allMetal3 allPoly 1 - overlap allMetal3 allMetal1 1 - overlap allMetal3 allMetal2 3 - - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.3 micron ---> multiplication factor 0.3 ] */ - sideoverlap allMetal1 space,allWell allPoly 17 - sideoverlap allMetal2 space,allWell allPoly 14 - sideoverlap allMetal2 space,allWell allMetal1 15 - sideoverlap allMetal3 space,allWell allPoly 11 - sideoverlap allMetal3 space,allWell allMetal1 13 - sideoverlap allMetal3 space,allWell allMetal2 16 - - /* Cross-couple capacitance */ - /* Perimeter parasitic capacitance (in attofarads per lambda) - [ 1 lambda = 0.3 micron ---> multiplication factor 0.3 ] */ - sidewall allP ~(allP) ~(allP) allP 9 - sidewall allMetal1 ~(allMetal1) ~(allMetal1) allMetal1 19 - sidewall allMetal2 ~(allMetal2) ~(allMetal2) allMetal2 21 - sidewall allMetal3 ~(allMetal3) ~(allMetal3) allMetal3 31 - - /* Active devices: N-well process */ - fet pfet pdiff,pdc 2 pfet Vdd! nwell 0 0 - fet nfet ndiff,ndc 2 nfet GND! pwell 0 0 - -#endif /* SUBMICRON */ - -#endif /* OLD_EXTRACT_STYLE */ -end - - -wiring - contact pdcontact 4 pdiff 0 metal1 0 - contact ndcontact 4 ndiff 0 metal1 0 - contact pcontact 4 poly 0 metal1 0 - contact ec 6 poly2 0 metal1 0 - contact m2contact 4 metal1 0 metal2 0 - contact m3contact 5 metal2 0 metal3 0 -end - -router - layer1 metal1 3 allMetal1 3 - layer2 metal2 3 allMetal2 4 allPoly,allDiff 1 - contacts m2contact 4 - gridspacing 8 -end - -plowing - fixed allFet,glass,pad - covered allFet - drag allFet -end - -plot - /* based on Jeffrey C. Gealow's (jgealow@mtl.mit.edu) contribution */ - style colorversatec - - ndiff,ndc yellow \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA - - ndiff,ndc cyan \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 - - - nsd,nsc,col,clc yellow \\ - 1515 2A2A 5151 A2A2 \\ - 1515 2A2A 5151 A2A2 \\ - 1515 2A2A 5151 A2A2 \\ - 1515 2A2A 5151 A2A2 - - nsd,nsc,col,clc cyan \\ - 0000 1515 0000 5151 \\ - 0000 1515 0000 5151 \\ - 0000 1515 0000 5151 \\ - 0000 1515 0000 5151 - - - pdiff,pdc yellow \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA - - pdiff,pdc cyan \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 - - pdiff,pdc magenta \\ - AAAA 0000 AAAA 0000 \\ - AAAA 0000 AAAA 0000 \\ - AAAA 0000 AAAA 0000 \\ - AAAA 0000 AAAA 0000 - - - psd,psc yellow \\ - 1515 2A2A 5151 A2A2 \\ - 1515 2A2A 5151 A2A2 \\ - 1515 2A2A 5151 A2A2 \\ - 1515 2A2A 5151 A2A2 - - psd,psc cyan \\ - 0000 1515 0000 5151 \\ - 0000 1515 0000 5151 \\ - 0000 1515 0000 5151 \\ - 0000 1515 0000 5151 - - psd,psc magenta \\ - 2A2A 0000 A2A2 0000 \\ - 2A2A 0000 A2A2 0000 \\ - 2A2A 0000 A2A2 0000 \\ - 2A2A 0000 A2A2 0000 - - - poly,pc/a magenta \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA - - - poly2,ec/a yellow \\ - FFFF FFFF FFFF FFFF \\ - FFFF FFFF FFFF FFFF \\ - FFFF FFFF FFFF FFFF \\ - FFFF FFFF FFFF FFFF - - - nfet yellow \\ - 0505 8282 1414 0A0A \\ - 5050 2828 4141 A0A0 \\ - 0505 8282 1414 0A0A \\ - 5050 2828 4141 A0A0 - - nfet cyan \\ - 0000 0505 0000 1414 \\ - 0000 5050 0000 4141 \\ - 0000 0505 0000 1414 \\ - 0000 5050 0000 4141 - - nfet magenta \\ - 5050 2828 4141 A0A0 \\ - 0505 8282 1414 0A0A \\ - 5050 2828 4141 A0A0 \\ - 0505 8282 1414 0A0A - - - enfet yellow \\ - BABA 7575 EAEA D5D5 \\ - ABAB 5757 AEAE 5D5D \\ - BABA 7575 EAEA D5D5 \\ - ABAB 5757 AEAE 5D5D - - enfet cyan \\ - 4141 0A0A 0505 2828 \\ - 1414 A0A0 5050 8282 \\ - 4141 0A0A 0505 2828 \\ - 1414 A0A0 5050 8282 - - - nffet yellow \\ - 8E8E 0707 8B8B D5D5 \\ - E8E8 7070 B8B8 5D5D \\ - 8E8E 0707 8B8B D5D5 \\ - E8E8 7070 B8B8 5D5D - - nffet cyan \\ - 0101 0808 1414 2828 \\ - 1010 8080 4141 8282 \\ - 0101 0808 1414 2828 \\ - 1010 8080 4141 8282 - - nffet magenta \\ - 5050 A0A0 4040 0202 \\ - 0505 0A0A 0404 2020 \\ - 5050 A0A0 4040 0202 \\ - 0505 0A0A 0404 2020 - - - pfet yellow \\ - 6363 A0A0 5050 2828 \\ - 3636 0A0A 0505 8282 \\ - 6363 A0A0 5050 2828 \\ - 3636 0A0A 0505 8282 - - pfet cyan \\ - 0000 5151 0000 5454 \\ - 0000 1515 0000 1515 \\ - 0000 5151 0000 5454 \\ - 0000 1515 0000 1515 - - pfet magenta \\ - 9494 0A0A 2525 8282 \\ - 4949 A0A0 5252 2828 \\ - 9494 0A0A 2525 8282 \\ - 4949 A0A0 5252 2828 - - - epfet yellow \\ - BCBC 4F4F 2F2F D3D3 \\ - CBCB F4F4 F2F2 3D3D \\ - BCBC 4F4F 2F2F D3D3 \\ - CBCB F4F4 F2F2 3D3D - - epfet cyan \\ - 0000 A0A0 0000 2828 \\ - 0000 0A0A 0000 8282 \\ - 0000 A0A0 0000 2828 \\ - 0000 0A0A 0000 8282 - - epfet magenta \\ - 4141 0000 5050 0000 \\ - 1414 0000 0505 0000 \\ - 4141 0000 5050 0000 \\ - 1414 0000 0505 0000 - - - pffet yellow \\ - 7B7B F0F0 F0F0 E9E9 \\ - B7B7 0F0F 0F0F 9E9E \\ - 7B7B F0F0 F0F0 E9E9 \\ - B7B7 0F0F 0F0F 9E9E - - pffet cyan \\ - 0000 0101 0000 1414 \\ - 0000 1010 0000 4141 \\ - 0000 0101 0000 1414 \\ - 0000 1010 0000 4141 - - pffet magenta \\ - 8484 0A0A 2525 8282 \\ - 4848 A0A0 5252 2828 \\ - 8484 0A0A 2525 8282 \\ - 4848 A0A0 5252 2828 - - - cap,cc/a yellow \\ - 3E3E 7777 E3E3 C1C1 \\ - E3E3 7777 3E3E 1C1C \\ - 3E3E 7777 E3E3 C1C1 \\ - E3E3 7777 3E3E 1C1C - - cap,cc/a magenta \\ - 4141 8888 1414 2A2A \\ - 1414 8888 4141 A2A2 \\ - 4141 8888 1414 2A2A \\ - 1414 8888 4141 A2A2 - - - allMetal1 cyan \\ - AAAA 0000 AAAA 0000 \\ - AAAA 0000 AAAA 0000 \\ - AAAA 0000 AAAA 0000 \\ - AAAA 0000 AAAA 0000 - - - allMetal2 cyan \\ - 0000 1111 0000 4444 \\ - 0000 1111 0000 4444 \\ - 0000 1111 0000 4444 \\ - 0000 1111 0000 4444 - - allMetal2 magenta \\ - 0000 4444 0000 1111 \\ - 0000 4444 0000 1111 \\ - 0000 4444 0000 1111 \\ - 0000 4444 0000 1111 - - - m2c/m1 black \\ - 0000 6666 6666 0000 \\ - 0000 9999 9999 0000 \\ - 0000 6666 6666 0000 \\ - 0000 9999 9999 0000 - - - pad,glass black \\ - 0300 0700 0E00 1C00 \\ - 3800 7000 E000 C000 \\ - 00C0 00E0 0070 0038 \\ - 001C 000E 0007 0003 - - - nwell yellow \\ - 0800 1000 2000 4000 \\ - 8000 0001 0002 0004 \\ - 0008 0010 0020 0040 \\ - 0080 0010 0200 0400 - - nwell cyan \\ - 1000 2000 4000 8000 \\ - 0001 0002 0004 0008 \\ - 0010 0020 0040 0080 \\ - 0100 0200 0400 0800 - - - pwell yellow \\ - 1000 0400 0400 0100 \\ - 0100 0040 0040 0010 \\ - 0010 0004 0004 0001 \\ - 0001 4000 4000 1000 - - pwell cyan \\ - 0000 0800 0000 0200 \\ - 0000 0080 0000 0020 \\ - 0000 0008 0000 0002 \\ - 0000 8000 0000 2000 - - pwell magenta \\ - 0800 0000 0200 0000 \\ - 0080 0000 0020 0000 \\ - 0008 0000 0002 0000 \\ - 8000 0000 2000 0000 - - - bd yellow \\ - 4444 8888 4444 8888 \\ - 4444 8888 4444 8888 \\ - 4444 8888 4444 8888 \\ - 4444 8888 4444 8888 - - bd cyan \\ - 0000 4444 0000 4444 \\ - 0000 4444 0000 4444 \\ - 0000 4444 0000 4444 \\ - 0000 4444 0000 4444 - - bd magenta \\ - 8888 0000 8888 0000 \\ - 8888 0000 8888 0000 \\ - 8888 0000 8888 0000 \\ - 8888 0000 8888 0000 - - - nbd,nbdc yellow \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA \\ - 5555 AAAA 5555 AAAA - - nbd,nbdc cyan \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 \\ - 0000 5555 0000 5555 - - nbd,nbdc magenta \\ - 8888 0000 8888 0000 \\ - 8888 0000 8888 0000 \\ - 8888 0000 8888 0000 \\ - 8888 0000 8888 0000 - - - em,emc yellow \\ - 4444 8888 4444 8888 \\ - 4444 8888 4444 8888 \\ - 4444 8888 4444 8888 \\ - 4444 8888 4444 8888 - - em,emc cyan \\ - 0000 4444 0000 4444 \\ - 0000 4444 0000 4444 \\ - 0000 4444 0000 4444 \\ - 0000 4444 0000 4444 - - - pbase,pbc yellow \\ - 5555 AAAA 0000 0000 \\ - 5555 AAAA 0000 0000 \\ - 5555 AAAA 0000 0000 \\ - 5555 AAAA 0000 0000 - - pbase,pbc cyan \\ - 0000 5555 0000 0000 \\ - 0000 5555 0000 0000 \\ - 0000 5555 0000 0000 \\ - 0000 5555 0000 0000 - - pbase,pbc magenta \\ - AAAA 0000 0000 0000 \\ - AAAA 0000 0000 0000 \\ - AAAA 0000 0000 0000 \\ - AAAA 0000 0000 0000 - - - allMetal3 black \\ - 0100 0000 0000 0000 \\ - 1010 0000 0000 0000 \\ - 0001 0000 0000 0000 \\ - 1010 0000 0000 0000 - - allMetal3 cyan \\ - 0280 0000 0820 0000 \\ - 2008 0000 8002 0000 \\ - 8002 0000 2008 0000 \\ - 0820 0000 0280 0000 - - allMetal3 magenta \\ - 0100 06C0 0440 1830 \\ - 1010 600C 4004 8003 \\ - 0001 C006 4004 3018 \\ - 1010 0C60 0440 0380 - - - m3c/m2 black \\ - 0820 0820 0820 0FE0 \\ - E00F 2008 2008 2008 \\ - 2008 2008 2008 E00F \\ - 0000 0FE0 0820 0820 - - - error_p,error_s,error_ps black \\ - 0000 3C3C 4646 4A4A \\ - 5252 6262 3C3C 0000 \\ - 0000 3C3C 4646 4A4A \\ - 5252 6262 3C3C 0000 - - - magnet yellow \\ - AAAA 0000 5555 0000 \\ - AAAA 0000 5555 0000 \\ - AAAA 0000 5555 0000 \\ - AAAA 0000 5555 0000 - - - fence magenta \\ - FFFF 0000 0000 0000 \\ - 0000 0000 0000 0000 \\ - FFFF 0000 0000 0000 \\ - 0000 0000 0000 0000 - - - rotate cyan \\ - 0000 E0E0 E0E0 E0E0 \\ - 0000 0000 0000 0000 \\ - 0000 E0E0 E0E0 E0E0 \\ - 0000 0000 0000 0000 - - - allCut,BiCut X - - - style versatec - - pfet \\ - 07c0 0f80 1f00 3e00 \\ - 7c00 f800 f001 e003 \\ - c007 800f 001f 003e \\ - 00c7 00f8 01f0 03e0 - - - nfet \\ - 1f00 0f80 07c0 03e0 \\ - 01f0 00f8 007c 003e \\ - 001f 800f c007 e003 \\ - f001 f800 7c00 3e00 - - - m2c \\ - c3c3 c3c3 0000 0000 \\ - 0000 0000 c3c3 c3c3 \\ - c3c3 c3c3 0000 0000 \\ - 0000 0000 c3c3 c3c3 - - - pwell \\ - 2020 2020 2020 2020 \\ - 2020 2020 2020 2020 \\ - 0000 0000 0000 0000 \\ - 0000 0000 0000 0000 - - - nwell \\ - 0808 0404 0202 0101 \\ - 0000 0000 0000 0000 \\ - 0808 0404 0202 0101 \\ - 0000 0000 0000 0000 - - - allPoly \\ - 0808 0400 0202 0101 \\ - 8080 4000 2020 1010 \\ - 0808 0004 0202 0101 \\ - 8080 0040 2020 1010 - - - allMetal1 \\ - 8080 0000 0000 0000 \\ - 0808 0000 0000 0000 \\ - 8080 0000 0000 0000 \\ - 0808 0000 0000 0000 - - - pad,glass \\ - 0000 0000 1c1c 3e3e \\ - 3636 3e3e 1c1c 0000 \\ - 0000 0000 1c1c 3e3e \\ - 3636 3e3e 1c1c 0000 - - - nsd,nsc,col,clc \\ - 0808 1414 2222 4141 \\ - 8080 4040 2020 1010 \\ - 0808 1414 2222 4141 \\ - 8080 4040 2020 1010 - - - allMetal2 \\ - 0000 1111 0000 0000 \\ - 0000 1111 0000 0000 \\ - 0000 1111 0000 0000 \\ - 0000 1111 0000 0000 - - - pdiff,pdc,pfet \\ - 0000 0808 5555 8080 \\ - 0000 8080 5555 0808 \\ - 0000 0808 5555 8080 \\ - 0000 8080 5555 0808 - - - psd,psc \\ - 1414 2222 0000 2222 \\ - 4141 2222 0000 2222 \\ - 1414 2222 0000 2222 \\ - 4141 2222 0000 2222 - - - ndiff,nfet,ndc \\ - 0808 1010 2020 4040 \\ - 8080 4141 2222 1414 \\ - 0808 1010 2020 4040 \\ - 8080 4141 2222 1414 - - - allPoly2 \\ - 0000 2020 5050 2020 \\ - 0000 0202 0505 0202 \\ - 0000 2020 5050 2020 \\ - 0000 0202 0505 0202 - - - allCut,BiCut X - -/* -------------------------------------------------------------- */ - style gremlin - pfet 9 - nfet 10 - m2c 11 - pwell 15 - nwell 16 - allPoly 19 - allMetal1 22 - pad,glass 23 - nsd,nsc 24 - allMetal2 28 - pdiff,pdc,pfet 29 - psd,psc 30 - ndiff,nfet,ndc 31 - m2c/m1,pc/m1,ndc/m1,pdc/m1,psc/m1,nsc/m1,pad/m1 X -/* -------------------------------------------------------------- */ - style postscript -/* - * stipple definitions for 32x8 bitmaps - * # row1 row2 row3 row4 row5 row6 row7 row8 - */ - 1 C0C0C0C0 C0C0C0C0 00000000 00000000 0C0C0C0C 0C0C0C0C 00000000 00000000 - 2 A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A A0A0A0A0 0A0A0A0A - 3 00030003 000C000C 00300030 00C000C0 03000300 0C000C00 30003000 C000C000 - 4 00000000 00000000 C0C0C0C0 00000000 00000000 00000000 0C0C0C0C 00000000 - 5 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF - 6 07070707 0E0E0E0E 1C1C1C1C 38383838 70707070 E0E0E0E0 C1C1C1C1 83838383 - 7 18181818 30303030 60606060 C0C0C0C0 81818181 03030303 06060606 0C0C0C0C - 8 18181818 0C0C0C0C 06060606 03030303 81818181 C0C0C0C0 60606060 30303030 - 9 18181818 3C3C3C3C 3C3C3C3C 18181818 81818181 C3C3C3C3 C3C3C3C3 81818181 - 10 F0F0F0F0 60606060 06060606 0F0F0F0F 0F0F0F0F 06060606 60606060 F0F0F0F0 - 11 01000080 02000040 0C000030 F000000F 000FF000 00300C00 00400200 00800100 - 12 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 - 13 00000000 00000000 33333333 33333333 00000000 00000000 CCCCCCCC CCCCCCCC -/* - * color definitions in CMYK format - * # C M Y K closest named color in RGB space - */ - 1 47 95 111 0 /* RosyBrown3 */ - 2 223 31 223 0 /* limegreen */ - 3 0 0 0 192 /* gray25 */ - 4 31 111 31 0 /* plum */ - 5 31 111 255 0 /* orange2 */ - 6 63 95 191 0 /* goldenrod3 */ - 7 255 63 255 0 /* green3 */ - 8 0 0 0 127 /* gray50 */ - 9 223 47 223 0 /* limegreen */ - 10 0 255 255 0 /* red */ - 11 0 0 255 0 /* yellow */ - 12 191 127 0 0 /* RoyalBlue1 */ - 13 95 223 63 0 /* DarkOrchid3 */ - 14 0 0 0 255 /* black */ - 15 191 127 63 0 /* steelblue */ - 16 111 151 244 0 /* goldenrod4 */ - 17 23 175 183 0 /* tomato2 */ -/* - * magic layer definitions (plotted top to bottom) - * layer(s) color# stipple# (plus B=box, X=cross & box) - */ - cc,pc,ndc,pdc,psc,nsc 14 X - m2c,pad,glass 14 B - pad,glass 14 11 - m2c 14 13 - m2,m2c,pad 13 10 - pdc,ndc,psc,nsc,hpdc,hndc,hpsc,hnsc,pc,ec,capc,clc,emc,pbc,nbdc,m1,m2c,gc 12 9 - cap,cc,poly2 11 7 - nsd,nsc 7 1 - psd,psc 6 1 - nfet,nffet 9 8 - pfet,wcap,pffet 1 7 - poly,pc,cap,cc 10 5 - nfet 16 5 - pfet,wcap 17 5 - pdiff,pdc,pffet 1 5 - ndiff,ndc,nffet 9 5 - pwell 1 4 - nwell 2 4 - -/* ------------------------------------------------------------------------ */ - style pnm - draw metal1 - draw metal2 - draw polysilicon - draw ndiffusion - draw pdiffusion - draw ntransistor - draw ptransistor - map psubstratepdiff pdiffusion - map nsubstratendiff ndiffusion - map polycontact polysilicon metal1 - map m2contact metal1 metal2 - map m3contact metal2 metal3 - map ndcontact ndiffusion metal1 - map pdcontact pdiffusion metal1 - map nsubstratencontact ndiffusion metal1 - map psubstratepcontact pdiffusion metal1 - -end diff --git a/scripts/configure b/scripts/configure index 2114738f..a2d9cb28 100755 --- a/scripts/configure +++ b/scripts/configure @@ -628,7 +628,7 @@ OA_LIBS OA MAGIC_REVISION MAGIC_VERSION -SCPP +MSED MCPP LD_RUN_PATH SHLIB_CFLAGS @@ -672,12 +672,11 @@ X_LIBS X_PRE_LIBS X_CFLAGS XMKMF +PYTHON3 CSH GCORE EGREP GREP -PYTHON3 -M4 RANLIB INSTALL_DATA INSTALL_SCRIPT @@ -4038,114 +4037,6 @@ else fi -for ac_prog in gm4 gnum4 m4 -do - # Extract the first word of "$ac_prog", so it can be a program name with args. -set dummy $ac_prog; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_path_M4+:} false; then : - $as_echo_n "(cached) " >&6 -else - case $M4 in - [\\/]* | ?:[\\/]*) - ac_cv_path_M4="$M4" # Let the user override the test with a path. - ;; - *) - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_path_M4="$as_dir/$ac_word$ac_exec_ext" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done - done -IFS=$as_save_IFS - - ;; -esac -fi -M4=$ac_cv_path_M4 -if test -n "$M4"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $M4" >&5 -$as_echo "$M4" >&6; } -else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } -fi - - - test -n "$M4" && break -done -test -n "$M4" || M4="no" - -if test x$M4 = xno; then - as_fn_error $? "M4 is required" "$LINENO" 5 -fi - -# Extract the first word of "python3", so it can be a program name with args. -set dummy python3; ac_word=$2 -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 -$as_echo_n "checking for $ac_word... " >&6; } -if ${ac_cv_path_PYTHON3+:} false; then : - $as_echo_n "(cached) " >&6 -else - case $PYTHON3 in - [\\/]* | ?:[\\/]*) - ac_cv_path_PYTHON3="$PYTHON3" # Let the user override the test with a path. - ;; - *) - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -for as_dir in $PATH -do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do - if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_path_PYTHON3="$as_dir/$ac_word$ac_exec_ext" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 - fi -done - done -IFS=$as_save_IFS - - test -z "$ac_cv_path_PYTHON3" && ac_cv_path_PYTHON3="no" - ;; -esac -fi -PYTHON3=$ac_cv_path_PYTHON3 -if test -n "$PYTHON3"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $PYTHON3" >&5 -$as_echo "$PYTHON3" >&6; } -else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -$as_echo "no" >&6; } -fi - - -if test "x${PYTHON3}" == "x"; then - - - if test "$CPP" = "$CC -E" ; then - MCPP="$CPP -x c" - fi - -else - MCPP="\${MAGICDIR}/scripts/preproc.py" -fi - -if test "$CPP" = "$CC -E" ; then - SCPP="$CPP -x c" -else - SCPP="$CPP" -fi - #------------------------------------------------------------ # AC_PROG_LD - find the path to the GNU or non-GNU linker @@ -5343,6 +5234,7 @@ use_libglu="-lGLU" usingTcl=1 usingOA=0 usingCairo=1 +usingPython3=1 # Extract the first word of "gcore", so it can be a program name with args. @@ -5434,6 +5326,65 @@ if test "x${CSH}" = "x"; then as_fn_error $? "cannot find /bin/csh---cannot compile!" "$LINENO" 5 fi +# Extract the first word of "python3", so it can be a program name with args. +set dummy python3; ac_word=$2 +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 +$as_echo_n "checking for $ac_word... " >&6; } +if ${ac_cv_path_PYTHON3+:} false; then : + $as_echo_n "(cached) " >&6 +else + case $PYTHON3 in + [\\/]* | ?:[\\/]*) + ac_cv_path_PYTHON3="$PYTHON3" # Let the user override the test with a path. + ;; + *) + as_save_IFS=$IFS; IFS=$PATH_SEPARATOR +for as_dir in $PATH +do + IFS=$as_save_IFS + test -z "$as_dir" && as_dir=. + for ac_exec_ext in '' $ac_executable_extensions; do + if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then + ac_cv_path_PYTHON3="$as_dir/$ac_word$ac_exec_ext" + $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 + break 2 + fi +done + done +IFS=$as_save_IFS + + test -z "$ac_cv_path_PYTHON3" && ac_cv_path_PYTHON3="no" + ;; +esac +fi +PYTHON3=$ac_cv_path_PYTHON3 +if test -n "$PYTHON3"; then + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $PYTHON3" >&5 +$as_echo "$PYTHON3" >&6; } +else + { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 +$as_echo "no" >&6; } +fi + + +if test "x${PYTHON3}" == "x"; then + + + usingPython3= + if test "$CPP" = "$CC -E" ; then + MCPP="$CPP -x c" + MSED="sed -e 's/\\/\\\\/'" + else + MCPP="$CPP" + MSED="sed -e 's/\\/\\\\/'" + fi + +else + MCPP="\${MAGICDIR}/scripts/preproc.py -ccomm" + MSED="cat" + usingPython3=1 +fi + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for X" >&5 $as_echo_n "checking for X... " >&6; } @@ -9470,6 +9421,19 @@ else echo fi +${ECHO_N} "Python3: " +if test $usingPython3 ; then + echo "yes" +else + echo "no" + echo + echo " Magic installation will use the gcc preprocessor for forming" + echo " the default SCMOS technology files and the macro definitions." + echo " This usually works, but in case of preprocessor failure, you" + echo " may need python3 installed." + echo +fi + ${ECHO_N} "OpenGL: " if test $usingOGL ; then echo "yes" @@ -9482,14 +9446,18 @@ if test $usingOGL ; then else echo "no" echo - echo " OpenGL graphics are considerably better than the standard 8-bit" - echo " and 24-bit X11 graphics, provided that you have a video card and" - echo " driver supporting accelerated OpenGL graphics. If you get this" - echo " message, you may need to download OpenGL libraries and header" - echo " files, which are usually available from the video card manufacturer." - echo " Magic with un-accelerated OpenGL, such as using Mesa GL without" - echo " a supported graphics card, is usually a very bad combination." - echo + if test $usingCairo ; then + echo " Cairo graphics are available so OpenGL is purely optional." + else + echo " OpenGL graphics are considerably better than the standard 8-bit" + echo " and 24-bit X11 graphics, provided that you have a video card and" + echo " driver supporting accelerated OpenGL graphics. If you get this" + echo " message, you may need to download OpenGL libraries and header" + echo " files, which are usually available from the video card manufacturer." + echo " Magic with un-accelerated OpenGL, such as using Mesa GL without" + echo " a supported graphics card, is usually a very bad combination." + echo + fi fi ${ECHO_N} "Cairo: " @@ -9498,12 +9466,18 @@ if test $usingCairo ; then else echo "no" echo - echo " Cairo graphics are considerably better than the standard 8-bit" - echo " and 24-bit X11 graphics, provided that you have a video card and" - echo " driver supporting hardware-accelerated graphics. If you get this" - echo " message, you may need to download Cairo and fontconfig libraries" - echo " and header files, which are usually found in package cairo-devel." - echo + if test $usingOGL ; then + echo " OpenGL graphics are available so Cairo is purely optional" + echo " unless there are issues with the video card driver's" + echo " implementation of OpenGL." + else + echo " Cairo graphics are considerably better than the standard 8-bit" + echo " and 24-bit X11 graphics, provided that you have a video card and" + echo " driver supporting hardware-accelerated graphics. If you get this" + echo " message, you may need to download Cairo and fontconfig libraries" + echo " and header files, which are usually found in package cairo-devel." + echo + fi fi if test $usingTcl ; then diff --git a/scripts/configure.in b/scripts/configure.in index 306ab304..8a00ba27 100644 --- a/scripts/configure.in +++ b/scripts/configure.in @@ -28,37 +28,6 @@ AC_ISC_POSIX AC_PROG_INSTALL AC_PROG_RANLIB -dnl GNU M4 is preferred due to some of the option switches. -AC_PATH_PROGS([M4], [gm4 gnum4 m4], [no]) -if test x$M4 = xno; then - AC_MSG_ERROR([M4 is required]) -fi - -dnl Python3 is preferred for running the preprocessor script -dnl but CPP can be used instead. -AC_PATH_PROG([PYTHON3], [python3], [no]) -if test "x${PYTHON3}" == "x"; then - - dnl check size of pointer for correct behavior on 64-bit systems - dnl If the C preprocessor is GCC, we need to force the flag to - dnl assert that input files are of type C, or else the preprocessing - dnl stage will not execute correctly on the ".in" files in the scmos - dnl directory. - - if test "$CPP" = "$CC -E" ; then - MCPP="$CPP -x c" - fi - -else - MCPP="\${MAGICDIR}/scripts/preproc.py" -fi - -if test "$CPP" = "$CC -E" ; then - SCPP="$CPP -x c" -else - SCPP="$CPP" -fi - dnl check if the linker is a GNU linker #------------------------------------------------------------ @@ -306,6 +275,7 @@ use_libglu="-lGLU" usingTcl=1 usingOA=0 usingCairo=1 +usingPython3=1 dnl Check for gcore, used by niceabort.c @@ -321,6 +291,32 @@ if test "x${CSH}" = "x"; then AC_MSG_ERROR([cannot find /bin/csh---cannot compile!]) fi +dnl Python3 is preferred for running the preprocessor script +dnl but CPP can be used instead. +AC_PATH_PROG([PYTHON3], [python3], [no]) +if test "x${PYTHON3}" == "x"; then + + dnl check size of pointer for correct behavior on 64-bit systems + dnl If the C preprocessor is GCC, we need to force the flag to + dnl assert that input files are of type C, or else the preprocessing + dnl stage will not execute correctly on the ".in" files in the scmos + dnl directory. + + usingPython3= + if test "$CPP" = "$CC -E" ; then + MCPP="$CPP -x c" + MSED="sed -e 's/\\/\\\\/'" + else + MCPP="$CPP" + MSED="sed -e 's/\\/\\\\/'" + fi + +else + MCPP="\${MAGICDIR}/scripts/preproc.py -ccomm" + MSED="cat" + usingPython3=1 +fi + dnl Check for X enabled/disabled AC_PATH_XTRA @@ -1802,7 +1798,7 @@ AC_SUBST(DEPEND_FLAG) AC_SUBST(SHLIB_CFLAGS) AC_SUBST(LD_RUN_PATH) AC_SUBST(MCPP) -AC_SUBST(SCPP) +AC_SUBST(MSED) AC_SUBST(MAGIC_VERSION) AC_SUBST(MAGIC_REVISION) @@ -1839,6 +1835,19 @@ else echo fi +${ECHO_N} "Python3: " +if test $usingPython3 ; then + echo "yes" +else + echo "no" + echo + echo " Magic installation will use the gcc preprocessor for forming" + echo " the default SCMOS technology files and the macro definitions." + echo " This usually works, but in case of preprocessor failure, you" + echo " may need python3 installed." + echo +fi + ${ECHO_N} "OpenGL: " if test $usingOGL ; then echo "yes" @@ -1851,14 +1860,18 @@ if test $usingOGL ; then else echo "no" echo - echo " OpenGL graphics are considerably better than the standard 8-bit" - echo " and 24-bit X11 graphics, provided that you have a video card and" - echo " driver supporting accelerated OpenGL graphics. If you get this" - echo " message, you may need to download OpenGL libraries and header" - echo " files, which are usually available from the video card manufacturer." - echo " Magic with un-accelerated OpenGL, such as using Mesa GL without" - echo " a supported graphics card, is usually a very bad combination." - echo + if test $usingCairo ; then + echo " Cairo graphics are available so OpenGL is purely optional." + else + echo " OpenGL graphics are considerably better than the standard 8-bit" + echo " and 24-bit X11 graphics, provided that you have a video card and" + echo " driver supporting accelerated OpenGL graphics. If you get this" + echo " message, you may need to download OpenGL libraries and header" + echo " files, which are usually available from the video card manufacturer." + echo " Magic with un-accelerated OpenGL, such as using Mesa GL without" + echo " a supported graphics card, is usually a very bad combination." + echo + fi fi ${ECHO_N} "Cairo: " @@ -1867,12 +1880,18 @@ if test $usingCairo ; then else echo "no" echo - echo " Cairo graphics are considerably better than the standard 8-bit" - echo " and 24-bit X11 graphics, provided that you have a video card and" - echo " driver supporting hardware-accelerated graphics. If you get this" - echo " message, you may need to download Cairo and fontconfig libraries" - echo " and header files, which are usually found in package cairo-devel." - echo + if test $usingOGL ; then + echo " OpenGL graphics are available so Cairo is purely optional" + echo " unless there are issues with the video card driver's" + echo " implementation of OpenGL." + else + echo " Cairo graphics are considerably better than the standard 8-bit" + echo " and 24-bit X11 graphics, provided that you have a video card and" + echo " driver supporting hardware-accelerated graphics. If you get this" + echo " message, you may need to download Cairo and fontconfig libraries" + echo " and header files, which are usually found in package cairo-devel." + echo + fi fi if test $usingTcl ; then diff --git a/scripts/defs.mak.in b/scripts/defs.mak.in index 98f07b37..0404e2ee 100755 --- a/scripts/defs.mak.in +++ b/scripts/defs.mak.in @@ -58,9 +58,8 @@ AR = ar ARFLAGS = crv LINK = ld -r LD = @LD@ -M4 = @M4@ MCPP = @MCPP@ -SCPP = @SCPP@ +MSED = @MSED@ RANLIB = @RANLIB@ SHDLIB_EXT = @SHDLIB_EXT@ LDDL_FLAGS = ${LDFLAGS} @LDDL_FLAGS@ diff --git a/scripts/preproc.py b/scripts/preproc.py index 7a2fc7cf..1fca5bef 100755 --- a/scripts/preproc.py +++ b/scripts/preproc.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 #-------------------------------------------------------------------- # # preproc.py @@ -25,6 +25,7 @@ # #endif # # #define [...] +# #define () [...] # #undef # # #include @@ -146,10 +147,27 @@ def solve_condition(condition, keys, defines, keyrex): else: return 0 +def sortkeys(keys): + newkeys = [] + for i in range(0, len(keys)): + keyword = keys[i] + found = False + for j in range(0, len(newkeys)): + inword = newkeys[j] + if inword in keyword: + # Insert keyword before inword + newkeys.insert(j, keyword) + found = True + break + if not found: + newkeys.append(keyword) + return newkeys + def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): includerex = re.compile('^[ \t]*#include[ \t]+"*([^ \t\n\r"]+)') definerex = re.compile('^[ \t]*#define[ \t]+([^ \t]+)[ \t]+(.+)') + paramrex = re.compile('^([^\(]+)\(([^\)]+)\)') defrex = re.compile('^[ \t]*#define[ \t]+([^ \t\n\r]+)') undefrex = re.compile('^[ \t]*#undef[ \t]+([^ \t\n\r]+)') ifdefrex = re.compile('^[ \t]*#ifdef[ \t]+(.+)') @@ -160,7 +178,8 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): endifrex = re.compile('^[ \t]*#endif') commentrex = re.compile('^###[^#]*$') ccstartrex = re.compile('/\*') # C-style comment start - ccendrex = re.compile('\*/') # C-style comment end + ccendrex = re.compile('\*/') # C-style comment end + contrex = re.compile('.*\\\\$') # Backslash continuation line badifrex = re.compile('^[ \t]*#if[ \t]*.*') badelserex = re.compile('^[ \t]*#else[ \t]*.*') @@ -187,7 +206,7 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): break if not ifile: - print("Error: Cannot open file " + inputfile + " for reading.\n") + print("Error: Cannot open file " + inputfile + " for reading.\n", file=sys.stderr) return ccblock = -1 @@ -196,6 +215,8 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): lineno = 0 filetext = ifile.readlines() + lastline = [] + for line in filetext: lineno += 1 @@ -206,7 +227,7 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): if pmatch: ematch = ccendrex.search(line[pmatch.end(0):]) if ematch: - line = line[0:pmatch.start(0)] + line[ematch.end(0)+2:] + line = line[0:pmatch.start(0)] + line[pmatch.end(0) + ematch.end(0):] else: line = line[0:pmatch.start(0)] ccblock = 1 @@ -218,55 +239,31 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): else: continue + # Handle continuation detected in previous line + if lastline: + # Note: Apparently there is a character retained after the backslash, + # so strip the last two characters from the line. + line = lastline[0:-2] + line + lastline = [] + + # Continuation lines have the next highest priority. However, this + # script will attempt to keep continuation lines in the body of the + # text and only collapse lines where continuation lines occur in + # a preprocessor statement. + + cmatch = contrex.match(line) + # Ignore lines beginning with "###" pmatch = commentrex.match(line) if pmatch: continue - # Handle include. Note that this code does not expect or - # handle 'if' blocks that cross file boundaries. - pmatch = includerex.match(line) - if pmatch: - inclfile = pmatch.group(1) - runpp(keys, keyrex, defines, ccomm, incdirs, inclfile, ofile) - continue - - # Handle define (with value) - pmatch = definerex.match(line) - if pmatch: - condition = pmatch.group(1) - value = pmatch.group(2) - defines[condition] = value - keyrex[condition] = re.compile(condition) - if condition not in keys: - keys.append(condition) - continue - - # Handle define (simple case, no value) - pmatch = defrex.match(line) - if pmatch: - condition = pmatch.group(1) - print("Defrex condition is " + condition) - defines[condition] = '1' - keyrex[condition] = re.compile(condition) - if condition not in keys: - keys.append(condition) - print("Defrex value is " + defines[condition]) - continue - - # Handle undef - pmatch = undefrex.match(line) - if pmatch: - condition = pmatch.group(1) - if condition in keys: - defines.pop(condition) - keyrex.pop(condition) - keys.remove(condition) - continue - # Handle ifdef pmatch = ifdefrex.match(line) if pmatch: + if cmatch: + lastline = line + continue if ifblock != -1: ifstack.append(ifblock) @@ -280,6 +277,9 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): # Handle ifndef pmatch = ifndefrex.match(line) if pmatch: + if cmatch: + lastline = line + continue if ifblock != -1: ifstack.append(ifblock) @@ -294,6 +294,9 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): # Handle if pmatch = ifrex.match(line) if pmatch: + if cmatch: + lastline = line + continue if ifblock != -1: ifstack.append(ifblock) @@ -307,8 +310,11 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): # Handle elseif pmatch = elseifrex.match(line) if pmatch: + if cmatch: + lastline = line + continue if ifblock == -1: - print("Error: #elseif without preceding #if at line " + str(lineno) + ".") + print("Error: #elseif without preceding #if at line " + str(lineno) + ".", file=sys.stderr) ifblock = 0 if ifblock == 1: @@ -321,8 +327,11 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): # Handle else pmatch = elserex.match(line) if pmatch: + if cmatch: + lastline = line + continue if ifblock == -1: - print("Error: #else without preceding #if at line " + str(lineno) + ".") + print("Error: #else without preceding #if at line " + str(lineno) + ".", file=sys.stderr) ifblock = 0 if ifblock == 1: @@ -334,8 +343,11 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): # Handle endif pmatch = endifrex.match(line) if pmatch: + if cmatch: + lastline = line + continue if ifblock == -1: - print("Error: #endif outside of #if block at line " + str(lineno) + " (ignored)") + print("Error: #endif outside of #if block at line " + str(lineno) + " (ignored)", file=sys.stderr) elif ifstack: ifblock = ifstack.pop() else: @@ -345,7 +357,7 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): # Check for 'if' or 'else' that were not properly formed pmatch = badifrex.match(line) if pmatch: - print("Error: Badly formed #if statement at line " + str(lineno) + " (ignored)") + print("Error: Badly formed #if statement at line " + str(lineno) + " (ignored)", file=sys.stderr) if ifblock != -1: ifstack.append(ifblock) @@ -357,7 +369,7 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): pmatch = badelserex.match(line) if pmatch: - print("Error: Badly formed #else statement at line " + str(lineno) + " (ignored)") + print("Error: Badly formed #else statement at line " + str(lineno) + " (ignored)", file=sys.stderr) ifblock = 2 continue @@ -365,15 +377,120 @@ def runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile): if ifblock == 0 or ifblock == 2: continue + # Handle include. Note that this code does not expect or + # handle 'if' blocks that cross file boundaries. + pmatch = includerex.match(line) + if pmatch: + if cmatch: + lastline = line + continue + inclfile = pmatch.group(1) + runpp(keys, keyrex, defines, ccomm, incdirs, inclfile, ofile) + continue + + # Handle define (with value) + pmatch = definerex.match(line) + if pmatch: + if cmatch: + lastline = line + continue + condition = pmatch.group(1) + + # Additional handling of definition w/parameters: #define X(a,b,c) ..." + rmatch = paramrex.match(condition) + if rmatch: + # 'condition' as a key into keyrex only needs to be unique. + # Use the definition word without everything in parentheses + condition = rmatch.group(1) + + # 'pcondition' is the actual search regexp and must capture all + # the parameters individually for substitution + + parameters = rmatch.group(2).split(',') + + # Generate the regexp string to match comma-separate values + # Note that this is based on the cpp preprocessor, which + # apparently allows commas in arguments if surrounded by + # parentheses; e.g., "def(a, b, (c1,c2))". This is NOT + # handled. + + pcondition = condition + '\(' + for param in parameters[0:-1]: + pcondition += '(.*),' + pcondition += '(.*)\)' + + # Generate the substitution string with group substitutions + pvalue = pmatch.group(2) + idx = 1 + for param in parameters: + pvalue = pvalue.replace(param, '\g<' + str(idx) + '>') + idx = idx + 1 + + defines[condition] = pvalue + keyrex[condition] = re.compile(pcondition) + else: + parameters = [] + value = pmatch.group(2) + # Note: Need to check for infinite recursion here, but it's tricky. + defines[condition] = value + keyrex[condition] = re.compile(condition) + + if condition not in keys: + # Parameterized keys go to the front of the list + if parameters: + keys.insert(0, condition) + else: + keys.append(condition) + keys = sortkeys(keys) + continue + + # Handle define (simple case, no value) + pmatch = defrex.match(line) + if pmatch: + if cmatch: + lastline = line + continue + condition = pmatch.group(1) + defines[condition] = '1' + keyrex[condition] = re.compile(condition) + if condition not in keys: + keys.append(condition) + keys = sortkeys(keys) + continue + + # Handle undef + pmatch = undefrex.match(line) + if pmatch: + if cmatch: + lastline = line + continue + condition = pmatch.group(1) + if condition in keys: + defines.pop(condition) + keyrex.pop(condition) + keys.remove(condition) + continue + # Now do definition replacement on what's left (if anything) - for keyword in keys: - line = keyrex[keyword].sub(defines[keyword], line) + # This must be done repeatedly from the top until there are no + # more substitutions to make. + + while True: + origline = line + for keyword in keys: + newline = keyrex[keyword].sub(defines[keyword], line) + if newline != line: + line = newline + break + + if line == origline: + break # Output the line print(line, file=ofile, end='') if ifblock != -1 or ifstack != []: - print("Error: input file ended with an unterminated #if block.") + print("Error: input file ended with an unterminated #if block.", file=sys.stderr) if ifile != sys.stdin: ifile.close() @@ -433,6 +550,7 @@ if __name__ == '__main__': defines[keyword] = value keyrex[keyword] = re.compile(keyword) keys.append(keyword) + keys = sortkeys(keys) else: print('Bad option ' + item + ', options are -help, -ccomm, -D -I\n') sys.exit(1) @@ -446,6 +564,12 @@ if __name__ == '__main__': print("Error: Cannot open file " + output_file + " for writing.") sys.exit(1) + # Sort keys so that if any definition contains another definition, the + # subset word is handled last; otherwise the subset word will get + # substituted, screwing up the definition names in which it occurs. + + keys = sortkeys(keys) + runpp(keys, keyrex, defines, ccomm, incdirs, inputfile, ofile) if ofile != sys.stdout: ofile.close()