diff --git a/VERSION b/VERSION
index 019cb7bc..996d9654 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-8.3.462
+8.3.463
diff --git a/tcltk/toolkit.tcl b/tcltk/toolkit.tcl
index 9062bb91..89388ac8 100644
--- a/tcltk/toolkit.tcl
+++ b/tcltk/toolkit.tcl
@@ -195,16 +195,46 @@ proc magic::generate_layout_add {subname subpins complist library} {
 
     box 0 0 0 0
 
-    # Generate pins
+    # Generate pins.  This routine can be made re-entrant;  if a
+    # cell exists, then its contents are compared to the incoming
+    # netlist contents.  Pins that exist in the netlist but not
+    # the layout are added.  Pins that exist in the layout but not
+    # in the netlist are removed.
+
     if {[llength $subpins] > 0} {
 	set pinlist [split $subpins]
-	set i 0
+
+	# Determine if this cell already has pins.
+	set existpins []
+	for {set i [port first]} {$i > -1} {set i [port $i next]} {
+            lappend existpins [port $i name]
+	}
+	set addpins []
 	foreach pin $pinlist {
+	    if {[lsearch $existpins $pin] == -1} {
+		lappend addpins $pin
+	    }
+	}
+
+	set rmpins []
+	foreach pin $existpins {
+	    if {[lsearch $pinlist $pin] == -1} {
+		lappend rmpins $pin
+	    }
+	}
+
+	set i 0
+	foreach pin $addpins {
 	    # Escape [ and ] in pin name
 	    set pin_esc [string map {\[ \\\[ \] \\\]} $pin]
 	    magic::create_new_pin $pin_esc $i
 	    incr i
 	}
+	foreach pin $rmpins {
+	    set llayer [goto $pin]
+	    select area $llayer
+	    erase label
+	}
     }
 
     # Set initial position for importing cells
@@ -213,6 +243,24 @@ proc magic::generate_layout_add {subname subpins complist library} {
     set posy [expr {round(3 / [cif scale out])}]
     box position ${posx}i ${posy}i
 
+    # Find all instances in the circuit
+    select top cell
+    set compexist [instance list children]
+    set compcells []
+    # Find the matching cell defs
+    foreach comp $compexist {
+	lappend compcells [instance list celldef $comp]
+    }
+
+    # Diagnostic
+    puts stdout "Cells already in the layout of ${subname}:"
+    for {set i 0} {$i < [llength $compexist]} {incr i} {
+	set comp [lindex $compexist $i]
+	set ccell [lindex $compcells $i]
+	puts stdout "${comp} (${ccell})"
+    }
+    flush stdout
+
     # Seed layout with components
     foreach comp $complist {
 	set pinlist {}
@@ -297,12 +345,30 @@ proc magic::generate_layout_add {subname subpins complist library} {
 	    lappend outparts [lindex $param 1]
 	}
 
-	if {[catch {eval [join $outparts]}]} {
-	    # Assume this is not a gencell, and get an instance.
-	    magic::get_and_move_inst $devtype $instname $mult
-	} else {
-	    # Move forward for next gencell
-	    magic::move_forward_by_width $instname
+	set inst_exists false
+	set existidx [lsearch $compexist $instname]
+	if {$existidx > -1} {
+	    set existcell [lindex $compcells $existidx]
+	    if {$devtype == $existcell} {
+		set inst_exists true
+	    } else {
+		# Instance name exists but is the wrong device type.
+		# To do:  Attempt to maintain the same position
+		pushbox
+		select cell $instname
+		delete
+		popbox
+ 	    }
+	}
+
+	if {$inst_exists == false} {
+	    if {[catch {eval [join $outparts]}]} {
+		# Assume this is not a gencell, and get an instance.
+		magic::get_and_move_inst $devtype $instname $mult
+	    } else {
+		# Move forward for next gencell
+		magic::move_forward_by_width $instname
+	    }
 	}
     }
     save $subname
@@ -393,7 +459,8 @@ proc magic::netlist_to_layout {netfile library} {
    set curtop [cellname list self]
 
    foreach subckt $allsubs {
-        puts stdout "Test: pre-generating subcircuit $subckt"
+	# Diagnostic output
+        puts stdout "Pre-generating subcircuit $subckt placeholder"
 	load $subckt -silent
    }
    load $curtop