diff --git a/Deep-Verification-Base.md b/Deep-Verification-Base.md
index 228b6d1..d9a50f4 100644
--- a/Deep-Verification-Base.md
+++ b/Deep-Verification-Base.md
@@ -28,7 +28,7 @@ The basic plan is this:
 
 In contrast to the flat operations provided so far, the new verification base operates in "deep" mode. Hence the name "Deep Verification Base" (DVB).
 
-# Plan for the hierarchical enhancements of the layout engine
+# Hierarchical enhancements of the layout engine
 
 The layout engine is based on the Region, Edges and EdgePairs classes. Currently those are monolithic structures, but after some refactoring they can be used as providers for the hierarchical algorithms.
 
@@ -36,10 +36,8 @@ The layout engine is based on the Region, Edges and EdgePairs classes. Currently
  * The deep collections utilize temporary layouts to store the shapes, edges and edge pairs away from the original layouts. This is required, as some operations will modify or optimize the original shapes and we don't want to destroy the original data. The temporary layouts are kept in the "deep shape store".
  * Operations acting on the new deep collections will utilize a hierarchical processor instead of the flat one. Not all operations will be migrated to hierarchical processing mode initially. Top priority are boolean polygon-vs-polygon and polygon-vs-edge operations as they are required mainly for device recognition.
  * When writing the deep collection data back to the original layout, hierarchy mapping from the temporary store to the original layout's hierarchy has to happen. KLayout already provides several methods to implement this mapping. 
- * Not all operations will be 
-
-Finally, the suggested use model can be 
 
+Finally, the suggested use model could be like this
 ```
 # A sample DRC script using deep mode
 
@@ -83,7 +81,7 @@ A further step involves recombination of the various context-dependent outputs o
 
 This is a brief description of the idea.
 
-## Schematic extraction tool
+# Schematic extraction tool
 
 Having a hierarchical processing engine allows generating hierarchical device recognition markers.