From 86a91539bbf50a54805d5cee3805f321d7ca1498 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Matthias=20K=C3=B6fferlein?= <matthias@koefferlein.de>
Date: Sun, 11 Nov 2018 22:42:32 +0100
Subject: [PATCH] Updated Deep Verification Base (markdown)

---
 Deep-Verification-Base.md | 62 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/Deep-Verification-Base.md b/Deep-Verification-Base.md
index 38a5587..afaa748 100644
--- a/Deep-Verification-Base.md
+++ b/Deep-Verification-Base.md
@@ -97,11 +97,73 @@ Connectivity layers are either taken from their original layers or derived using
 
 After device recognition, schematic extraction can proceed bottom-up to connect shape by shape and form growing clusters of connected shapes. The incremental nature of the connection extraction forms sub-circuits for each cell. When moving up in the hierarchy, nets from these sub-circuits are connected with nets either from the parent cell or with nets from sibling cells. The result is a hierarchical netlist.
 
+Here is a rough idea for a schematic extraction script:
 
+```(ruby)
+# device definitions
 
+class MOSDevice < DeviceExtractor
 
+  def extract(layout, seed, body)
 
+    body.size == 1 || raise("MOS device requires exactly one body layer")
 
+    sd = body[0]
+    sd.size == 2 || raise("Exactly two body shapes (S,D) are required for MOS devices")
 
+    sides = seed.edges * sd.edges
+    width = sides.length * 0.5 * layout.dbu
 
+    faces = seed.edges - sd.edges
+    length = faces.length * 0.5 * layout.dbu
 
+    params = { "W" => width, "L" => length }
+
+    ports = [
+      Port::new(SEED, "G", seed), 
+      Port::new(BODY1, "S", sd[0]), 
+      Port::new(BODY1, "D", sd[1])
+    ]
+
+    return Device::new(self.DEVICE_NAME, params, ports)
+
+  end
+
+end
+
+class NMOSDevice < MOSDevice
+  self.DEVICE_NAME = "NMOS"
+end
+
+class PMOSDevice < MOSDevice
+  self.DEVICE_NAME = "PMOS"
+end
+
+# body
+
+deep
+
+# generation rules
+sd = active - poly
+gate = active * poly
+pmos = gate * nwell
+nmos = gate - nwell
+
+# net extraction
+extract_nets do
+
+  connect metal2, via1
+  connect via1, metal1
+  connect metal1, contact
+  connect contact, sd
+  connect contact, poly
+  connect contact, gate
+
+  label metal1, metal1_texts
+  label metal2, metal2_texts
+
+  device NMOSDevice, nmos, sd
+  device PMOSDevice, pmos, sd
+
+end
+```
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