From 818ef2ca521bcd320d2a87f6ad34d61eea0a9de3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Matthias=20K=C3=B6fferlein?= <matthias@koefferlein.de>
Date: Tue, 8 Jan 2019 21:01:36 +0100
Subject: [PATCH] Updated 2019 01 07 (markdown)

---
 2019-01-07.md | 58 ++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 55 insertions(+), 3 deletions(-)

diff --git a/2019-01-07.md b/2019-01-07.md
index ae5a5f1..063a97f 100644
--- a/2019-01-07.md
+++ b/2019-01-07.md
@@ -128,8 +128,8 @@ Here is code for such an extraction. It also recognizes tie-down diodes for subs
 included in the net extraction like a conductive layer.
 
 ```ruby
- ly = RBA::Layout::new
-ly.read(File.join($ut_testsrc, "testdata", "algo", "device_extract_l3.gds"))
+ly = RBA::Layout::new
+ly.read(File.join("testdata", "algo", "device_extract_l3.gds"))
 
 l2n = RBA::LayoutToNetlist::new(RBA::RecursiveShapeIterator::new(ly, ly.top_cell, []))
 
@@ -206,4 +206,56 @@ l2n.connect_global(rbulk, "BULK")
 l2n.extract_netlist
 
 puts l2n.netlist.to_s
-```
\ No newline at end of file
+```
+
+The output of this script is:
+
+```
+Circuit RINGO ():
+  XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)
+  XINV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)
+  XINV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)
+  XINV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)
+  XINV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)
+Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
+  XINV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
+  XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
+Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
+  DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
+  DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
+  DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
+  DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
+  XTRANS $1 ($1=$3,$2=VSS,$3=IN)
+  XTRANS $2 ($1=$3,$2=VDD,$3=IN)
+  XTRANS $3 ($1=VDD,$2=OUT,$3=$3)
+  XTRANS $4 ($1=VSS,$2=OUT,$3=$3)
+Circuit TRANS ($1=$1,$2=$2,$3=$3):
+```
+
+With some additional steps, the netlist can be simplified and top-level pins are added:
+
+```ruby
+l2n.netlist.purge
+l2n.netlist.make_top_level_pins
+
+puts l2n.netlist.to_s
+```
+
+This cleaned netlist lacks the empty "TRANS" subcircuits which are left over from transistor cells - they are propagated because the n-Well layer differentiates them into PMOS and NMOS transistors. The cleaned netlist looks like this:
+
+```
+Circuit RINGO (FB=FB,VDD=VDD,'BULK,VSS'='BULK,VSS'):
+  XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=(null),$7=VDD)
+  XINV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)
+  XINV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)
+  XINV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)
+  XINV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)
+Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
+  XINV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
+  XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
+Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
+  DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
+  DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
+  DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
+  DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
+```