#%lvsdb-klayout

# Layout
layout(
 top(RINGO)
 unit(0.001)

 # Layer section
 # This section lists the mask layers (drawing or derived) and their connections.

 # Mask layers
 layer(l3 '1/0')
 layer(l4 '5/0')
 layer(l8 '8/0')
 layer(l11 '9/0')
 layer(l12 '10/0')
 layer(l13 '11/0')
 layer(l7 '13/0')
 layer(l2)
 layer(l9)
 layer(l6)
 layer(l10)

 # Mask layer connectivity
 connect(l3 l3 l9)
 connect(l4 l4 l8)
 connect(l8 l4 l8 l11 l2 l9 l6 l10)
 connect(l11 l8 l11 l12)
 connect(l12 l11 l12 l13)
 connect(l13 l12 l13)
 connect(l2 l8 l2)
 connect(l9 l3 l8 l9)
 connect(l6 l8 l6)
 connect(l10 l8 l10)

 # Global nets and connectivity
 global(l7 SUBSTRATE)
 global(l10 SUBSTRATE)

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(ND2X1

  # Circuit boundary
  rect((-100 250) (2600 7750))

  # Outgoing pins and their connections to nets
  pin(name(VDD))
  pin(name(OUT))
  pin(name(VSS))
  pin()
  pin(name(B))
  pin(name(A))
  pin(name(BULK))

 )
 circuit(INVX1

  # Circuit boundary
  rect((-100 250) (2000 7750))

  # Outgoing pins and their connections to nets
  pin(name(VDD))
  pin(name(OUT))
  pin(name(VSS))
  pin()
  pin(name(IN))
  pin(name(BULK))

 )
 circuit(INVX2

  # Circuit boundary
  rect((-100 250) (2600 7750))

  # Outgoing pins and their connections to nets
  pin(name(IN))
  pin(name(VDD))
  pin(name(OUT))
  pin(name(VSS))
  pin()
  pin(name(BULK))

 )
 circuit(RINGO

  # Circuit boundary
  rect((600 250) (25800 7750))

  # Nets with their geometries
  net(1
   rect(l11 (4040 2950) (610 300))
  )
  net(2
   rect(l11 (5550 2950) (900 300))
  )
  net(3
   rect(l11 (18150 2950) (900 300))
  )
  net(4
   rect(l11 (19950 2950) (900 300))
  )
  net(5 name(FB)
   rect(l11 (21750 2950) (900 300))
   rect(l11 (-19530 590) (320 320))
   rect(l11 (17820 -320) (320 320))
   rect(l12 (-18400 -260) (200 200))
   rect(l12 (17940 -200) (200 200))
   rect(l13 (-18040 -300) (17740 400))
   rect(l13 (-17920 -200) (0 0))
   rect(l13 (-220 -200) (400 400))
   rect(l13 (17740 -400) (400 400))
  )
  net(6 name(VDD)
   rect(l3 (1100 4500) (1400 3500))
   rect(l3 (-1900 -3500) (600 3500))
   rect(l3 (23300 -3500) (1400 3500))
   rect(l3 (-100 -3500) (600 3500))
   rect(l8 (-24690 -1240) (180 180))
   rect(l8 (-180 370) (180 180))
   rect(l8 (-180 -1280) (180 180))
   rect(l8 (23220 370) (180 180))
   rect(l8 (-180 370) (180 180))
   rect(l8 (-180 -1280) (180 180))
   rect(l11 (-22340 860) (0 0))
   rect(l11 (-1750 -450) (1200 800))
   rect(l11 (-750 -1450) (300 1400))
   rect(l11 (-100 -350) (0 0))
   rect(l11 (-1250 -400) (600 800))
   rect(l11 (23400 -800) (1200 800))
   rect(l11 (-750 -1450) (300 1400))
   rect(l11 (-100 -350) (0 0))
   rect(l11 (550 -400) (600 800))
   rect(l9 (-24850 -1500) (500 1500))
   rect(l9 (22900 -1500) (500 1500))
  )
  net(7 name(OUT)
   rect(l11 (23440 3840) (320 320))
   rect(l12 (-260 -260) (200 200))
   rect(l13 (-100 -100) (0 0))
   rect(l13 (-200 -200) (400 400))
  )
  net(8 name(ENABLE)
   rect(l11 (2440 2940) (320 320))
   rect(l12 (-260 -260) (200 200))
   rect(l13 (-100 -100) (0 0))
   rect(l13 (-200 -200) (400 400))
  )
  net(9 name(VSS)
   rect(l8 (1710 1610) (180 180))
   rect(l8 (-180 -1280) (180 180))
   rect(l8 (-180 370) (180 180))
   rect(l8 (23220 370) (180 180))
   rect(l8 (-180 -1280) (180 180))
   rect(l8 (-180 370) (180 180))
   rect(l11 (-22340 -390) (0 0))
   rect(l11 (-1300 -400) (300 1400))
   rect(l11 (-750 -1450) (1200 800))
   rect(l11 (-550 -400) (0 0))
   rect(l11 (-1250 -400) (600 800))
   rect(l11 (23850 -750) (300 1400))
   rect(l11 (-750 -1450) (1200 800))
   rect(l11 (-550 -400) (0 0))
   rect(l11 (550 -400) (600 800))
   rect(l10 (-24850 -800) (500 1500))
   rect(l10 (22900 -1500) (500 1500))
  )
  net(10
   rect(l11 (7350 2950) (900 300))
  )
  net(11
   rect(l11 (16350 2950) (900 300))
  )
  net(12
   rect(l11 (9150 2950) (900 300))
  )
  net(13
   rect(l11 (10950 2950) (900 300))
  )
  net(14
   rect(l11 (12750 2950) (900 300))
  )
  net(15
   rect(l11 (14550 2950) (900 300))
  )

  # Outgoing pins and their connections to nets
  pin(5 name(FB))
  pin(6 name(VDD))
  pin(7 name(OUT))
  pin(8 name(ENABLE))
  pin(9 name(VSS))

  # Subcircuits and their connections
  circuit(1 ND2X1 location(1800 0)
   pin(0 6)
   pin(1 1)
   pin(2 9)
   pin(3 6)
   pin(4 5)
   pin(5 8)
   pin(6 9)
  )
  circuit(2 INVX1 location(4200 0)
   pin(0 6)
   pin(1 2)
   pin(2 9)
   pin(3 6)
   pin(4 1)
   pin(5 9)
  )
  circuit(3 INVX1 location(6000 0)
   pin(0 6)
   pin(1 10)
   pin(2 9)
   pin(3 6)
   pin(4 2)
   pin(5 9)
  )
  circuit(4 INVX1 location(16800 0)
   pin(0 6)
   pin(1 3)
   pin(2 9)
   pin(3 6)
   pin(4 11)
   pin(5 9)
  )
  circuit(5 INVX1 location(18600 0)
   pin(0 6)
   pin(1 4)
   pin(2 9)
   pin(3 6)
   pin(4 3)
   pin(5 9)
  )
  circuit(6 INVX1 location(20400 0)
   pin(0 6)
   pin(1 5)
   pin(2 9)
   pin(3 6)
   pin(4 4)
   pin(5 9)
  )
  circuit(7 INVX2 location(22200 0)
   pin(0 5)
   pin(1 6)
   pin(2 7)
   pin(3 9)
   pin(4 6)
   pin(5 9)
  )
  circuit(17 INVX1 location(7800 0)
   pin(0 6)
   pin(1 12)
   pin(2 9)
   pin(3 6)
   pin(4 10)
   pin(5 9)
  )
  circuit(18 INVX1 location(9600 0)
   pin(0 6)
   pin(1 13)
   pin(2 9)
   pin(3 6)
   pin(4 12)
   pin(5 9)
  )
  circuit(19 INVX1 location(11400 0)
   pin(0 6)
   pin(1 14)
   pin(2 9)
   pin(3 6)
   pin(4 13)
   pin(5 9)
  )
  circuit(20 INVX1 location(13200 0)
   pin(0 6)
   pin(1 15)
   pin(2 9)
   pin(3 6)
   pin(4 14)
   pin(5 9)
  )
  circuit(21 INVX1 location(15000 0)
   pin(0 6)
   pin(1 11)
   pin(2 9)
   pin(3 6)
   pin(4 15)
   pin(5 9)
  )

 )
)

# Reference netlist
reference(

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(ND2X1

  # Outgoing pins and their connections to nets
  pin(name(VDD))
  pin(name(OUT))
  pin(name(VSS))
  pin(name(NWELL))
  pin(name(B))
  pin(name(A))
  pin(name(BULK))

 )
 circuit(INVX1

  # Outgoing pins and their connections to nets
  pin(name(VDD))
  pin(name(OUT))
  pin(name(VSS))
  pin(name(NWELL))
  pin(name(IN))
  pin(name(BULK))

 )
 circuit(INVX2

  # Outgoing pins and their connections to nets
  pin(name(VDD))
  pin(name(OUT))
  pin(name(VSS))
  pin(name(NWELL))
  pin(name(IN))
  pin(name(BULK))

 )
 circuit(RINGO

  # Nets
  net(1 name(VSS))
  net(2 name(VDD))
  net(3 name(FB))
  net(4 name(ENABLE))
  net(5 name(OUT))
  net(6 name('1'))
  net(7 name('2'))
  net(8 name('3'))
  net(9 name('4'))
  net(10 name('5'))
  net(11 name('6'))
  net(12 name('7'))
  net(13 name('8'))
  net(14 name('9'))
  net(15 name('10'))

  # Outgoing pins and their connections to nets
  pin(1 name(VSS))
  pin(2 name(VDD))
  pin(3 name(FB))
  pin(4 name(ENABLE))
  pin(5 name(OUT))

  # Subcircuits and their connections
  circuit(1 ND2X1 name($1)
   pin(0 2)
   pin(1 6)
   pin(2 1)
   pin(3 2)
   pin(4 3)
   pin(5 4)
   pin(6 1)
  )
  circuit(2 INVX1 name($2)
   pin(0 2)
   pin(1 7)
   pin(2 1)
   pin(3 2)
   pin(4 6)
   pin(5 1)
  )
  circuit(3 INVX1 name($3)
   pin(0 2)
   pin(1 8)
   pin(2 1)
   pin(3 2)
   pin(4 7)
   pin(5 1)
  )
  circuit(4 INVX1 name($4)
   pin(0 2)
   pin(1 9)
   pin(2 1)
   pin(3 2)
   pin(4 8)
   pin(5 1)
  )
  circuit(5 INVX1 name($5)
   pin(0 2)
   pin(1 10)
   pin(2 1)
   pin(3 2)
   pin(4 9)
   pin(5 1)
  )
  circuit(6 INVX1 name($6)
   pin(0 2)
   pin(1 11)
   pin(2 1)
   pin(3 2)
   pin(4 10)
   pin(5 1)
  )
  circuit(7 INVX1 name($7)
   pin(0 2)
   pin(1 12)
   pin(2 1)
   pin(3 2)
   pin(4 11)
   pin(5 1)
  )
  circuit(8 INVX1 name($8)
   pin(0 2)
   pin(1 13)
   pin(2 1)
   pin(3 2)
   pin(4 12)
   pin(5 1)
  )
  circuit(9 INVX1 name($9)
   pin(0 2)
   pin(1 14)
   pin(2 1)
   pin(3 2)
   pin(4 13)
   pin(5 1)
  )
  circuit(10 INVX1 name($10)
   pin(0 2)
   pin(1 15)
   pin(2 1)
   pin(3 2)
   pin(4 14)
   pin(5 1)
  )
  circuit(11 INVX1 name($11)
   pin(0 2)
   pin(1 3)
   pin(2 1)
   pin(3 2)
   pin(4 15)
   pin(5 1)
  )
  circuit(12 INVX2 name($12)
   pin(0 2)
   pin(1 5)
   pin(2 1)
   pin(3 2)
   pin(4 3)
   pin(5 1)
  )

 )
)

# Cross reference
xref(
 circuit(INVX1 INVX1 match
  xref(
   pin(3 3 match)
   pin(5 5 match)
   pin(4 4 match)
   pin(1 1 match)
   pin(0 0 match)
   pin(2 2 match)
  )
 )
 circuit(INVX2 INVX2 match
  xref(
   pin(4 3 match)
   pin(5 5 match)
   pin(0 4 match)
   pin(2 1 match)
   pin(1 0 match)
   pin(3 2 match)
  )
 )
 circuit(ND2X1 ND2X1 match
  xref(
   pin(3 3 match)
   pin(5 5 match)
   pin(4 4 match)
   pin(6 6 match)
   pin(1 1 match)
   pin(0 0 match)
   pin(2 2 match)
  )
 )
 circuit(RINGO RINGO match
  xref(
   net(1 6 match)
   net(4 15 match)
   net(2 7 match)
   net(10 8 match)
   net(12 9 match)
   net(13 10 match)
   net(14 11 match)
   net(15 12 match)
   net(11 13 match)
   net(3 14 match)
   net(8 4 match)
   net(5 3 match)
   net(7 5 match)
   net(6 2 match)
   net(9 1 match)
   pin(3 3 match)
   pin(0 2 match)
   pin(2 4 match)
   pin(1 1 match)
   pin(4 0 match)
   circuit(2 2 match)
   circuit(3 3 match)
   circuit(17 4 match)
   circuit(18 5 match)
   circuit(19 6 match)
   circuit(20 7 match)
   circuit(21 8 match)
   circuit(4 9 match)
   circuit(5 10 match)
   circuit(6 11 match)
   circuit(7 12 match)
   circuit(1 1 match)
  )
 )
)