source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

schematic("resistor.cir")

deep

contact     = input(15, 0)
metal1      = input(16, 0)  
metal1_ver  = input(16, 5)
metal1_lbl  = labels(16, 3) 
res = metal1 & metal1_ver
metal1_not_res = metal1 - metal1_ver

dc = extract_devices(resistor("RR1", 1),  { "R" => res , "C" => metal1_not_res})
dc.enable_parameter("W", true)
dc.enable_parameter("L", true)
sp = dc.spice_profile("")
sp.outgoing_parameters = {
  "R" => "",  # drop
  "W" => "W",
  "L" => "L",
  "$" => "R"  # direct value
}
dc.set_spice_profile("", sp)

connect(contact, metal1_not_res)
connect(metal1_not_res, metal1_lbl)

align
netlist.make_top_level_pins(false)
netlist.simplify
compare