source($lvs_test_source)

report_lvs($lvs_test_target_lvsdb)

writer = write_spice(true, false)
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")

schematic("invchain_for_cheat.cir")

deep

# Drawing layers

nwell       = input(1, 0)
active      = input(2, 0)
poly        = input(3, 0)
diff_cont   = input(4, 0)
poly_cont   = input(5, 0)
metal1      = input(6, 0)
via1        = input(7, 0)
metal2      = input(8, 0)

# Bulk layer for terminal provisioning

bulk        = polygon_layer

# Computed layers

active_in_nwell       = active & nwell
pactive               = active_in_nwell 
pgate                 = pactive & poly
psd                   = pactive - pgate

active_outside_nwell  = active - nwell
nactive               = active_outside_nwell 
ngate                 = nactive & poly
nsd                   = nactive - ngate

# Device extraction

cheat("INV") do

  # PMOS transistor device extraction
  extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate, 
                                  "tS" => psd, "tD" => psd, "tG" => poly })

  # NMOS transistor device extraction
  extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate, 
                                  "tS" => nsd, "tD" => nsd, "tG" => poly })

end

# Define connectivity for netlist extraction

# Inter-layer
connect(psd,        diff_cont)
connect(nsd,        diff_cont)
connect(poly,       poly_cont)
connect(diff_cont,  metal1)
connect(poly_cont,  metal1)
connect(metal1,     via1)
connect(via1,       metal2)

# Global
connect_global(bulk, "SUBSTRATE")

# Compare section

netlist.simplify

compare