source($lvs_test_source, "NAND2_WITH_DIODES") report_lvs($lvs_test_target_lvsdb, true) target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") schematic("nand2_split_gate_schematic.cir") join_symmetric_nets("*") deep # Reports generated # Drawing layers nwell = input(1, 0) active = input(2, 0) pplus = input(3, 0) nplus = input(4, 0) poly = input(5, 0) contact = input(6, 0) metal1 = input(7, 0) metal1_lbl = labels(7, 1) via1 = input(8, 0) metal2 = input(9, 0) metal2_lbl = labels(9, 1) # Bulk layer for terminal provisioning bulk = polygon_layer # Computed layers active_in_nwell = active & nwell pactive = active_in_nwell & pplus pgate = pactive & poly psd = pactive - pgate ntie = active_in_nwell & nplus active_outside_nwell = active - nwell nactive = active_outside_nwell & nplus ngate = nactive & poly nsd = nactive - ngate ptie = active_outside_nwell & pplus # Device extraction # PMOS transistor device extraction extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) # NMOS transistor device extraction extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) # Define connectivity for netlist extraction # Inter-layer connect(psd, contact) connect(nsd, contact) connect(poly, contact) connect(ntie, contact) connect(nwell, ntie) connect(ptie, contact) connect(contact, metal1) connect(metal1, metal1_lbl) # attaches labels connect(metal1, via1) connect(via1, metal2) connect(metal2, metal2_lbl) # attaches labels # Global connect_global(bulk, "SUBSTRATE") connect_global(ptie, "SUBSTRATE") # Extract, simplify netlist netlist.simplify # Compare section compare