#%lvsdb-klayout

# Layout
layout(
 top(ND2X1)
 unit(0.001)

 # Layer section
 # This section lists the mask layers (drawing or derived) and their connections.

 # Mask layers
 layer(l3 '1/0')
 layer(l4 '5/0')
 layer(l8 '8/0')
 layer(l11 '9/0')
 layer(l12)
 layer(l13)
 layer(l7)
 layer(l2)
 layer(l9)
 layer(l6)
 layer(l10)

 # Mask layer connectivity
 connect(l3 l3 l9)
 connect(l4 l4 l8)
 connect(l8 l4 l8 l11 l2 l9 l6 l10)
 connect(l11 l8 l11 l12)
 connect(l12 l11 l12 l13)
 connect(l13 l12 l13)
 connect(l7 l7)
 connect(l2 l8 l2)
 connect(l9 l3 l8 l9)
 connect(l6 l8 l6)
 connect(l10 l8 l10)

 # Global nets and connectivity
 global(l7 SUBSTRATE)
 global(l10 SUBSTRATE)

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Device abstracts section
 # Device abstracts list the pin shapes of the devices.
 device(D$PMOS PMOS
  terminal(S
   rect(l2 (-550 -750) (425 1500))
  )
  terminal(G
   rect(l4 (-125 -750) (250 1500))
  )
  terminal(D
   rect(l2 (125 -750) (450 1500))
  )
  terminal(B
   rect(l3 (-125 -750) (250 1500))
  )
 )
 device(D$PMOS$1 PMOS
  terminal(S
   rect(l2 (-575 -750) (450 1500))
  )
  terminal(G
   rect(l4 (-125 -750) (250 1500))
  )
  terminal(D
   rect(l2 (125 -750) (425 1500))
  )
  terminal(B
   rect(l3 (-125 -750) (250 1500))
  )
 )
 device(D$NMOS NMOS
  terminal(S
   rect(l6 (-550 -475) (425 950))
  )
  terminal(G
   rect(l4 (-125 -475) (250 950))
  )
  terminal(D
   rect(l6 (125 -475) (450 950))
  )
  terminal(B
   rect(l7 (-125 -475) (250 950))
  )
 )
 device(D$NMOS$1 NMOS
  terminal(S
   rect(l6 (-575 -475) (450 950))
  )
  terminal(G
   rect(l4 (-125 -475) (250 950))
  )
  terminal(D
   rect(l6 (125 -475) (425 950))
  )
  terminal(B
   rect(l7 (-125 -475) (250 950))
  )
 )

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(ND2X1

  # Circuit boundary
  rect((-100 400) (2600 7600))

  # Nets with their geometries
  net(1 name(VSS)
   rect(l8 (1110 5160) (180 180))
   rect(l8 (-180 920) (180 180))
   rect(l8 (-180 -730) (180 180))
   rect(l11 (-240 -790) (300 1700))
   rect(l11 (-1350 0) (2400 800))
   rect(l11 (-1150 -400) (0 0))
   rect(l2 (-275 -2150) (425 1500))
   rect(l2 (-400 -1500) (425 1500))
  )
  net(2
   rect(l8 (1810 1770) (180 180))
   rect(l8 (-180 370) (180 180))
   rect(l8 (-1580 3760) (180 180))
   rect(l8 (-180 -730) (180 180))
   rect(l8 (-180 -730) (180 180))
   rect(l8 (1220 920) (180 180))
   rect(l8 (-180 -1280) (180 180))
   rect(l8 (-180 370) (180 180))
   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
   rect(l11 (-110 1390) (300 1400))
   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
   rect(l11 (-1890 600) (300 1400))
   rect(l11 (1100 -1700) (300 300))
   rect(l11 (-300 0) (300 1400))
   rect(l2 (-1750 -1450) (425 1500))
   rect(l2 (950 -1500) (425 1500))
   rect(l6 (-425 -4890) (425 950))
  )
  net(3 name(VDD)
   rect(l8 (410 1770) (180 180))
   rect(l8 (-180 370) (180 180))
   rect(l11 (-240 -1300) (300 1360))
   rect(l11 (-650 -2160) (2400 800))
   rect(l11 (-1150 -400) (0 0))
   rect(l6 (-950 860) (425 950))
  )
  net(4
   rect(l3 (-100 4500) (2600 3500))
  )
  net(5 name(b)
   rect(l4 (1425 2860) (250 1940))
   rect(l4 (-345 -950) (300 300))
   rect(l4 (-205 650) (250 2000))
   rect(l4 (-250 -2000) (250 2000))
   rect(l4 (-250 -5390) (250 1450))
   rect(l8 (-285 1050) (180 180))
   rect(l11 (-70 -90) (0 0))
   rect(l11 (-170 -150) (300 300))
  )
  net(6 name(X)
   rect(l4 (725 2860) (250 1940))
   rect(l4 (-325 -1850) (300 300))
   rect(l4 (-225 1550) (250 2000))
   rect(l4 (-250 -2000) (250 2000))
   rect(l4 (-250 -5390) (250 1450))
   rect(l8 (-265 150) (180 180))
   rect(l11 (-90 -90) (0 0))
   rect(l11 (-150 -150) (300 300))
  )
  net(7 name(SUBSTRATE))
  net(8 name($I3)
   rect(l6 (975 1660) (425 950))
   rect(l6 (-400 -950) (425 950))
  )

  # Outgoing pins and their connections to nets
  pin(1 name(VSS))
  pin(3 name(VDD))
  pin(5 name(b))
  pin(6 name(X))
  pin(7 name(SUBSTRATE))

  # Devices and their connections
  device(1 D$PMOS
   location(850 5800)
   param(L 0.25)
   param(W 1.5)
   param(AS 0.6375)
   param(AD 0.3375)
   param(PS 3.85)
   param(PD 1.95)
   terminal(S 2)
   terminal(G 6)
   terminal(D 1)
   terminal(B 4)
  )
  device(2 D$PMOS$1
   location(1550 5800)
   param(L 0.25)
   param(W 1.5)
   param(AS 0.3375)
   param(AD 0.6375)
   param(PS 1.95)
   param(PD 3.85)
   terminal(S 1)
   terminal(G 5)
   terminal(D 2)
   terminal(B 4)
  )
  device(3 D$NMOS
   location(850 2135)
   param(L 0.25)
   param(W 0.95)
   param(AS 0.40375)
   param(AD 0.21375)
   param(PS 2.75)
   param(PD 1.4)
   terminal(S 3)
   terminal(G 6)
   terminal(D 8)
   terminal(B 7)
  )
  device(4 D$NMOS$1
   location(1550 2135)
   param(L 0.25)
   param(W 0.95)
   param(AS 0.21375)
   param(AD 0.40375)
   param(PS 1.4)
   param(PD 2.75)
   terminal(S 8)
   terminal(G 5)
   terminal(D 2)
   terminal(B 7)
  )

 )
)

# Reference netlist
reference(

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(ND2X1

  # Nets
  net(1 name(VDD))
  net(2 name(OUT))
  net(3 name(VSS))
  net(4 name(NWELL))
  net(5 name(B))
  net(6 name(A))
  net(7 name(BULK))
  net(8 name('1'))

  # Outgoing pins and their connections to nets
  pin(1 name(VDD))
  pin(2 name(OUT))
  pin(3 name(VSS))
  pin(4 name(NWELL))
  pin(5 name(B))
  pin(6 name(A))
  pin(7 name(BULK))

  # Devices and their connections
  device(1 PMOS
   name($1)
   param(L 0.25)
   param(W 1.5)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 1)
   terminal(G 6)
   terminal(D 2)
   terminal(B 4)
  )
  device(2 PMOS
   name($2)
   param(L 0.25)
   param(W 1.5)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 1)
   terminal(G 5)
   terminal(D 2)
   terminal(B 4)
  )
  device(3 NMOS
   name($3)
   param(L 0.25)
   param(W 0.95)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 3)
   terminal(G 6)
   terminal(D 8)
   terminal(B 7)
  )
  device(4 NMOS
   name($4)
   param(L 0.25)
   param(W 0.95)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 8)
   terminal(G 5)
   terminal(D 2)
   terminal(B 7)
  )

 )
)

# Cross reference
xref(
 circuit(ND2X1 ND2X1 match
  log(
   entry(error description('Port mismatch \'$4\' vs. \'NWELL\''))
   entry(error description('Port mismatch \'$2\' vs. \'OUT\''))
   entry(error description('Port mismatch \'SUBSTRATE\' vs. \'BULK\''))
   entry(error description('Port mismatch \'VDD\' vs. \'VSS\''))
   entry(error description('Port mismatch \'VSS\' vs. \'VDD\''))
   entry(error description('Port mismatch \'X\' vs. \'A\''))
  )
  xref(
   net(8 8 match)
   net(4 4 match)
   net(2 2 match)
   net(7 7 match)
   net(3 3 match)
   net(1 1 match)
   net(6 6 match)
   net(5 5 match)
   pin(() 3 match)
   pin(() 1 match)
   pin(4 6 match)
   pin(1 2 match)
   pin(0 0 match)
   pin(3 5 match)
   pin(2 4 match)
   device(3 3 match)
   device(4 4 match)
   device(1 1 match)
   device(2 2 match)
  )
 )
)