diff --git a/src/db/unit_tests/dbNetlistCompareTests.cc b/src/db/unit_tests/dbNetlistCompareTests.cc
index 32d9b07d6..fb4613b62 100644
--- a/src/db/unit_tests/dbNetlistCompareTests.cc
+++ b/src/db/unit_tests/dbNetlistCompareTests.cc
@@ -1986,8 +1986,7 @@ TEST(14_Subcircuit2NandMismatchNoSwap)
     "match_pins $4 $4\n"
     "pin_mismatch (null) $0\n"
     "match_subcircuits $2 $1\n"
-    "subcircuit_mismatch (null) $2\n"
-    "subcircuit_mismatch $1 (null)\n"
+    "subcircuit_mismatch $1 $2\n"
     "end_circuit TOP TOP NOMATCH"
   );
 
@@ -2058,17 +2057,14 @@ TEST(14_Subcircuit2NandMismatchNoSwap)
     "  subcircuit_pin $2[$2]:$1[$2]\n"
     " net VDD:VDD [Mismatch]\n"
     "  pin $3:$3\n"
-    "  subcircuit_pin (null):$2[$3]\n"
-    "  subcircuit_pin $1[$3]:(null)\n"
+    "  subcircuit_pin $1[$3]:$2[$3]\n"
     "  subcircuit_pin $2[$3]:$1[$3]\n"
     " net VSS:VSS [Mismatch]\n"
     "  pin $4:$4\n"
-    "  subcircuit_pin (null):$2[$4]\n"
-    "  subcircuit_pin $1[$4]:(null)\n"
+    "  subcircuit_pin $1[$4]:$2[$4]\n"
     "  subcircuit_pin $2[$4]:$1[$4]\n"
-    " subcircuit (null):$2 [Mismatch]\n"
-    " subcircuit $1:(null) [Mismatch]\n"
     " subcircuit $2:$1 [Match]\n"
+    " subcircuit $1:$2 [Mismatch]\n"
   );
   EXPECT_EQ (good, false);
 }
diff --git a/src/db/unit_tests/dbNetlistReaderTests.cc b/src/db/unit_tests/dbNetlistReaderTests.cc
index bc7c1f262..4817ebc37 100644
--- a/src/db/unit_tests/dbNetlistReaderTests.cc
+++ b/src/db/unit_tests/dbNetlistReaderTests.cc
@@ -164,12 +164,12 @@ TEST(5_CircuitParameters)
   reader.read (is, nl);
 
   EXPECT_EQ (nl.to_string (),
-    "circuit SUBCKT ($1=$1,$2=A,$3='V42(%)',$4=Z,$5=gnd,$6=gnd$1);\n"
+    "circuit SUBCKT ($1=$1,$2=A,$3='V42(%)',$4=Z,$5=GND,$6=GND$1);\n"
     "  subcircuit HVPMOS D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n"
     "  subcircuit HVPMOS D_$2 ($1='V42(%)',$2=A,$3=$3,$4=$1);\n"
-    "  subcircuit HVNMOS D_$3 ($1=gnd,$2=$3,$3=gnd,$4=gnd$1);\n"
-    "  subcircuit HVNMOS D_$4 ($1=gnd,$2=$3,$3=Z,$4=gnd$1);\n"
-    "  subcircuit HVNMOS D_$5 ($1=gnd,$2=A,$3=$3,$4=gnd$1);\n"
+    "  subcircuit HVNMOS D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n"
+    "  subcircuit HVNMOS D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n"
+    "  subcircuit HVNMOS D_$5 ($1=GND,$2=A,$3=$3,$4=GND$1);\n"
     "end;\n"
     "circuit HVPMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n"
     "end;\n"
@@ -242,12 +242,12 @@ TEST(6_ReaderWithDelegate)
   reader.read (is, nl);
 
   EXPECT_EQ (nl.to_string (),
-    "circuit SUBCKT ($1=$1,$2=A,$3=VDD,$4=Z,$5=gnd,$6=gnd$1);\n"
+    "circuit SUBCKT ($1=$1,$2=A,$3=VDD,$4=Z,$5=GND,$6=GND$1);\n"
     "  device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n"
     "  device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n"
-    "  device HVNMOS $3 (S=gnd,G=$3,D=gnd,B=gnd$1) (L=1.695,W=3.18,AS=0,AD=0,PS=9,PD=9);\n"
-    "  device HVNMOS $4 (S=gnd,G=$3,D=Z,B=gnd$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=1.74,PD=1.74);\n"
-    "  device HVNMOS $5 (S=gnd,G=A,D=$3,B=gnd$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);\n"
+    "  device HVNMOS $3 (S=GND,G=$3,D=GND,B=GND$1) (L=1.695,W=3.18,AS=0,AD=0,PS=9,PD=9);\n"
+    "  device HVNMOS $4 (S=GND,G=$3,D=Z,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=1.74,PD=1.74);\n"
+    "  device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);\n"
     "  device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);\n"
     "end;\n"
     "circuit .TOP ();\n"
diff --git a/testdata/ruby/dbNetlistReaderTests.rb b/testdata/ruby/dbNetlistReaderTests.rb
index 3127e71f4..3e138d288 100644
--- a/testdata/ruby/dbNetlistReaderTests.rb
+++ b/testdata/ruby/dbNetlistReaderTests.rb
@@ -92,12 +92,12 @@ class DBNetlistReaderTests_TestClass < TestBase
     assert_equal(nl.description, "Read by MyDelegate (sucessfully)")
 
     assert_equal(nl.to_s, <<"END")
-circuit SUBCKT ($1=$1,$2=A,$3=VDD,$4=Z,$5=gnd,$6=gnd$1);
+circuit SUBCKT ($1=$1,$2=A,$3=VDD,$4=Z,$5=GND,$6=GND$1);
   device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);
   device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);
-  device HVNMOS $3 (S=gnd,G=$3,D=gnd,B=gnd$1) (L=1.695,W=3.18,AS=0,AD=0,PS=9,PD=9);
-  device HVNMOS $4 (S=gnd,G=$3,D=Z,B=gnd$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=1.74,PD=1.74);
-  device HVNMOS $5 (S=gnd,G=A,D=$3,B=gnd$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);
+  device HVNMOS $3 (S=GND,G=$3,D=GND,B=GND$1) (L=1.695,W=3.18,AS=0,AD=0,PS=9,PD=9);
+  device HVNMOS $4 (S=GND,G=$3,D=Z,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=1.74,PD=1.74);
+  device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);
   device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);
 end;
 circuit .TOP ();