diff --git a/src/lvs/unit_tests/lvsTests.cc b/src/lvs/unit_tests/lvsTests.cc
index 001df63da..74e618c27 100644
--- a/src/lvs/unit_tests/lvsTests.cc
+++ b/src/lvs/unit_tests/lvsTests.cc
@@ -148,7 +148,7 @@ TEST(16_private)
 TEST(17_private)
 {
   test_is_long_runner ();
-  run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_4.lvsdb");
+  run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_5.lvsdb");
 }
 
 TEST(18_private)
diff --git a/testdata/algo/l2n_writer_au_2.gds b/testdata/algo/l2n_writer_au_2.gds
index 37ba81471..ad1f8eb42 100644
Binary files a/testdata/algo/l2n_writer_au_2.gds and b/testdata/algo/l2n_writer_au_2.gds differ
diff --git a/testdata/algo/l2n_writer_au_p.txt b/testdata/algo/l2n_writer_au_p.txt
index 84e52624e..f3143941d 100644
--- a/testdata/algo/l2n_writer_au_p.txt
+++ b/testdata/algo/l2n_writer_au_p.txt
@@ -71,7 +71,13 @@ D(D$NMOS$1 NMOS
 )
 X(INV2
  R((-1700 -800) (3100 4600))
+ F(#17 #42)
+ F('a_"non_quoted"_string' 's')
+ F('a_float' ##0.5)
  N(1 I(IN)
+  F(#17 #142)
+  F('a_"non_quoted"_string' '1s')
+  F('a_float' ##10.5)
   R(poly (-525 -250) (250 2500))
   R(poly (-1425 -630) (1300 360))
   R(poly (-125 -2780) (250 1600))
@@ -191,13 +197,7 @@ X(INV2
 )
 X(RINGO
  R((-1720 -800) (26880 4600))
- F(#17 #42)
- F('a_"non_quoted"_string' 's')
- F('a_float' ##0.5)
  N(1 I(FB)
-  F(#17 #142)
-  F('a_"non_quoted"_string' '1s')
-  F('a_float' ##10.5)
   R(metal1 (-1700 1620) (360 360))
   R(via1 (-305 -305) (250 250))
   R(via1 (24230 -250) (250 250))
diff --git a/testdata/lvs/floating.cir b/testdata/lvs/floating.cir
index 9acc99ffe..dfbfbd09f 100644
--- a/testdata/lvs/floating.cir
+++ b/testdata/lvs/floating.cir
@@ -43,8 +43,8 @@ X$2 3 5 2 6 INVX1
 * net 2 VDD
 * net 3 IN
 * net 4 VSS
-* device instance $1 r0 *1 0.85,5.8 PMOS
-M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
-* device instance $2 r0 *1 0.85,2.135 NMOS
-M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+* device instance $1 r0 *1 0.85,2.135 NMOS
+M$1 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+* device instance $2 r0 *1 0.85,5.8 PMOS
+M$2 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
 .ENDS INVX1
diff --git a/testdata/lvs/floating.lvsdb b/testdata/lvs/floating.lvsdb
index 3822292b2..e3bbfcc38 100644
--- a/testdata/lvs/floating.lvsdb
+++ b/testdata/lvs/floating.lvsdb
@@ -135,20 +135,7 @@ layout(
   pin(4 name(VSS))
 
   # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 2)
-   terminal(G 3)
-   terminal(D 1)
-   terminal(B 2)
-  )
-  device(2 D$NMOS
+  device(1 D$NMOS
    location(850 2135)
    param(L 0.25)
    param(W 0.95)
@@ -161,6 +148,19 @@ layout(
    terminal(D 1)
    terminal(B 4)
   )
+  device(2 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 2)
+   terminal(G 3)
+   terminal(D 1)
+   terminal(B 2)
+  )
 
  )
  circuit(DINV
@@ -410,8 +410,8 @@ xref(
    pin(0 1 match)
    pin(1 2 match)
    pin(3 3 match)
-   device(2 1 match)
-   device(1 2 match)
+   device(1 1 match)
+   device(2 2 match)
   )
  )
  circuit(TOP TOP match
diff --git a/testdata/lvs/invchain_cheat.cir.1 b/testdata/lvs/invchain_cheat.cir
similarity index 100%
rename from testdata/lvs/invchain_cheat.cir.1
rename to testdata/lvs/invchain_cheat.cir
index 95fe6cd10..b4be279a6 100644
--- a/testdata/lvs/invchain_cheat.cir.1
+++ b/testdata/lvs/invchain_cheat.cir
@@ -6,17 +6,17 @@ X$2 \$5 \$6 \$4 \$5 VDD VSS INV2
 X$3 VSS VDD \$6 OUT INV
 .ENDS INVCHAIN
 
+.SUBCKT INV2 \$I8 \$I7 \$I6 \$I5 \$I4 \$I2
+X$1 \$I2 \$I4 \$I6 \$I8 INV
+X$2 \$I2 \$I4 \$I5 \$I7 INV
+.ENDS INV2
+
 .SUBCKT INV3 3 5 7 4 6 8 \$I4 \$I2
 X$1 \$I2 \$I4 3 4 INV
 X$2 \$I2 \$I4 5 6 INV
 X$3 \$I2 \$I4 7 8 INV
 .ENDS INV3
 
-.SUBCKT INV2 \$I8 \$I7 \$I6 \$I5 \$I4 \$I2
-X$1 \$I2 \$I4 \$I6 \$I8 INV
-X$2 \$I2 \$I4 \$I5 \$I7 INV
-.ENDS INV2
-
 .SUBCKT INV \$1 \$2 \$3 \$4
 M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
 + PD=3.45U
diff --git a/testdata/lvs/invchain_cheat.lvsdb b/testdata/lvs/invchain_cheat.lvsdb
index bf85c951c..c5fa8c4b6 100644
--- a/testdata/lvs/invchain_cheat.lvsdb
+++ b/testdata/lvs/invchain_cheat.lvsdb
@@ -116,33 +116,6 @@ J(
    T(D 1)
   )
  )
- X(INV2
-  R((0 0) (5500 4600))
-  N(1)
-  N(2)
-  N(3)
-  N(4)
-  N(5)
-  N(6)
-  P(1)
-  P(2)
-  P(3)
-  P(4)
-  P(5)
-  P(6)
-  X(1 INV M O(180) Y(1500 800)
-   P(0 6)
-   P(1 5)
-   P(2 3)
-   P(3 1)
-  )
-  X(2 INV Y(4000 800)
-   P(0 6)
-   P(1 5)
-   P(2 4)
-   P(3 2)
-  )
- )
  X(INV3
   R((0 0) (6300 4600))
   N(1 I('3')
@@ -192,6 +165,33 @@ J(
    P(3 6)
   )
  )
+ X(INV2
+  R((0 0) (5500 4600))
+  N(1)
+  N(2)
+  N(3)
+  N(4)
+  N(5)
+  N(6)
+  P(1)
+  P(2)
+  P(3)
+  P(4)
+  P(5)
+  P(6)
+  X(1 INV M O(180) Y(1500 800)
+   P(0 6)
+   P(1 5)
+   P(2 3)
+   P(3 1)
+  )
+  X(2 INV Y(4000 800)
+   P(0 6)
+   P(1 5)
+   P(2 4)
+   P(3 2)
+  )
+ )
  X(INVCHAIN
   R((-1500 -800) (10400 4600))
   N(1 I(IN)
diff --git a/testdata/lvs/layer_names.cir b/testdata/lvs/layer_names.cir
index 9acc99ffe..dfbfbd09f 100644
--- a/testdata/lvs/layer_names.cir
+++ b/testdata/lvs/layer_names.cir
@@ -43,8 +43,8 @@ X$2 3 5 2 6 INVX1
 * net 2 VDD
 * net 3 IN
 * net 4 VSS
-* device instance $1 r0 *1 0.85,5.8 PMOS
-M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
-* device instance $2 r0 *1 0.85,2.135 NMOS
-M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+* device instance $1 r0 *1 0.85,2.135 NMOS
+M$1 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+* device instance $2 r0 *1 0.85,5.8 PMOS
+M$2 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
 .ENDS INVX1
diff --git a/testdata/lvs/layer_names.lvsdb b/testdata/lvs/layer_names.lvsdb
index 1a9df5bf6..24ee02136 100644
--- a/testdata/lvs/layer_names.lvsdb
+++ b/testdata/lvs/layer_names.lvsdb
@@ -135,20 +135,7 @@ layout(
   pin(4 name(VSS))
 
   # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 2)
-   terminal(G 3)
-   terminal(D 1)
-   terminal(B 2)
-  )
-  device(2 D$NMOS
+  device(1 D$NMOS
    location(850 2135)
    param(L 0.25)
    param(W 0.95)
@@ -161,6 +148,19 @@ layout(
    terminal(D 1)
    terminal(B 4)
   )
+  device(2 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 2)
+   terminal(G 3)
+   terminal(D 1)
+   terminal(B 2)
+  )
 
  )
  circuit(DINV
@@ -410,8 +410,8 @@ xref(
    pin(0 1 match)
    pin(1 2 match)
    pin(3 3 match)
-   device(2 1 match)
-   device(1 2 match)
+   device(1 1 match)
+   device(2 2 match)
   )
  )
  circuit(TOP TOP match
diff --git a/testdata/lvs/ringo_mixed_hierarchy.cir b/testdata/lvs/ringo_mixed_hierarchy.cir
index 6a8f50780..1f0ebe297 100644
--- a/testdata/lvs/ringo_mixed_hierarchy.cir
+++ b/testdata/lvs/ringo_mixed_hierarchy.cir
@@ -57,8 +57,8 @@ M$4 4 1 15 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
 * net 3 VSS
 * net 5 IN
 * net 6 SUBSTRATE
-* device instance $1 r0 *1 0.85,5.8 PMOS
-M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
-* device instance $2 r0 *1 0.85,2.135 NMOS
-M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+* device instance $1 r0 *1 0.85,2.135 NMOS
+M$1 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
+* device instance $2 r0 *1 0.85,5.8 PMOS
+M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
 .ENDS INVX1
diff --git a/testdata/lvs/ringo_mixed_hierarchy.lvsdb b/testdata/lvs/ringo_mixed_hierarchy.lvsdb
index 35c7fd126..aaab4f995 100644
--- a/testdata/lvs/ringo_mixed_hierarchy.lvsdb
+++ b/testdata/lvs/ringo_mixed_hierarchy.lvsdb
@@ -190,20 +190,7 @@ layout(
   pin(6 name(SUBSTRATE))
 
   # Devices and their connections
-  device(1 D$PMOS$2
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 D$NMOS$2
+  device(1 D$NMOS$2
    location(850 2135)
    param(L 0.25)
    param(W 0.95)
@@ -216,6 +203,19 @@ layout(
    terminal(D 2)
    terminal(B 6)
   )
+  device(2 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
 
  )
  circuit(RINGO
@@ -770,8 +770,8 @@ xref(
    pin(5 5 match)
    pin(0 0 match)
    pin(2 2 match)
-   device(2 2 match)
-   device(1 1 match)
+   device(1 2 match)
+   device(2 1 match)
   )
  )
  circuit(RINGO RINGO match
diff --git a/testdata/lvs/ringo_simple_blackboxing.cir b/testdata/lvs/ringo_simple_blackboxing.cir
index e6a7e5bcc..57d864ae5 100644
--- a/testdata/lvs/ringo_simple_blackboxing.cir
+++ b/testdata/lvs/ringo_simple_blackboxing.cir
@@ -38,6 +38,17 @@ X$20 6 15 9 6 14 9 INVX1
 X$21 6 11 9 6 15 9 INVX1
 .ENDS RINGO
 
+* cell ND2X1
+* pin VDD
+* pin OUT
+* pin VSS
+* pin 
+* pin B
+* pin A
+* pin BULK
+.SUBCKT ND2X1 1 2 3 4 5 6 7
+.ENDS ND2X1
+
 * cell INVX2
 * pin IN
 * pin VDD
@@ -57,14 +68,3 @@ X$21 6 11 9 6 15 9 INVX1
 * pin BULK
 .SUBCKT INVX1 1 2 3 4 5 6
 .ENDS INVX1
-
-* cell ND2X1
-* pin VDD
-* pin OUT
-* pin VSS
-* pin 
-* pin B
-* pin A
-* pin BULK
-.SUBCKT ND2X1 1 2 3 4 5 6 7
-.ENDS ND2X1
diff --git a/testdata/lvs/ringo_simple_blackboxing.lvsdb b/testdata/lvs/ringo_simple_blackboxing.lvsdb
index 938c32edf..c2cdd8571 100644
--- a/testdata/lvs/ringo_simple_blackboxing.lvsdb
+++ b/testdata/lvs/ringo_simple_blackboxing.lvsdb
@@ -43,21 +43,6 @@ layout(
 
  # Circuit section
  # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Circuit boundary
-  rect((-100 250) (2600 7750))
-
-  # Outgoing pins and their connections to nets
-  pin(name(VDD))
-  pin(name(OUT))
-  pin(name(VSS))
-  pin()
-  pin(name(B))
-  pin(name(A))
-  pin(name(BULK))
-
- )
  circuit(INVX1
 
   # Circuit boundary
@@ -85,6 +70,21 @@ layout(
   pin()
   pin(name(BULK))
 
+ )
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 250) (2600 7750))
+
+  # Outgoing pins and their connections to nets
+  pin(name(VDD))
+  pin(name(OUT))
+  pin(name(VSS))
+  pin()
+  pin(name(B))
+  pin(name(A))
+  pin(name(BULK))
+
  )
  circuit(RINGO
 
diff --git a/testdata/lvs/ringo_simple_blackboxing_netter.cir b/testdata/lvs/ringo_simple_blackboxing_netter.cir
index e6a7e5bcc..57d864ae5 100644
--- a/testdata/lvs/ringo_simple_blackboxing_netter.cir
+++ b/testdata/lvs/ringo_simple_blackboxing_netter.cir
@@ -38,6 +38,17 @@ X$20 6 15 9 6 14 9 INVX1
 X$21 6 11 9 6 15 9 INVX1
 .ENDS RINGO
 
+* cell ND2X1
+* pin VDD
+* pin OUT
+* pin VSS
+* pin 
+* pin B
+* pin A
+* pin BULK
+.SUBCKT ND2X1 1 2 3 4 5 6 7
+.ENDS ND2X1
+
 * cell INVX2
 * pin IN
 * pin VDD
@@ -57,14 +68,3 @@ X$21 6 11 9 6 15 9 INVX1
 * pin BULK
 .SUBCKT INVX1 1 2 3 4 5 6
 .ENDS INVX1
-
-* cell ND2X1
-* pin VDD
-* pin OUT
-* pin VSS
-* pin 
-* pin B
-* pin A
-* pin BULK
-.SUBCKT ND2X1 1 2 3 4 5 6 7
-.ENDS ND2X1
diff --git a/testdata/lvs/ringo_simple_blackboxing_netter.lvsdb b/testdata/lvs/ringo_simple_blackboxing_netter.lvsdb
index 938c32edf..c2cdd8571 100644
--- a/testdata/lvs/ringo_simple_blackboxing_netter.lvsdb
+++ b/testdata/lvs/ringo_simple_blackboxing_netter.lvsdb
@@ -43,21 +43,6 @@ layout(
 
  # Circuit section
  # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Circuit boundary
-  rect((-100 250) (2600 7750))
-
-  # Outgoing pins and their connections to nets
-  pin(name(VDD))
-  pin(name(OUT))
-  pin(name(VSS))
-  pin()
-  pin(name(B))
-  pin(name(A))
-  pin(name(BULK))
-
- )
  circuit(INVX1
 
   # Circuit boundary
@@ -85,6 +70,21 @@ layout(
   pin()
   pin(name(BULK))
 
+ )
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 250) (2600 7750))
+
+  # Outgoing pins and their connections to nets
+  pin(name(VDD))
+  pin(name(OUT))
+  pin(name(VSS))
+  pin()
+  pin(name(B))
+  pin(name(A))
+  pin(name(BULK))
+
  )
  circuit(RINGO
 
diff --git a/testdata/lvs/ringo_simple_simplification_with_align.cir b/testdata/lvs/ringo_simple_simplification_with_align.cir
index 4996f57fa..00c2f73be 100644
--- a/testdata/lvs/ringo_simple_simplification_with_align.cir
+++ b/testdata/lvs/ringo_simple_simplification_with_align.cir
@@ -26,16 +26,16 @@ X$5 6 4 9 6 3 9 INVX1
 X$6 6 5 9 6 4 9 INVX1
 * cell instance $7 r0 *1 22.2,0
 X$7 5 6 7 9 6 9 INVX2
-* cell instance $13 r0 *1 7.8,0
-X$13 6 12 9 6 10 9 INVX1
-* cell instance $14 r0 *1 9.6,0
-X$14 6 13 9 6 12 9 INVX1
-* cell instance $15 r0 *1 11.4,0
-X$15 6 14 9 6 13 9 INVX1
-* cell instance $16 r0 *1 13.2,0
-X$16 6 15 9 6 14 9 INVX1
-* cell instance $17 r0 *1 15,0
-X$17 6 11 9 6 15 9 INVX1
+* cell instance $17 r0 *1 7.8,0
+X$17 6 12 9 6 10 9 INVX1
+* cell instance $18 r0 *1 9.6,0
+X$18 6 13 9 6 12 9 INVX1
+* cell instance $19 r0 *1 11.4,0
+X$19 6 14 9 6 13 9 INVX1
+* cell instance $20 r0 *1 13.2,0
+X$20 6 15 9 6 14 9 INVX1
+* cell instance $21 r0 *1 15,0
+X$21 6 11 9 6 15 9 INVX1
 .ENDS RINGO
 
 * cell INVX2
diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1
index acb6dfc04..cf50d6703 100644
--- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1
+++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1
@@ -644,7 +644,7 @@ layout(
    pin(4 6)
    pin(5 9)
   )
-  circuit(13 INVX1 location(7800 0)
+  circuit(17 INVX1 location(7800 0)
    pin(0 6)
    pin(1 12)
    pin(2 9)
@@ -652,7 +652,7 @@ layout(
    pin(4 10)
    pin(5 9)
   )
-  circuit(14 INVX1 location(9600 0)
+  circuit(18 INVX1 location(9600 0)
    pin(0 6)
    pin(1 13)
    pin(2 9)
@@ -660,7 +660,7 @@ layout(
    pin(4 12)
    pin(5 9)
   )
-  circuit(15 INVX1 location(11400 0)
+  circuit(19 INVX1 location(11400 0)
    pin(0 6)
    pin(1 14)
    pin(2 9)
@@ -668,7 +668,7 @@ layout(
    pin(4 13)
    pin(5 9)
   )
-  circuit(16 INVX1 location(13200 0)
+  circuit(20 INVX1 location(13200 0)
    pin(0 6)
    pin(1 15)
    pin(2 9)
@@ -676,7 +676,7 @@ layout(
    pin(4 14)
    pin(5 9)
   )
-  circuit(17 INVX1 location(15000 0)
+  circuit(21 INVX1 location(15000 0)
    pin(0 6)
    pin(1 11)
    pin(2 9)
@@ -1080,11 +1080,11 @@ xref(
    pin(4 0 match)
    circuit(2 2 match)
    circuit(3 3 match)
-   circuit(13 4 match)
-   circuit(14 5 match)
-   circuit(15 6 match)
-   circuit(16 7 match)
-   circuit(17 8 match)
+   circuit(17 4 match)
+   circuit(18 5 match)
+   circuit(19 6 match)
+   circuit(20 7 match)
+   circuit(21 8 match)
    circuit(4 9 match)
    circuit(5 10 match)
    circuit(6 11 match)
diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2
deleted file mode 100644
index 650cb1b5a..000000000
--- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2
+++ /dev/null
@@ -1,1095 +0,0 @@
-#%lvsdb-klayout
-
-# Layout
-layout(
- top(RINGO)
- unit(0.001)
-
- # Layer section
- # This section lists the mask layers (drawing or derived) and their connections.
-
- # Mask layers
- layer(l3 '1/0')
- layer(l4 '5/0')
- layer(l8 '8/0')
- layer(l11 '9/0')
- layer(l12 '10/0')
- layer(l13 '11/0')
- layer(l7)
- layer(l2)
- layer(l9)
- layer(l6)
- layer(l10)
-
- # Mask layer connectivity
- connect(l3 l3 l9)
- connect(l4 l4 l8)
- connect(l8 l4 l8 l11 l2 l9 l6 l10)
- connect(l11 l8 l11 l12)
- connect(l12 l11 l12 l13)
- connect(l13 l12 l13)
- connect(l7 l7)
- connect(l2 l8 l2)
- connect(l9 l3 l8 l9)
- connect(l6 l8 l6)
- connect(l10 l8 l10)
-
- # Global nets and connectivity
- global(l7 SUBSTRATE)
- global(l10 SUBSTRATE)
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Device abstracts section
- # Device abstracts list the pin shapes of the devices.
- device(D$PMOS PMOS
-  terminal(S
-   rect(l2 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l2 (125 -750) (450 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$1 PMOS
-  terminal(S
-   rect(l2 (-575 -750) (450 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l2 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$2 PMOS
-  terminal(S
-   rect(l2 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l2 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$NMOS NMOS
-  terminal(S
-   rect(l6 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (450 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$1 NMOS
-  terminal(S
-   rect(l6 (-575 -475) (450 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$2 NMOS
-  terminal(S
-   rect(l6 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Circuit boundary
-  rect((-100 400) (2600 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -790) (300 1700))
-   rect(l11 (-1350 0) (2400 800))
-   rect(l11 (-1150 -400) (0 0))
-   rect(l2 (-275 -2150) (425 1500))
-   rect(l2 (-400 -1500) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1810 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-1580 3760) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (1220 920) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
-   rect(l11 (-110 1390) (300 1400))
-   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
-   rect(l11 (-140 -500) (0 0))
-   rect(l11 (-1750 1100) (300 1400))
-   rect(l11 (1100 -1700) (300 300))
-   rect(l11 (-300 0) (300 1400))
-   rect(l2 (-375 -1450) (425 1500))
-   rect(l2 (-1800 -1500) (425 1500))
-   rect(l6 (950 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (2400 800))
-   rect(l11 (-1150 -400) (0 0))
-   rect(l6 (-950 860) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2600 3500))
-  )
-  net(5 name(B)
-   rect(l4 (1425 2860) (250 1940))
-   rect(l4 (-345 -950) (300 300))
-   rect(l4 (-205 650) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-285 1050) (180 180))
-   rect(l11 (-70 -90) (0 0))
-   rect(l11 (-170 -150) (300 300))
-  )
-  net(6 name(A)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-325 -1850) (300 300))
-   rect(l4 (-225 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-265 150) (180 180))
-   rect(l11 (-90 -90) (0 0))
-   rect(l11 (-150 -150) (300 300))
-  )
-  net(7 name(SUBSTRATE))
-  net(8
-   rect(l6 (975 1660) (425 950))
-   rect(l6 (-400 -950) (425 950))
-  )
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.3375)
-   param(PS 3.85)
-   param(PD 1.95)
-   terminal(S 2)
-   terminal(G 6)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 D$PMOS$1
-   location(1550 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.3375)
-   param(AD 0.6375)
-   param(PS 1.95)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 D$NMOS
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.21375)
-   param(PS 2.75)
-   param(PD 1.4)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 D$NMOS$1
-   location(1550 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.21375)
-   param(AD 0.40375)
-   param(PS 1.4)
-   param(PD 2.75)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Circuit boundary
-  rect((-100 400) (2000 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (410 6260) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -240) (300 1400))
-   rect(l11 (-650 300) (1800 800))
-   rect(l11 (-1450 -1100) (300 300))
-   rect(l11 (300 400) (0 0))
-   rect(l2 (-650 -2150) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -4120) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -790) (300 4790))
-   rect(l11 (-150 -2500) (0 0))
-   rect(l2 (-225 1050) (425 1500))
-   rect(l6 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (1800 800))
-   rect(l11 (-850 -400) (0 0))
-   rect(l6 (-650 860) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2000 3500))
-  )
-  net(5 name(IN)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-525 -1850) (300 300))
-   rect(l4 (-25 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-465 150) (180 180))
-   rect(l11 (-90 -90) (0 0))
-   rect(l11 (-150 -150) (300 300))
-  )
-  net(6 name(SUBSTRATE))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(IN))
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS$2
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 D$NMOS$2
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.40375)
-   param(PS 2.75)
-   param(PD 2.75)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(INVX2
-
-  # Circuit boundary
-  rect((-100 400) (2600 7600))
-
-  # Nets with their geometries
-  net(1 name(IN)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-225 -1300) (675 450))
-   rect(l4 (0 -1100) (250 1950))
-   rect(l4 (-1225 -1850) (300 300))
-   rect(l4 (675 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-950 -2000) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (450 -5390) (250 1450))
-   rect(l4 (-950 -1450) (250 1450))
-   rect(l8 (-465 150) (180 180))
-   rect(l11 (-90 -90) (0 0))
-   rect(l11 (-150 -150) (300 300))
-  )
-  net(2 name(VDD)
-   rect(l8 (410 6260) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (1220 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-1640 -240) (300 1400))
-   rect(l11 (-650 300) (2400 800))
-   rect(l11 (-2050 -1100) (300 300))
-   rect(l11 (1100 -300) (300 300))
-   rect(l11 (-1100 400) (0 0))
-   rect(l11 (800 -2100) (300 1400))
-   rect(l2 (-375 -1450) (425 1500))
-   rect(l2 (-1800 -1500) (425 1500))
-  )
-  net(3 name(OUT)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -4120) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -790) (300 4790))
-   rect(l11 (-150 -2500) (0 0))
-   rect(l2 (-225 1050) (425 1500))
-   rect(l2 (-400 -1500) (425 1500))
-   rect(l6 (-450 -4890) (425 950))
-   rect(l6 (-400 -950) (425 950))
-  )
-  net(4 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (1220 -730) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-1640 -1300) (300 1360))
-   rect(l11 (-650 -2160) (2400 800))
-   rect(l11 (-650 0) (300 1360))
-   rect(l11 (-1100 -1760) (0 0))
-   rect(l6 (725 860) (425 950))
-   rect(l6 (-1800 -950) (425 950))
-  )
-  net(5
-   rect(l3 (-100 4500) (2600 3500))
-  )
-  net(6 name(SUBSTRATE))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(IN))
-  pin(2 name(VDD))
-  pin(3 name(OUT))
-  pin(4 name(VSS))
-  pin(5)
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   device(D$PMOS$1 location(700 0))
-   connect(0 S S)
-   connect(1 S D)
-   connect(0 G G)
-   connect(1 G G)
-   connect(0 D D)
-   connect(1 D S)
-   connect(0 B B)
-   connect(1 B B)
-   location(850 5800)
-   param(L 0.25)
-   param(W 3)
-   param(AS 0.975)
-   param(AD 0.975)
-   param(PS 5.8)
-   param(PD 5.8)
-   terminal(S 2)
-   terminal(G 1)
-   terminal(D 3)
-   terminal(B 5)
-  )
-  device(3 D$NMOS
-   device(D$NMOS$1 location(700 0))
-   connect(0 S S)
-   connect(1 S D)
-   connect(0 G G)
-   connect(1 G G)
-   connect(0 D D)
-   connect(1 D S)
-   connect(0 B B)
-   connect(1 B B)
-   location(850 2135)
-   param(L 0.25)
-   param(W 1.9)
-   param(AS 0.6175)
-   param(AD 0.6175)
-   param(PS 4.15)
-   param(PD 4.15)
-   terminal(S 4)
-   terminal(G 1)
-   terminal(D 3)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Circuit boundary
-  rect((600 350) (25800 7650))
-
-  # Nets with their geometries
-  net(1
-   rect(l11 (4040 2950) (610 300))
-  )
-  net(2
-   rect(l11 (5550 2950) (900 300))
-  )
-  net(3
-   rect(l11 (18150 2950) (900 300))
-  )
-  net(4
-   rect(l11 (19950 2950) (900 300))
-  )
-  net(5 name(FB)
-   rect(l11 (21750 2950) (900 300))
-   rect(l11 (-19530 590) (320 320))
-   rect(l11 (17820 -320) (320 320))
-   rect(l12 (-18400 -260) (200 200))
-   rect(l12 (17940 -200) (200 200))
-   rect(l13 (-18040 -300) (17740 400))
-   rect(l13 (-17920 -200) (0 0))
-   rect(l13 (-220 -200) (400 400))
-   rect(l13 (17740 -400) (400 400))
-  )
-  net(6 name(VDD)
-   rect(l3 (1100 4500) (1400 3500))
-   rect(l3 (-1900 -3500) (600 3500))
-   rect(l3 (23300 -3500) (1400 3500))
-   rect(l3 (-100 -3500) (600 3500))
-   rect(l8 (-24690 -1240) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (23220 370) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l11 (-22340 860) (0 0))
-   rect(l11 (-1750 -450) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-100 -350) (0 0))
-   rect(l11 (-1250 -400) (600 800))
-   rect(l11 (23400 -800) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-100 -350) (0 0))
-   rect(l11 (550 -400) (600 800))
-   rect(l9 (-24850 -1500) (500 1500))
-   rect(l9 (22900 -1500) (500 1500))
-  )
-  net(7 name(OUT)
-   rect(l11 (23440 3840) (320 320))
-   rect(l12 (-260 -260) (200 200))
-   rect(l13 (-100 -100) (0 0))
-   rect(l13 (-200 -200) (400 400))
-  )
-  net(8 name(ENABLE)
-   rect(l11 (2440 2940) (320 320))
-   rect(l12 (-260 -260) (200 200))
-   rect(l13 (-100 -100) (0 0))
-   rect(l13 (-200 -200) (400 400))
-  )
-  net(9 name(VSS)
-   rect(l8 (1710 1610) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (23220 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-22340 -390) (0 0))
-   rect(l11 (-1300 -400) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (-1250 -400) (600 800))
-   rect(l11 (23850 -750) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (550 -400) (600 800))
-   rect(l10 (-24850 -800) (500 1500))
-   rect(l10 (22900 -1500) (500 1500))
-  )
-  net(10
-   rect(l11 (7350 2950) (900 300))
-  )
-  net(11
-   rect(l11 (16350 2950) (900 300))
-  )
-  net(12
-   rect(l11 (9150 2950) (900 300))
-  )
-  net(13
-   rect(l11 (10950 2950) (900 300))
-  )
-  net(14
-   rect(l11 (12750 2950) (900 300))
-  )
-  net(15
-   rect(l11 (14550 2950) (900 300))
-  )
-
-  # Outgoing pins and their connections to nets
-  pin(5 name(FB))
-  pin(6 name(VDD))
-  pin(7 name(OUT))
-  pin(8 name(ENABLE))
-  pin(9 name(VSS))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 location(1800 0)
-   pin(0 6)
-   pin(1 1)
-   pin(2 9)
-   pin(3 6)
-   pin(4 5)
-   pin(5 8)
-   pin(6 9)
-  )
-  circuit(2 INVX1 location(4200 0)
-   pin(0 6)
-   pin(1 2)
-   pin(2 9)
-   pin(3 6)
-   pin(4 1)
-   pin(5 9)
-  )
-  circuit(3 INVX1 location(6000 0)
-   pin(0 6)
-   pin(1 10)
-   pin(2 9)
-   pin(3 6)
-   pin(4 2)
-   pin(5 9)
-  )
-  circuit(4 INVX1 location(16800 0)
-   pin(0 6)
-   pin(1 3)
-   pin(2 9)
-   pin(3 6)
-   pin(4 11)
-   pin(5 9)
-  )
-  circuit(5 INVX1 location(18600 0)
-   pin(0 6)
-   pin(1 4)
-   pin(2 9)
-   pin(3 6)
-   pin(4 3)
-   pin(5 9)
-  )
-  circuit(6 INVX1 location(20400 0)
-   pin(0 6)
-   pin(1 5)
-   pin(2 9)
-   pin(3 6)
-   pin(4 4)
-   pin(5 9)
-  )
-  circuit(7 INVX2 location(22200 0)
-   pin(0 5)
-   pin(1 6)
-   pin(2 7)
-   pin(3 9)
-   pin(4 6)
-   pin(5 9)
-  )
-  circuit(13 INVX1 location(7800 0)
-   pin(0 6)
-   pin(1 12)
-   pin(2 9)
-   pin(3 6)
-   pin(4 10)
-   pin(5 9)
-  )
-  circuit(14 INVX1 location(9600 0)
-   pin(0 6)
-   pin(1 13)
-   pin(2 9)
-   pin(3 6)
-   pin(4 12)
-   pin(5 9)
-  )
-  circuit(15 INVX1 location(11400 0)
-   pin(0 6)
-   pin(1 14)
-   pin(2 9)
-   pin(3 6)
-   pin(4 13)
-   pin(5 9)
-  )
-  circuit(16 INVX1 location(13200 0)
-   pin(0 6)
-   pin(1 15)
-   pin(2 9)
-   pin(3 6)
-   pin(4 14)
-   pin(5 9)
-  )
-  circuit(17 INVX1 location(15000 0)
-   pin(0 6)
-   pin(1 11)
-   pin(2 9)
-   pin(3 6)
-   pin(4 15)
-   pin(5 9)
-  )
-
- )
-)
-
-# Reference netlist
-reference(
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(B))
-  net(6 name(A))
-  net(7 name(BULK))
-  net(8 name('1'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 6)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 PMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 5)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(3 NMOS
-   name($3)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 8)
-   terminal(G 6)
-   terminal(D 3)
-   terminal(B 7)
-  )
-  device(4 NMOS
-   name($4)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 5)
-   terminal(D 8)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(IN))
-  pin(6 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 5)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 5)
-   terminal(D 3)
-   terminal(B 6)
-  )
-
- )
- circuit(INVX2
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(IN))
-  pin(6 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 3)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 5)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.9)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 5)
-   terminal(D 3)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Nets
-  net(1 name(VSS))
-  net(2 name(VDD))
-  net(3 name(FB))
-  net(4 name(ENABLE))
-  net(5 name(OUT))
-  net(6 name('1'))
-  net(7 name('2'))
-  net(8 name('3'))
-  net(9 name('4'))
-  net(10 name('5'))
-  net(11 name('6'))
-  net(12 name('7'))
-  net(13 name('8'))
-  net(14 name('9'))
-  net(15 name('10'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VSS))
-  pin(2 name(VDD))
-  pin(3 name(FB))
-  pin(4 name(ENABLE))
-  pin(5 name(OUT))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 name($1)
-   pin(0 2)
-   pin(1 6)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 4)
-   pin(6 1)
-  )
-  circuit(2 INVX1 name($2)
-   pin(0 2)
-   pin(1 7)
-   pin(2 1)
-   pin(3 2)
-   pin(4 6)
-   pin(5 1)
-  )
-  circuit(3 INVX1 name($3)
-   pin(0 2)
-   pin(1 8)
-   pin(2 1)
-   pin(3 2)
-   pin(4 7)
-   pin(5 1)
-  )
-  circuit(4 INVX1 name($4)
-   pin(0 2)
-   pin(1 9)
-   pin(2 1)
-   pin(3 2)
-   pin(4 8)
-   pin(5 1)
-  )
-  circuit(5 INVX1 name($5)
-   pin(0 2)
-   pin(1 10)
-   pin(2 1)
-   pin(3 2)
-   pin(4 9)
-   pin(5 1)
-  )
-  circuit(6 INVX1 name($6)
-   pin(0 2)
-   pin(1 11)
-   pin(2 1)
-   pin(3 2)
-   pin(4 10)
-   pin(5 1)
-  )
-  circuit(7 INVX1 name($7)
-   pin(0 2)
-   pin(1 12)
-   pin(2 1)
-   pin(3 2)
-   pin(4 11)
-   pin(5 1)
-  )
-  circuit(8 INVX1 name($8)
-   pin(0 2)
-   pin(1 13)
-   pin(2 1)
-   pin(3 2)
-   pin(4 12)
-   pin(5 1)
-  )
-  circuit(9 INVX1 name($9)
-   pin(0 2)
-   pin(1 14)
-   pin(2 1)
-   pin(3 2)
-   pin(4 13)
-   pin(5 1)
-  )
-  circuit(10 INVX1 name($10)
-   pin(0 2)
-   pin(1 15)
-   pin(2 1)
-   pin(3 2)
-   pin(4 14)
-   pin(5 1)
-  )
-  circuit(11 INVX1 name($11)
-   pin(0 2)
-   pin(1 3)
-   pin(2 1)
-   pin(3 2)
-   pin(4 15)
-   pin(5 1)
-  )
-  circuit(12 INVX2 name($12)
-   pin(0 2)
-   pin(1 5)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 1)
-  )
-
- )
-)
-
-# Cross reference
-xref(
- circuit(INVX1 INVX1 match
-  xref(
-   net(4 4 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(6 6 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(5 5 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(2 2 match)
-   device(1 1 match)
-  )
- )
- circuit(INVX2 INVX2 match
-  xref(
-   net(5 4 match)
-   net(1 5 match)
-   net(3 2 match)
-   net(6 6 match)
-   net(2 1 match)
-   net(4 3 match)
-   pin(4 3 match)
-   pin(0 4 match)
-   pin(2 1 match)
-   pin(5 5 match)
-   pin(1 0 match)
-   pin(3 2 match)
-   device(3 2 match)
-   device(1 1 match)
-  )
- )
- circuit(ND2X1 ND2X1 match
-  xref(
-   net(8 8 match)
-   net(4 4 match)
-   net(6 6 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(7 7 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(5 5 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(6 6 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(3 3 match)
-   device(4 4 match)
-   device(1 1 match)
-   device(2 2 match)
-  )
- )
- circuit(RINGO RINGO match
-  xref(
-   net(1 6 match)
-   net(4 15 match)
-   net(2 7 match)
-   net(10 8 match)
-   net(12 9 match)
-   net(13 10 match)
-   net(14 11 match)
-   net(15 12 match)
-   net(11 13 match)
-   net(3 14 match)
-   net(8 4 match)
-   net(5 3 match)
-   net(7 5 match)
-   net(6 2 match)
-   net(9 1 match)
-   pin(3 3 match)
-   pin(0 2 match)
-   pin(2 4 match)
-   pin(1 1 match)
-   pin(4 0 match)
-   circuit(2 2 match)
-   circuit(3 3 match)
-   circuit(13 4 match)
-   circuit(14 5 match)
-   circuit(15 6 match)
-   circuit(16 7 match)
-   circuit(17 8 match)
-   circuit(4 9 match)
-   circuit(5 10 match)
-   circuit(6 11 match)
-   circuit(7 12 match)
-   circuit(1 1 match)
-  )
- )
-)
diff --git a/testdata/lvs/soft_connect3.cir b/testdata/lvs/soft_connect3.cir
index e342448fa..a3a51122f 100644
--- a/testdata/lvs/soft_connect3.cir
+++ b/testdata/lvs/soft_connect3.cir
@@ -10,12 +10,12 @@ X$1 \$5 \$1 \$4 SUBSTRATE NTRANS
 X$2 \$5 \$2 \$4 \$3 PTRANS
 .ENDS INV
 
-.SUBCKT PTRANS \$1 \$3 \$5 \$I3
-M$1 \$3 \$5 \$1 \$I3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
-+ PD=3.45U
-.ENDS PTRANS
-
 .SUBCKT NTRANS \$1 \$3 \$5 SUBSTRATE
 M$1 \$3 \$5 \$1 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
 + PD=3.45U
 .ENDS NTRANS
+
+.SUBCKT PTRANS \$1 \$3 \$5 \$I3
+M$1 \$3 \$5 \$1 \$I3 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
++ PD=3.45U
+.ENDS PTRANS
diff --git a/testdata/lvs/soft_connect3.l2n b/testdata/lvs/soft_connect3.l2n
index f046069b3..559481af0 100644
--- a/testdata/lvs/soft_connect3.l2n
+++ b/testdata/lvs/soft_connect3.l2n
@@ -73,42 +73,6 @@ D(D$NMOS NMOS
   R(l7 (-125 -475) (250 950))
  )
 )
-X(NTRANS
- R((-1000 -800) (2000 1600))
- N(1
-  R(l8 (-510 -310) (220 220))
-  R(l8 (-220 180) (220 220))
-  R(l12 (-290 -690) (360 760))
-  R(l6 (-680 -855) (775 950))
- )
- N(2
-  R(l8 (290 -310) (220 220))
-  R(l8 (-220 180) (220 220))
-  R(l12 (-290 -690) (360 760))
-  R(l6 (-455 -855) (775 950))
- )
- N(3
-  R(l4 (-125 -800) (250 1600))
- )
- N(4 I(SUBSTRATE))
- P(1)
- P(2)
- P(3)
- P(4 I(SUBSTRATE))
- D(1 D$NMOS
-  Y(0 0)
-  E(L 0.25)
-  E(W 0.95)
-  E(AS 0.73625)
-  E(AD 0.73625)
-  E(PS 3.45)
-  E(PD 3.45)
-  T(S 1)
-  T(G 3)
-  T(D 2)
-  T(B 4)
- )
-)
 X(PTRANS
  R((-1000 -800) (2000 1600))
  N(1
@@ -145,6 +109,42 @@ X(PTRANS
   T(B 4)
  )
 )
+X(NTRANS
+ R((-1000 -800) (2000 1600))
+ N(1
+  R(l8 (-510 -310) (220 220))
+  R(l8 (-220 180) (220 220))
+  R(l12 (-290 -690) (360 760))
+  R(l6 (-680 -855) (775 950))
+ )
+ N(2
+  R(l8 (290 -310) (220 220))
+  R(l8 (-220 180) (220 220))
+  R(l12 (-290 -690) (360 760))
+  R(l6 (-455 -855) (775 950))
+ )
+ N(3
+  R(l4 (-125 -800) (250 1600))
+ )
+ N(4 I(SUBSTRATE))
+ P(1)
+ P(2)
+ P(3)
+ P(4 I(SUBSTRATE))
+ D(1 D$NMOS
+  Y(0 0)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.73625)
+  E(AD 0.73625)
+  E(PS 3.45)
+  E(PD 3.45)
+  T(S 1)
+  T(G 3)
+  T(D 2)
+  T(B 4)
+ )
+)
 X(INV
  R((-1500 -800) (3000 4600))
  N(1
diff --git a/testdata/python/dbLayoutToNetlist.py b/testdata/python/dbLayoutToNetlist.py
index 78da9dfbc..81d7118c9 100644
--- a/testdata/python/dbLayoutToNetlist.py
+++ b/testdata/python/dbLayoutToNetlist.py
@@ -286,19 +286,7 @@ end;
     # Perform netlist extraction
     l2n.extract_netlist()
 
-    self.assertEqual(str(l2n.netlist()), """circuit RINGO ();
-  subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
-  subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
-  subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
-  subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
-  subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
-  subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
-  subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
-  subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
-  subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
-  subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
-end;
-circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
+    self.assertEqual(str(l2n.netlist()), """circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
   device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
   device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
   device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
@@ -310,6 +298,18 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
 end;
 circuit TRANS ($1=$1,$2=$2,$3=$3);
 end;
+circuit RINGO ();
+  subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
+  subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
+  subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
+  subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
+  subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
+  subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
+  subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
+  subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
+  subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
+  subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
+end;
 """)
 
     # cleanup now
@@ -401,18 +401,7 @@ end;
     # Perform netlist extraction
     l2n.extract_netlist()
 
-    self.assertEqual(str(l2n.netlist()), """circuit RINGO ();
-  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
-  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
-  subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
-  subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
-  subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
-end;
-circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
-  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
-  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
-end;
-circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
+    self.assertEqual(str(l2n.netlist()), """circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
   device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
   device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
   device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
@@ -424,29 +413,41 @@ circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
 end;
 circuit TRANS ($1=$1,$2=$2,$3=$3);
 end;
-""")
-
-    l2n.netlist().combine_devices()
-    l2n.netlist().make_top_level_pins()
-    l2n.netlist().purge()
-
-    self.assertEqual(str(l2n.netlist()), """circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
+circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
+  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
+  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
+end;
+circuit RINGO ();
   subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
   subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
   subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
   subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
   subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
 end;
-circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
-  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
-  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
-end;
-circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
+""")
+
+    l2n.netlist().combine_devices()
+    l2n.netlist().make_top_level_pins()
+    l2n.netlist().purge()
+
+    print('"""' + str(l2n.netlist()) + '"""')
+    self.assertEqual(str(l2n.netlist()), """circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
   device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
   device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
   device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
   device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
 end;
+circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
+  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
+  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
+end;
+circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
+  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
+  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
+  subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
+  subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
+  subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
+end;
 """)
 
     # cleanup now
diff --git a/testdata/ruby/dbLayoutToNetlist.rb b/testdata/ruby/dbLayoutToNetlist.rb
index 44bb782af..dd58d69ad 100644
--- a/testdata/ruby/dbLayoutToNetlist.rb
+++ b/testdata/ruby/dbLayoutToNetlist.rb
@@ -368,18 +368,6 @@ END
     l2n.extract_netlist
 
     assert_equal(l2n.netlist.to_s, <<END)
-circuit RINGO ();
-  subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
-  subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
-  subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
-  subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
-  subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
-  subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
-  subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
-  subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
-  subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
-  subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
-end;
 circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
   device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
   device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
@@ -392,6 +380,18 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
 end;
 circuit TRANS ($1=$1,$2=$2,$3=$3);
 end;
+circuit RINGO ();
+  subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);
+  subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);
+  subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);
+  subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);
+  subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);
+  subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);
+  subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);
+  subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);
+  subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);
+  subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);
+end;
 END
 
     # cleanup now
@@ -484,17 +484,6 @@ END
     l2n.extract_netlist
 
     assert_equal(l2n.netlist.to_s, <<END)
-circuit RINGO ();
-  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
-  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
-  subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
-  subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
-  subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
-end;
-circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
-  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
-  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
-end;
 circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
   device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
   device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
@@ -507,6 +496,17 @@ circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
 end;
 circuit TRANS ($1=$1,$2=$2,$3=$3);
 end;
+circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
+  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
+  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
+end;
+circuit RINGO ();
+  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
+  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
+  subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I17,$6=$I9,$7=VDD);
+  subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
+  subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
+end;
 END
 
     l2n.netlist.combine_devices
@@ -514,6 +514,16 @@ END
     l2n.netlist.purge
 
     assert_equal(l2n.netlist.to_s, <<END)
+circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
+  device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
+  device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
+  device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
+  device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
+end;
+circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
+  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
+  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
+end;
 circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
   subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I11,$6=OSC,$7=VDD);
   subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I17,$7=VDD);
@@ -521,16 +531,6 @@ circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);
   subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I9,$6=$I10,$7=VDD);
   subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I10,$6=$I11,$7=VDD);
 end;
-circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);
-  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);
-  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);
-end;
-circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);
-  device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
-  device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
-  device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);
-  device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);
-end;
 END
 
     # cleanup now