@@ -52,9 +52,10 @@
@@ -52,9 +52,10 @@
In SPICE, plain resistors are represented by the "R" element.
+ The API class is
@@ -71,7 +72,11 @@
bulk terminals are connected to the same net.
+ The API class of the resistor with bulk is
@@ -90,9 +95,10 @@
In SPICE, plain capacitors are represented by the "C" element.
+ The API class is
@@ -109,7 +115,11 @@
bulk terminals are connected to the same net.
+ The API class of the capacitor with bulk is
@@ -133,9 +143,10 @@
In SPICE, diodes are represented by the "D" element using the
device class name as the model name.
+ The API class is
@@ -161,7 +172,11 @@
In this case their widths, areas and perimeters will add.
+ The API class of the three-terminal MOS transistor is
@@ -182,9 +197,10 @@
In SPICE, MOS4 devices are represented by the "M" element with the
device class name as the model name.
+ The API class is
@@ -216,9 +232,10 @@
In SPICE, BJT3 devices are represented by the "Q" element with the
device class name as the model name.
+ The API class is
@@ -237,6 +254,307 @@
In SPICE, BJT4 devices are represented by the "Q" element with four nodes and the
device class name as the model name.
+ The API class is
+ The resistor extractor assumes a layout which consists of a resistor "wire" + and two caps (contacts). The wire is specified with the layer symbol "R", + the caps are specified with the layer symbol "C": +
+ +
+ 
+
+ The extractor will compute the resistance from the number of squares + and the sheet resistance. The sheet resistance needs to be given + when creating the extractor: +
+ +sheet_rho = 0.5
+model_name = "RES"
+extract_devices(resistor(model_name, sheet_rho), { "R" => res_layer, "C" => cap_layer })
+
+ + The plain resistor offers two terminals which it outputs on "tA" and "tB" terminal layers. + If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "C" layer. + respectively. +
+ +
+ 
+
+ 
+
+ For the resistor with bulk, the wire area is output on the "tW" terminal layer as + the "W" terminal: +
+ +
+ 
+
+ Capacitors are assumed to consist of two "plates" (vertical capacitors). + The plates are on layers P1 and P2. The capacitor is extracted from the area where + these two layers overlap. +
+ +
+ 
+
+ The extractor will compute the capacitance from the area of the + overlap and the capacitance per area (F/µm²) value. +
+ +area_cap = 1.5e-15
+model_name = "CAP"
+extract_devices(capacitor(model_name, area_cap), { "P1" => metal1, "P2" => metal2 })
+
+ + The plain capacitor offers two terminals which it outputs on "tA" and "tB" terminal layers. + If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "P1" and "P2" layers + respectively. +
+ +
+ 
+
+ 
+
+ For the capacitor with bulk, the capacitor area is output on the "tW" terminal layer as + the "W" terminal: +
+ +
+ 
+
+ Diodes are assumed to consist of two vertical implant regions (wells, diffusion). + One of the regions is p type ("P" layer) and the other "n" type ("N" layer). + These layers also form the anode (p) and cathode (n) of the diode. +
+ +
+ 
+
+ The extractor will compute the capacitance from the area of the + overlap and the capacitance per area (F/µm²) value. +
+ +model_name = "DIODE"
+extract_devices(diode(model_name), { "P" => pplus, "N" => nwell })
+
+ + The diode offers two terminals which it outputs on "tA" and "tC" terminal layers. + If "tA" is not specified, "A" terminals will be written on the "P" layer. + If "tC" is not specified, "C" terminals will be written on the "N" layer. +
+ +
+ 
+
+ 
+
+ MOS transistors are recognized by their gate ("G" input) and source/drain ("SD" input) regions. + Source and drain needs to be separated from the gate shape. The touching edges of gate and + source/drain regions define the width of the device, the perpendicular dimension the gate length. + Because the separation of source/drain, the computation of gates and the separation of + these for NMOS and PMOS devices, the "G" and "SD" layers are usually derived layers. + As these usually won't participate in the connectivity, it's important to specify the + "tS", "tD", "tG" and "tB" (for MOS4) layers explicitly and redirect the terminal shapes + to layers that really participate in connections. +
+ +
+ 
+
model_name = "PMOS"
+extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" => (active & poly), "W" => nwell,
+ "tS" => active, "tD" => active, "tG" => poly, "tB" => nwell })
+
+ + The MOS3 device produces three terminals which it outputs on "tS", "tG" and "tD" terminal layers (source, + gate and drain respectively): +
+ +
+ 
+
+ 
+
+ 
+
+ The MOS4 device offers one more terminal (bulk) which it writes on "tB". +
+ +
+ 
+
+ There are basically two kind of bipolar transistors: vertical and lateral ones. +
+ ++ Lateral transistors are formed by implant or diffusion wells creating a intermittent + n/p structure on the wafer. The basic recognition region is the base region. The collector + and emitter regions are inside or overlapping the base region and use the opposite doping + than base: if the base region is n doped, then + collector and emitter regions have to be p doped. The structure then forms a PNP transistor. + KLayout recognizes lateral transistors when the base is partially covered by the collector region. + For lateral transistors, the emitter is defined by the emitter region inside base. The + collector region is defined by collector inside base and outside emitter. +
+ ++ Vertical transistors are formed by a stack of n/p wells. Sometimes vertical transistors + are formed as parasitic devices in standard CMOS processes. A PNP transistor can be formed + by taking the collector as the substrate, nwell for the base and pplus implant for the emitter. + KLayout recognizes a vertical bipolar transistor when the base is covered entirely by the + collector or has no collector at all - this means the collector + region can be empty (e.g. bulk). +
+ ++ In both cases, there can be multiple emitter regions inside a base island. In this + case, one transistor is extracted for each emitter region. +
+ ++ Vertical bipolar transistors take their inputs from "B" (base), "C" (collector) + and "E" (emitter). "C" is optional: +
+ +
+ 
+
+ Especially for bipolar devices it's important to device useful terminal output + layers. Typically, the wells and diffusion areas will be connected through "contact", + (not considering the Schottky diodes for now). + So it's a good idea to send the terminals to the contact layer: +
+ +model_name = "PNP"
+extract_devices(bjt3(model_name), { "C" => collector, "B" => base, "E" => emitter,
+ "tC" => contact, "tB" => contact, "tE" => contact })
+
+ + The BJT3 device produces three terminals which it outputs on "tC", "tB" and "tE" terminal layers (collector, + base and emitter respectively): +
+ +
+ 
+
+ 
+
+ 
+
+ If the collector region is empty (e.g. p substrate), the base shape is copied to the "tC" output layer + for the collector terminal. +
+ ++ The BJT4 device offers one more terminal (substrate) which it writes on "tS". "tS" is + a copy of the emitter shape but connected to the substrate terminal: +
+ +
+ 
+
+ Lateral bipolar transistors also take their inputs from "B" (base), "C" (collector) + and "E" (emitter). For lateral transistors, "C" is not optional and must not fully cover + the base region. Apart from this, the use model for BJT3 and BJT4 extractors is + identical for vertical and lateral transistors. +
+ ++ A typical lateral transistor is formed by a collector ring and emitter + island inside the base region: +
+ +
+ 
+
+ The terminals produced by the bipolar transistor extractor in the lateral case are + the same than for the vertical case, but with a different geometry: +
+ +
+ 
+
+ 
+
+ 
+
+ Again, for BJT4, "tS" is a copy of the emitter shape but connected to the substrate terminal: +
+ +
+ 
deep@@ -188,7 +188,7 @@ compare
report_lvs
- We can also write the report to a file if we want (see ): + We can also write the report to a file if we want (see report_lvs):
report_lvs("inv.lvsdb")
@@ -214,7 +214,9 @@ metal2_lbl = labels(9, 1)
(the layout source is - as in DRC - usually the current layout).
While "input" pulls all kind of shapes, "labels" will only pull texts.
We use "labels" to pull labels for first metal from GDS layer 7, datatype 1 and
- labels for second metal from GDS layer 9, datatype 1. For details see .
+ labels for second metal from GDS layer 9, datatype 1. For details see
+ input and
+ labels.
@@ -258,7 +260,7 @@ nsd = nactive - ngate "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
- The first argument of "extract_devices" (see ) is the device extractor. + The first argument of "extract_devices" (see extract_devices) is the device extractor. The device extractor is an object responsible for the actual extraction of a certain device type. In our case the template is "MOS4" and we want to produce a new class of devices called "PMOS". mos4("PMOS") will create a new @@ -289,7 +291,8 @@ nsd = nactive - ngate "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
- Having the devices is already half the work. We now need to supply the connectivity (see ): + Having the devices is already half the work. We now need to supply the + connectivity (see connect):
connect(psd, contact) @@ -317,7 +320,7 @@ connect(metal2, metal2_lbl) # attaches labels
- Furthermore, two special connections need to be made: + Furthermore, two special connections need to be made (see connect_global):
connect_global(bulk, "SUBSTRATE") @@ -346,7 +349,7 @@ connect_global(nwell, "NWELL")
compare
- If we insert a netlist write statement (see ) at the beginning of the script, we can obtain + If we insert a netlist write statement (see target_netlist) at the beginning of the script, we can obtain a SPICE version of the extracted netlist:
diff --git a/src/lay/lay/doc/manual/mos_ex_layout.png b/src/lay/lay/doc/manual/mos_ex_layout.png new file mode 100644 index 000000000..9e84462d9 Binary files /dev/null and b/src/lay/lay/doc/manual/mos_ex_layout.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_tb.png b/src/lay/lay/doc/manual/mos_ex_tb.png new file mode 100644 index 000000000..0c0979484 Binary files /dev/null and b/src/lay/lay/doc/manual/mos_ex_tb.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_td.png b/src/lay/lay/doc/manual/mos_ex_td.png new file mode 100644 index 000000000..d723abc34 Binary files /dev/null and b/src/lay/lay/doc/manual/mos_ex_td.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_tg.png b/src/lay/lay/doc/manual/mos_ex_tg.png new file mode 100644 index 000000000..a488d7350 Binary files /dev/null and b/src/lay/lay/doc/manual/mos_ex_tg.png differ diff --git a/src/lay/lay/doc/manual/mos_ex_ts.png b/src/lay/lay/doc/manual/mos_ex_ts.png new file mode 100644 index 000000000..9f459cfeb Binary files /dev/null and b/src/lay/lay/doc/manual/mos_ex_ts.png differ diff --git a/src/lay/lay/doc/manual/res_ex_layout.png b/src/lay/lay/doc/manual/res_ex_layout.png new file mode 100644 index 000000000..4b16e19ff Binary files /dev/null and b/src/lay/lay/doc/manual/res_ex_layout.png differ diff --git a/src/lay/lay/doc/manual/res_ex_ta.png b/src/lay/lay/doc/manual/res_ex_ta.png new file mode 100644 index 000000000..971633c59 Binary files /dev/null and b/src/lay/lay/doc/manual/res_ex_ta.png differ diff --git a/src/lay/lay/doc/manual/res_ex_tb.png b/src/lay/lay/doc/manual/res_ex_tb.png new file mode 100644 index 000000000..e25fdce18 Binary files /dev/null and b/src/lay/lay/doc/manual/res_ex_tb.png differ diff --git a/src/lay/lay/doc/manual/res_ex_tw.png b/src/lay/lay/doc/manual/res_ex_tw.png new file mode 100644 index 000000000..706b39b5b Binary files /dev/null and b/src/lay/lay/doc/manual/res_ex_tw.png differ diff --git a/src/lay/lay/layHelpResources.qrc b/src/lay/lay/layHelpResources.qrc index 3bb34f248..b0c2118e8 100644 --- a/src/lay/lay/layHelpResources.qrc +++ b/src/lay/lay/layHelpResources.qrc @@ -189,6 +189,32 @@