From d7eb9162ce26fbdc691d1c12fa5e1f32bd52a329 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Mon, 18 Mar 2019 19:28:20 +0100 Subject: [PATCH] WIP: unified to_string/to_parsable_string of db::Netlist, step 1 --- src/db/db/dbNetlist.cc | 21 +- src/db/db/dbNetlist.h | 2 +- src/db/db/gsiDeclDbNetlist.cc | 2 +- src/db/unit_tests/dbLayoutToNetlistTests.cc | 455 ++++++++++-------- .../unit_tests/dbNetlistDeviceClassesTests.cc | 436 +++++++++-------- src/db/unit_tests/dbNetlistExtractorTests.cc | 253 +++++----- src/db/unit_tests/dbNetlistTests.cc | 28 +- 7 files changed, 654 insertions(+), 543 deletions(-) diff --git a/src/db/db/dbNetlist.cc b/src/db/db/dbNetlist.cc index 198364bbf..937128f0b 100644 --- a/src/db/db/dbNetlist.cc +++ b/src/db/db/dbNetlist.cc @@ -486,7 +486,7 @@ static std::string pin2string (const db::Pin &pin) } } -std::string Netlist::to_string () const +std::string Netlist::to_string_old () const { std::string res; for (db::Netlist::const_circuit_iterator c = begin_circuits (); c != end_circuits (); ++c) { @@ -559,14 +559,14 @@ std::string Netlist::to_parsable_string () const ps += pin2string (*p) + "=" + net2string (c->net_for_pin (p->id ())); } - res += std::string ("circuit ") + c->name () + " (" + ps + ");\n"; + res += std::string ("circuit ") + tl::to_word_or_quoted_string (c->name ()) + " (" + ps + ");\n"; for (db::Circuit::const_device_iterator d = c->begin_devices (); d != c->end_devices (); ++d) { std::string ts; const std::vector &td = d->device_class ()->terminal_definitions (); for (std::vector::const_iterator t = td.begin (); t != td.end (); ++t) { if (t != td.begin ()) { - ts += ", "; + ts += ","; } ts += t->name () + "=" + net2string (d->net_for_terminal (t->id ())); } @@ -587,9 +587,9 @@ std::string Netlist::to_parsable_string () const const db::Circuit *circuit = sc->circuit_ref (); for (db::Circuit::const_pin_iterator p = circuit->begin_pins (); p != circuit->end_pins (); ++p) { if (p != circuit->begin_pins ()) { - ps += ", "; + ps += ","; } - ps += net2string (subcircuit.net_for_pin (p->id ())); + ps += pin2string (*p) + "=" + net2string (subcircuit.net_for_pin (p->id ())); } res += std::string (" subcircuit ") + tl::to_word_or_quoted_string (circuit->name ()) + " " + subcircuit2string (*sc) + " (" + ps + ");\n"; } @@ -799,11 +799,18 @@ static void read_subcircuit_pins (tl::Extractor &ex, db::SubCircuit *subcircuit, ex.expect ("("); while (! ex.test (")")) { + std::string pn; + ex.read_word_or_quoted (pn); + + ex.expect ("="); + if (pi == circuit->end_pins ()) { // add a dummy pin - circuit->add_pin (std::string ()); + circuit->add_pin (pn); pi = circuit->end_pins (); --pi; + } else if (pi->name () != pn) { + ex.error (tl::to_string (tr ("Expected pin with name: ")) + pi->name ()); } ex.expect_more (); @@ -820,7 +827,7 @@ static void read_subcircuit_pins (tl::Extractor &ex, db::SubCircuit *subcircuit, } if (pi != circuit->end_pins ()) { - // @@@ ex.error (tl::to_string (tr ("Too few pins in subcircuit call"))); + ex.error (tl::to_string (tr ("Too few pins in subcircuit call"))); } } diff --git a/src/db/db/dbNetlist.h b/src/db/db/dbNetlist.h index fab9c79f9..b563aa493 100644 --- a/src/db/db/dbNetlist.h +++ b/src/db/db/dbNetlist.h @@ -92,7 +92,7 @@ public: * * This method is basically intended to testing. */ - std::string to_string () const; + std::string to_string_old () const; /** * @brief Returns a parsable string representation of the netlist diff --git a/src/db/db/gsiDeclDbNetlist.cc b/src/db/db/gsiDeclDbNetlist.cc index 0b5b4d0d8..9c8e0ac9f 100644 --- a/src/db/db/gsiDeclDbNetlist.cc +++ b/src/db/db/gsiDeclDbNetlist.cc @@ -972,7 +972,7 @@ Class decl_dbNetlist ("db", "Netlist", gsi::iterator ("each_device_class", (db::Netlist::device_class_iterator (db::Netlist::*) ()) &db::Netlist::begin_device_classes, (db::Netlist::device_class_iterator (db::Netlist::*) ()) &db::Netlist::end_device_classes, "@brief Iterates over the device classes of the netlist" ) + - gsi::method ("to_s", &db::Netlist::to_string, + gsi::method ("to_s", &db::Netlist::to_parsable_string, "@brief Converts the netlist to a string representation.\n" "This method is intended for test purposes mainly." ) + diff --git a/src/db/unit_tests/dbLayoutToNetlistTests.cc b/src/db/unit_tests/dbLayoutToNetlistTests.cc index 730d31ae0..54ce41d6a 100644 --- a/src/db/unit_tests/dbLayoutToNetlistTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistTests.cc @@ -337,28 +337,31 @@ TEST(1_BasicExtraction) db::compare_layouts (_this, ly, au); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO ():\n" - " XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)\n" - " XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD)\n" - " XINV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD)\n" - " XINV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD)\n" - " XINV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD)\n" - " XINV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD)\n" - " XINV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD)\n" - " XINV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD)\n" - " XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)\n" - " XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " XTRANS $1 ($1=$2,$2=$4,$3=IN)\n" - " XTRANS $2 ($1=$2,$2=$5,$3=IN)\n" - " XTRANS $3 ($1=$5,$2=OUT,$3=$2)\n" - " XTRANS $4 ($1=$4,$2=OUT,$3=$2)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n" + " subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n" + " subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n" + " subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // do some probing before purging @@ -492,23 +495,25 @@ TEST(1_BasicExtraction) l2n.netlist ()->purge (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD):\n" - " XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)\n" - " XINV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD)\n" - " XINV2 $3 (IN=$I19,$2=(null),OUT=$I1,$4=VSS,$5=VDD)\n" - " XINV2 $4 (IN=$I1,$2=(null),OUT=$I2,$4=VSS,$5=VDD)\n" - " XINV2 $5 (IN=$I2,$2=(null),OUT=$I3,$4=VSS,$5=VDD)\n" - " XINV2 $6 (IN=$I3,$2=(null),OUT=$I4,$4=VSS,$5=VDD)\n" - " XINV2 $7 (IN=$I4,$2=(null),OUT=$I5,$4=VSS,$5=VDD)\n" - " XINV2 $8 (IN=$I5,$2=(null),OUT=$I6,$4=VSS,$5=VDD)\n" - " XINV2 $9 (IN=$I6,$2=(null),OUT=$I7,$4=VSS,$5=VDD)\n" - " XINV2 $10 (IN=$I7,$2=(null),OUT=$I8,$4=VSS,$5=VDD)\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=(null),OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=(null),OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=(null),OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=(null),OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=(null),OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=(null),OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=(null),OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // do some probing after purging @@ -684,26 +689,30 @@ TEST(2_Probing) dump_recursive_nets_to_layout (l2n, ly, dump_map, cm); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO ():\n" - " XINV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC)\n" - " XINV2PAIR $2 ($1=$I18,$2=VDD,$3=VSS,$4=FB,$5=$I9)\n" - " XINV2PAIR $3 ($1=$I19,$2=VDD,$3=VSS,$4=$I9,$5=$I1)\n" - " XINV2PAIR $4 ($1=$I20,$2=VDD,$3=VSS,$4=$I1,$5=$I2)\n" - " XINV2PAIR $5 ($1=$I21,$2=VDD,$3=VSS,$4=$I2,$5=$I3)\n" - "Circuit INV2PAIR ($1=$I7,$2=$I5,$3=$I4,$4=$I2,$5=$I1):\n" - " XINV2 $1 (IN=$I3,$2=$I7,OUT=$I1,$4=$I4,$5=$I5)\n" - " XINV2 $2 (IN=$I2,$2=$I6,OUT=$I3,$4=$I4,$5=$I5)\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " XTRANS $1 ($1=$2,$2=$4,$3=IN)\n" - " XTRANS $2 ($1=$2,$2=$5,$3=IN)\n" - " XTRANS $3 ($1=$5,$2=OUT,$3=$2)\n" - " XTRANS $4 ($1=$4,$2=OUT,$3=$2)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC);\n" + " subcircuit INV2PAIR $2 ($1=$I18,$2=VDD,$3=VSS,$4=FB,$5=$I9);\n" + " subcircuit INV2PAIR $3 ($1=$I19,$2=VDD,$3=VSS,$4=$I9,$5=$I1);\n" + " subcircuit INV2PAIR $4 ($1=$I20,$2=VDD,$3=VSS,$4=$I1,$5=$I2);\n" + " subcircuit INV2PAIR $5 ($1=$I21,$2=VDD,$3=VSS,$4=$I2,$5=$I3);\n" + "end;\n" + "circuit INV2PAIR ($1=$I7,$2=$I5,$3=$I4,$4=$I2,$5=$I1);\n" + " subcircuit INV2 $1 (IN=$I3,$2=$I7,OUT=$I1,$4=$I4,$5=$I5);\n" + " subcircuit INV2 $2 (IN=$I2,$2=$I6,OUT=$I3,$4=$I4,$5=$I5);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n" + " subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n" + " subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n" + " subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // compare the collected test data @@ -736,21 +745,24 @@ TEST(2_Probing) l2n.netlist ()->purge (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD):\n" - " XINV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC)\n" - " XINV2PAIR $2 ($1=(null),$2=VDD,$3=VSS,$4=FB,$5=$I9)\n" - " XINV2PAIR $3 ($1=(null),$2=VDD,$3=VSS,$4=$I9,$5=$I1)\n" - " XINV2PAIR $4 ($1=(null),$2=VDD,$3=VSS,$4=$I1,$5=$I2)\n" - " XINV2PAIR $5 ($1=(null),$2=VDD,$3=VSS,$4=$I2,$5=$I3)\n" - "Circuit INV2PAIR ($1=$I7,$2=$I5,$3=$I4,$4=$I2,$5=$I1):\n" - " XINV2 $1 (IN=$I3,$2=$I7,OUT=$I1,$4=$I4,$5=$I5)\n" - " XINV2 $2 (IN=$I2,$2=(null),OUT=$I3,$4=$I4,$5=$I5)\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n" + " subcircuit INV2PAIR $1 ($1=FB,$2=VDD,$3=VSS,$4=$I3,$5=OSC);\n" + " subcircuit INV2PAIR $2 ($1=(null),$2=VDD,$3=VSS,$4=FB,$5=$I9);\n" + " subcircuit INV2PAIR $3 ($1=(null),$2=VDD,$3=VSS,$4=$I9,$5=$I1);\n" + " subcircuit INV2PAIR $4 ($1=(null),$2=VDD,$3=VSS,$4=$I1,$5=$I2);\n" + " subcircuit INV2PAIR $5 ($1=(null),$2=VDD,$3=VSS,$4=$I2,$5=$I3);\n" + "end;\n" + "circuit INV2PAIR ($1=$I7,$2=$I5,$3=$I4,$4=$I2,$5=$I1);\n" + " subcircuit INV2 $1 (IN=$I3,$2=$I7,OUT=$I1,$4=$I4,$5=$I5);\n" + " subcircuit INV2 $2 (IN=$I2,$2=(null),OUT=$I3,$4=$I4,$5=$I5);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // do some probing after purging @@ -956,26 +968,30 @@ TEST(3_GlobalNetConnections) dump_recursive_nets_to_layout (l2n, ly, dump_map, cm); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO ():\n" - " XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)\n" - " XINV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)\n" - " XINV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)\n" - " XINV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)\n" - " XINV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)\n" - "Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):\n" - " XINV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)\n" - " XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)\n" - "Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):\n" - " DPMOS $1 (S=$3,G=IN,D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=VDD,G=$3,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$3,G=IN,D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=VSS,G=$3,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " XTRANS $1 ($1=$3,$2=VSS,$3=IN)\n" - " XTRANS $2 ($1=$3,$2=VDD,$3=IN)\n" - " XTRANS $3 ($1=VDD,$2=OUT,$3=$3)\n" - " XTRANS $4 ($1=VSS,$2=OUT,$3=$3)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD);\n" + "end;\n" + "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" + "end;\n" + "circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n" + " device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$3,$2=VSS,$3=IN);\n" + " subcircuit TRANS $2 ($1=$3,$2=VDD,$3=IN);\n" + " subcircuit TRANS $3 ($1=VDD,$2=OUT,$3=$3);\n" + " subcircuit TRANS $4 ($1=VSS,$2=OUT,$3=$3);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // compare the collected test data @@ -1008,21 +1024,24 @@ TEST(3_GlobalNetConnections) l2n.netlist ()->purge (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS'):\n" - " XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)\n" - " XINV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)\n" - " XINV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)\n" - " XINV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)\n" - " XINV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)\n" - "Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):\n" - " XINV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)\n" - " XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)\n" - "Circuit INV2 ($1=(null),IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=(null)):\n" - " DPMOS $1 (S=$3,G=IN,D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=VDD,G=$3,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$3,G=IN,D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=VSS,G=$3,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');\n" + " subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD);\n" + "end;\n" + "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" + "end;\n" + "circuit INV2 ($1=(null),IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=(null));\n" + " device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // do some probing after purging @@ -1234,26 +1253,30 @@ TEST(4_GlobalNetDeviceExtraction) dump_recursive_nets_to_layout (l2n, ly, dump_map, cm); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO ():\n" - " XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)\n" - " XINV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)\n" - " XINV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)\n" - " XINV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)\n" - " XINV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)\n" - "Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):\n" - " XINV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)\n" - " XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)\n" - "Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):\n" - " DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " XTRANS $1 ($1=$3,$2=VSS,$3=IN)\n" - " XTRANS $2 ($1=$3,$2=VDD,$3=IN)\n" - " XTRANS $3 ($1=VDD,$2=OUT,$3=$3)\n" - " XTRANS $4 ($1=VSS,$2=OUT,$3=$3)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=$I22,$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=$I23,$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=$I24,$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=$I25,$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD);\n" + "end;\n" + "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" + "end;\n" + "circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n" + " device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$3,$2=VSS,$3=IN);\n" + " subcircuit TRANS $2 ($1=$3,$2=VDD,$3=IN);\n" + " subcircuit TRANS $3 ($1=VDD,$2=OUT,$3=$3);\n" + " subcircuit TRANS $4 ($1=VSS,$2=OUT,$3=$3);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // compare the collected test data @@ -1286,21 +1309,24 @@ TEST(4_GlobalNetDeviceExtraction) l2n.netlist ()->purge (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS'):\n" - " XINV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD)\n" - " XINV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD)\n" - " XINV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD)\n" - " XINV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD)\n" - " XINV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD)\n" - "Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):\n" - " XINV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)\n" - " XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)\n" - "Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):\n" - " DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');\n" + " subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=FB,$3=VDD,$4='BULK,VSS',$5=$I7,$6=OSC,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=(null),$3=VDD,$4='BULK,VSS',$5=$I6,$6=$I7,$7=VDD);\n" + "end;\n" + "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" + "end;\n" + "circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n" + " device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=VDD,G=$3,D=OUT,B=$1) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$3,G=IN,D=VSS,B=BULK) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // do some probing after purging @@ -1512,26 +1538,30 @@ TEST(5_DeviceExtractionWithDeviceCombination) dump_recursive_nets_to_layout (l2n, ly, dump_map, cm); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO ():\n" - " XINV2PAIR $1 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=FB,$5=$I7,$6=OSC,$7=VDD)\n" - " XINV2PAIR $2 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I22,$5=FB,$6=$I13,$7=VDD)\n" - " XINV2PAIR $3 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I23,$5=$I13,$6=$I5,$7=VDD)\n" - " XINV2PAIR $4 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I24,$5=$I5,$6=$I6,$7=VDD)\n" - " XINV2PAIR $5 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I25,$5=$I6,$6=$I7,$7=VDD)\n" - "Circuit INV2PAIR (BULK=BULK,$2=$I6,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1):\n" - " XINV2 $1 ($1=$I1,IN=$I3,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)\n" - " XINV2 $2 ($1=$I1,IN=$I4,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)\n" - "Circuit INV2 ($1=$1,IN=IN,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):\n" - " DPMOS $1 (S=OUT,G=IN,D=VDD,B=$1) [L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3]\n" - " DPMOS $2 (S=VDD,G=IN,D=OUT,B=$1) [L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55]\n" - " DNMOS $3 (S=OUT,G=IN,D=VSS,B=BULK) [L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3]\n" - " DNMOS $4 (S=VSS,G=IN,D=OUT,B=BULK) [L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55]\n" - " XTRANS $1 ($1=OUT,$2=VSS,$3=IN)\n" - " XTRANS $2 ($1=OUT,$2=VDD,$3=IN)\n" - " XTRANS $3 ($1=OUT,$2=VSS,$3=IN)\n" - " XTRANS $4 ($1=OUT,$2=VDD,$3=IN)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=FB,$5=$I7,$6=OSC,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I22,$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I23,$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I24,$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=$I25,$5=$I6,$6=$I7,$7=VDD);\n" + "end;\n" + "circuit INV2PAIR (BULK=BULK,$2=$I6,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $2 ($1=$I1,IN=$I4,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" + "end;\n" + "circuit INV2 ($1=$1,IN=IN,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n" + " device PMOS $1 (S=OUT,G=IN,D=VDD,B=$1) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $2 (S=VDD,G=IN,D=OUT,B=$1) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $3 (S=OUT,G=IN,D=VSS,B=BULK) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $4 (S=VSS,G=IN,D=OUT,B=BULK) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " subcircuit TRANS $1 ($1=OUT,$2=VSS,$3=IN);\n" + " subcircuit TRANS $2 ($1=OUT,$2=VDD,$3=IN);\n" + " subcircuit TRANS $3 ($1=OUT,$2=VSS,$3=IN);\n" + " subcircuit TRANS $4 ($1=OUT,$2=VDD,$3=IN);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // compare the collected test data @@ -1561,19 +1591,22 @@ TEST(5_DeviceExtractionWithDeviceCombination) l2n.netlist ()->purge (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS'):\n" - " XINV2PAIR $1 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=FB,$5=$I7,$6=OSC,$7=VDD)\n" - " XINV2PAIR $2 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=FB,$6=$I13,$7=VDD)\n" - " XINV2PAIR $3 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=$I13,$6=$I5,$7=VDD)\n" - " XINV2PAIR $4 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=$I5,$6=$I6,$7=VDD)\n" - " XINV2PAIR $5 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=$I6,$6=$I7,$7=VDD)\n" - "Circuit INV2PAIR (BULK=BULK,$2=$I6,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1):\n" - " XINV2 $1 ($1=$I1,IN=$I3,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)\n" - " XINV2 $2 ($1=$I1,IN=$I4,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)\n" - "Circuit INV2 ($1=$1,IN=IN,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):\n" - " DPMOS $1 (S=OUT,G=IN,D=VDD,B=$1) [L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85]\n" - " DNMOS $3 (S=OUT,G=IN,D=VSS,B=BULK) [L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,'BULK,VSS'='BULK,VSS');\n" + " subcircuit INV2PAIR $1 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=FB,$5=$I7,$6=OSC,$7=VDD);\n" + " subcircuit INV2PAIR $2 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=FB,$6=$I13,$7=VDD);\n" + " subcircuit INV2PAIR $3 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=$I13,$6=$I5,$7=VDD);\n" + " subcircuit INV2PAIR $4 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=$I5,$6=$I6,$7=VDD);\n" + " subcircuit INV2PAIR $5 (BULK='BULK,VSS',$2=VDD,$3='BULK,VSS',$4=(null),$5=$I6,$6=$I7,$7=VDD);\n" + "end;\n" + "circuit INV2PAIR (BULK=BULK,$2=$I6,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1);\n" + " subcircuit INV2 $1 ($1=$I1,IN=$I3,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n" + " subcircuit INV2 $2 ($1=$I1,IN=$I4,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n" + "end;\n" + "circuit INV2 ($1=$1,IN=IN,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n" + " device PMOS $1 (S=OUT,G=IN,D=VDD,B=$1) (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n" + " device NMOS $3 (S=OUT,G=IN,D=VSS,B=BULK) (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n" + "end;\n" ); // do some probing after purging @@ -1732,14 +1765,15 @@ TEST(6_MoreDeviceTypes) l2n.extract_netlist (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit TOP ():\n" - " DHVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) [L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4]\n" - " DHVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) [L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8]\n" - " DLVPMOS $3 (S=$10,G=A,D=$6,B=$9) [L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5]\n" - " DHVNMOS $4 (S=Z,G=$6,D=VSS,B=BULK) [L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6]\n" - " DHVNMOS $5 (S=VSS,G=A,D=$5,B=BULK) [L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2]\n" - " DLVNMOS $6 (S=VSS,G=A,D=$6,B=BULK) [L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit TOP ();\n" + " device HVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n" + " device HVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n" + " device LVPMOS $3 (S=$10,G=A,D=$6,B=$9) (L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5);\n" + " device HVNMOS $4 (S=Z,G=$6,D=VSS,B=BULK) (L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6);\n" + " device HVNMOS $5 (S=VSS,G=A,D=$5,B=BULK) (L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2);\n" + " device LVNMOS $6 (S=VSS,G=A,D=$6,B=BULK) (L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89);\n" + "end;\n" ); } @@ -1887,14 +1921,15 @@ TEST(7_MoreByEmptyDeviceTypes) l2n.extract_netlist (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit TOP ():\n" - " DLVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) [L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4]\n" - " DLVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) [L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8]\n" - " DLVPMOS $3 (S=$10,G=A,D=$6,B=$9) [L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5]\n" - " DLVNMOS $4 (S=VSS,G=A,D=$6,B=BULK) [L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89]\n" - " DLVNMOS $5 (S=Z,G=$6,D=VSS,B=BULK) [L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6]\n" - " DLVNMOS $6 (S=VSS,G=A,D=$5,B=BULK) [L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit TOP ();\n" + " device LVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n" + " device LVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n" + " device LVPMOS $3 (S=$10,G=A,D=$6,B=$9) (L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5);\n" + " device LVNMOS $4 (S=VSS,G=A,D=$6,B=BULK) (L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89);\n" + " device LVNMOS $5 (S=Z,G=$6,D=VSS,B=BULK) (L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6);\n" + " device LVNMOS $6 (S=VSS,G=A,D=$5,B=BULK) (L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2);\n" + "end;\n" ); } @@ -2064,14 +2099,15 @@ TEST(8_FlatExtraction) l2n.extract_netlist (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit TOP ():\n" - " DHVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) [L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4]\n" - " DHVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) [L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8]\n" - " DLVPMOS $3 (S=$10,G=A,D=$6,B=$9) [L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5]\n" - " DHVNMOS $4 (S=Z,G=$6,D=VSS,B=BULK) [L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6]\n" - " DHVNMOS $5 (S=VSS,G=A,D=$5,B=BULK) [L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2]\n" - " DLVNMOS $6 (S=VSS,G=A,D=$6,B=BULK) [L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit TOP ();\n" + " device HVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n" + " device HVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n" + " device LVPMOS $3 (S=$10,G=A,D=$6,B=$9) (L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5);\n" + " device HVNMOS $4 (S=Z,G=$6,D=VSS,B=BULK) (L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6);\n" + " device HVNMOS $5 (S=VSS,G=A,D=$5,B=BULK) (L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2);\n" + " device LVNMOS $6 (S=VSS,G=A,D=$6,B=BULK) (L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89);\n" + "end;\n" ); } @@ -2246,14 +2282,15 @@ TEST(9_FlatExtractionWithExternalDSS) l2n.extract_netlist (); // compare netlist as string - EXPECT_EQ (l2n.netlist ()->to_string (), - "Circuit TOP ():\n" - " DLVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) [L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4]\n" - " DLVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) [L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8]\n" - " DLVPMOS $3 (S=$10,G=A,D=$6,B=$9) [L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5]\n" - " DLVNMOS $4 (S=VSS,G=A,D=$6,B=BULK) [L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89]\n" - " DLVNMOS $5 (S=Z,G=$6,D=VSS,B=BULK) [L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6]\n" - " DLVNMOS $6 (S=VSS,G=A,D=$5,B=BULK) [L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2]\n" + EXPECT_EQ (l2n.netlist ()->to_parsable_string (), + "circuit TOP ();\n" + " device LVPMOS $1 (S=Z,G=$5,D=VDD2,B=$8) (L=1.5,W=4.05,AS=5.4675,AD=2.73375,PS=10.8,PD=5.4);\n" + " device LVPMOS $2 (S=VDD2,G=Z,D=$5,B=$8) (L=1.5,W=4.05,AS=2.73375,AD=5.4675,PS=5.4,PD=10.8);\n" + " device LVPMOS $3 (S=$10,G=A,D=$6,B=$9) (L=1.5,W=2.475,AS=1.11375,AD=3.155625,PS=5.85,PD=7.5);\n" + " device LVNMOS $4 (S=VSS,G=A,D=$6,B=BULK) (L=1.2,W=1.7,AS=2.346,AD=2.1165,PS=6.16,PD=5.89);\n" + " device LVNMOS $5 (S=Z,G=$6,D=VSS,B=BULK) (L=1.5,W=5.25,AS=7.0875,AD=3.54375,PS=13.2,PD=6.6);\n" + " device LVNMOS $6 (S=VSS,G=A,D=$5,B=BULK) (L=1.5,W=5.25,AS=3.54375,AD=7.0875,PS=6.6,PD=13.2);\n" + "end;\n" ); } diff --git a/src/db/unit_tests/dbNetlistDeviceClassesTests.cc b/src/db/unit_tests/dbNetlistDeviceClassesTests.cc index 095541605..a61bd37bb 100644 --- a/src/db/unit_tests/dbNetlistDeviceClassesTests.cc +++ b/src/db/unit_tests/dbNetlistDeviceClassesTests.cc @@ -64,18 +64,20 @@ TEST(1_SerialResistors) r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n1,B=n2) [R=1]\n" - " D r2 (A=n2,B=n3) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n1,B=n2) (R=1);\n" + " device '' r2 (A=n2,B=n3) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n1,B=n3) [R=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n1,B=n3) (R=4);\n" + "end;\n" ); } @@ -115,18 +117,20 @@ TEST(2_SerialResistors1Swapped) r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n1,B=n2) [R=1]\n" - " D r2 (A=n3,B=n2) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n1,B=n2) (R=1);\n" + " device '' r2 (A=n3,B=n2) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n1,B=n3) [R=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n1,B=n3) (R=4);\n" + "end;\n" ); } @@ -166,18 +170,20 @@ TEST(3_SerialResistors1OtherSwapped) r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n2,B=n1) [R=1]\n" - " D r2 (A=n2,B=n3) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n2,B=n1) (R=1);\n" + " device '' r2 (A=n2,B=n3) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n3,B=n1) [R=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n3,B=n1) (R=4);\n" + "end;\n" ); } @@ -217,18 +223,20 @@ TEST(4_SerialResistors2Swapped) r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n2,B=n1) [R=1]\n" - " D r2 (A=n3,B=n2) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n2,B=n1) (R=1);\n" + " device '' r2 (A=n3,B=n2) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D r1 (A=n3,B=n1) [R=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' r1 (A=n3,B=n1) (R=4);\n" + "end;\n" ); } @@ -270,19 +278,21 @@ TEST(5_SerialResistorsNoCombination) r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3,C=n2):\n" - " D r1 (A=n1,B=n2) [R=1]\n" - " D r2 (A=n2,B=n3) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3,C=n2);\n" + " device '' r1 (A=n1,B=n2) (R=1);\n" + " device '' r2 (A=n2,B=n3) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3,C=n2):\n" - " D r1 (A=n1,B=n2) [R=1]\n" - " D r2 (A=n2,B=n3) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3,C=n2);\n" + " device '' r1 (A=n1,B=n2) (R=1);\n" + " device '' r2 (A=n2,B=n3) (R=3);\n" + "end;\n" ); } @@ -319,18 +329,20 @@ TEST(6_ParallelResistors) r1->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2); r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n1,B=n2) [R=2]\n" - " D r2 (A=n1,B=n2) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n1,B=n2) (R=2);\n" + " device '' r2 (A=n1,B=n2) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n1,B=n2) [R=1.2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n1,B=n2) (R=1.2);\n" + "end;\n" ); } @@ -367,18 +379,20 @@ TEST(7_ParallelResistors1Swapped) r1->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2); r2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n2,B=n1) [R=2]\n" - " D r2 (A=n1,B=n2) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n2,B=n1) (R=2);\n" + " device '' r2 (A=n1,B=n2) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n2,B=n1) [R=1.2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n2,B=n1) (R=1.2);\n" + "end;\n" ); } @@ -415,18 +429,20 @@ TEST(8_ParallelResistors1OtherSwapped) r1->connect_terminal (db::DeviceClassResistor::terminal_id_B, n2); r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n1,B=n2) [R=2]\n" - " D r2 (A=n2,B=n1) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n1,B=n2) (R=2);\n" + " device '' r2 (A=n2,B=n1) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n1,B=n2) [R=1.2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n1,B=n2) (R=1.2);\n" + "end;\n" ); } @@ -463,18 +479,20 @@ TEST(9_ParallelResistors2Swapped) r1->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2); r2->connect_terminal (db::DeviceClassResistor::terminal_id_A, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n2,B=n1) [R=2]\n" - " D r2 (A=n2,B=n1) [R=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n2,B=n1) (R=2);\n" + " device '' r2 (A=n2,B=n1) (R=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D r1 (A=n2,B=n1) [R=1.2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' r1 (A=n2,B=n1) (R=1.2);\n" + "end;\n" ); } @@ -536,20 +554,22 @@ TEST(10_ComplexRegistorCombination) circuit->connect_pin (pin_b.id (), n4); r4->connect_terminal (db::DeviceClassResistor::terminal_id_B, n4); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n4):\n" - " D r1 (A=n1,B=n2) [R=1]\n" - " D r2 (A=n2,B=n3) [R=1]\n" - " D r3 (A=n1,B=n3) [R=3]\n" - " D r4 (A=n3,B=n4) [R=0.8]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n4);\n" + " device '' r1 (A=n1,B=n2) (R=1);\n" + " device '' r2 (A=n2,B=n3) (R=1);\n" + " device '' r3 (A=n1,B=n3) (R=3);\n" + " device '' r4 (A=n3,B=n4) (R=0.8);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n4):\n" - " D r4 (A=n1,B=n4) [R=2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n4);\n" + " device '' r4 (A=n1,B=n4) (R=2);\n" + "end;\n" ); } @@ -589,18 +609,20 @@ TEST(11_SerialInductors) l2->connect_terminal (db::DeviceClassResistor::terminal_id_B, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D l1 (A=n1,B=n2) [L=1]\n" - " D l2 (A=n2,B=n3) [L=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' l1 (A=n1,B=n2) (L=1);\n" + " device '' l2 (A=n2,B=n3) (L=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D l1 (A=n1,B=n3) [L=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' l1 (A=n1,B=n3) (L=4);\n" + "end;\n" ); } @@ -637,18 +659,20 @@ TEST(12_ParallelInductors) l1->connect_terminal (db::DeviceClassInductor::terminal_id_B, n2); l2->connect_terminal (db::DeviceClassInductor::terminal_id_B, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D l1 (A=n1,B=n2) [L=2]\n" - " D l2 (A=n1,B=n2) [L=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' l1 (A=n1,B=n2) (L=2);\n" + " device '' l2 (A=n1,B=n2) (L=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D l1 (A=n1,B=n2) [L=1.2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' l1 (A=n1,B=n2) (L=1.2);\n" + "end;\n" ); } @@ -688,18 +712,20 @@ TEST(13_SerialCapacitors) c2->connect_terminal (db::DeviceClassCapacitor::terminal_id_B, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D c1 (A=n1,B=n2) [C=2]\n" - " D c2 (A=n2,B=n3) [C=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' c1 (A=n1,B=n2) (C=2);\n" + " device '' c2 (A=n2,B=n3) (C=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D c1 (A=n1,B=n3) [C=1.2]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' c1 (A=n1,B=n3) (C=1.2);\n" + "end;\n" ); } @@ -736,18 +762,20 @@ TEST(14_ParallelCapacitors) c1->connect_terminal (db::DeviceClassCapacitor::terminal_id_B, n2); c2->connect_terminal (db::DeviceClassCapacitor::terminal_id_B, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D c1 (A=n1,B=n2) [C=1]\n" - " D c2 (A=n1,B=n2) [C=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' c1 (A=n1,B=n2) (C=1);\n" + " device '' c2 (A=n1,B=n2) (C=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D c1 (A=n1,B=n2) [C=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' c1 (A=n1,B=n2) (C=4);\n" + "end;\n" ); } @@ -787,10 +815,11 @@ TEST(15_SerialDiodes) d2->connect_terminal (db::DeviceClassDiode::terminal_id_C, n3); circuit->connect_pin (pin_b.id (), n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D d1 (A=n1,C=n2) [A=2]\n" - " D d2 (A=n2,C=n3) [A=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' d1 (A=n1,C=n2) (A=2);\n" + " device '' d2 (A=n2,C=n3) (A=3);\n" + "end;\n" ); nl.combine_devices (); @@ -798,10 +827,11 @@ TEST(15_SerialDiodes) // serial diodes are not combined! - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n3):\n" - " D d1 (A=n1,C=n2) [A=2]\n" - " D d2 (A=n2,C=n3) [A=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n3);\n" + " device '' d1 (A=n1,C=n2) (A=2);\n" + " device '' d2 (A=n2,C=n3) (A=3);\n" + "end;\n" ); } @@ -838,18 +868,20 @@ TEST(16_ParallelDiodes) d1->connect_terminal (db::DeviceClassDiode::terminal_id_C, n2); d2->connect_terminal (db::DeviceClassDiode::terminal_id_C, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D d1 (A=n1,C=n2) [A=1]\n" - " D d2 (A=n1,C=n2) [A=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' d1 (A=n1,C=n2) (A=1);\n" + " device '' d2 (A=n1,C=n2) (A=3);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D d1 (A=n1,C=n2) [A=4]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' d1 (A=n1,C=n2) (A=4);\n" + "end;\n" ); } @@ -886,10 +918,11 @@ TEST(17_AntiParallelDiodes) d1->connect_terminal (db::DeviceClassDiode::terminal_id_C, n2); d2->connect_terminal (db::DeviceClassDiode::terminal_id_A, n2); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D d1 (A=n1,C=n2) [A=1]\n" - " D d2 (A=n2,C=n1) [A=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' d1 (A=n1,C=n2) (A=1);\n" + " device '' d2 (A=n2,C=n1) (A=3);\n" + "end;\n" ); nl.combine_devices (); @@ -897,10 +930,11 @@ TEST(17_AntiParallelDiodes) // anti-parallel diodes are not combined - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2):\n" - " D d1 (A=n1,C=n2) [A=1]\n" - " D d2 (A=n2,C=n1) [A=3]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2);\n" + " device '' d1 (A=n1,C=n2) (A=1);\n" + " device '' d2 (A=n2,C=n1) (A=3);\n" + "end;\n" ); } @@ -954,18 +988,20 @@ TEST(20_ParallelMOS3Transistors) d1->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3); d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=3,AS=5,AD=7,PS=25,PD=27]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n" + "end;\n" ); } @@ -1019,18 +1055,20 @@ TEST(21_AntiParallelMOS3Transistors) d1->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3); d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n2,G=n3,D=n1) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n2,G=n3,D=n1) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=3,AS=5,AD=7,PS=25,PD=27]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n" + "end;\n" ); } @@ -1089,10 +1127,11 @@ TEST(22_ParallelMOS3TransistorsDisconnectedGates) circuit->connect_pin (pin_c2.id (), n4); d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n4); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C1=n3,C2=n4):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n4,D=n2) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C1=n3,C2=n4);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n4,D=n2) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); @@ -1100,10 +1139,11 @@ TEST(22_ParallelMOS3TransistorsDisconnectedGates) // because of the disconnected gates, devices will no be joined: - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C1=n3,C2=n4):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n4,D=n2) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C1=n3,C2=n4);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n4,D=n2) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); } @@ -1157,10 +1197,11 @@ TEST(23_ParallelMOS3TransistorsDifferentLength) d1->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3); d2->connect_terminal (db::DeviceClassMOS3Transistor::terminal_id_G, n3); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2) [L=0.75,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); @@ -1168,10 +1209,11 @@ TEST(23_ParallelMOS3TransistorsDifferentLength) // because of different length, the devices will not be combined: - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3):\n" - " D d1 (S=n1,G=n3,D=n2) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2) [L=0.75,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3);\n" + " device '' d1 (S=n1,G=n3,D=n2) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); } @@ -1232,18 +1274,20 @@ TEST(30_ParallelMOS4Transistors) d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D=n0):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D=n0);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D=n0):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=3,AS=5,AD=7,PS=25,PD=27]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D=n0);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n" + "end;\n" ); } @@ -1304,18 +1348,20 @@ TEST(31_AntiParallelMOS4Transistors) d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D=n0):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n2,G=n3,D=n1,B=n0) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D=n0);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n2,G=n3,D=n1,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D=n0):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=3,AS=5,AD=7,PS=25,PD=27]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D=n0);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=3,AS=5,AD=7,PS=25,PD=27);\n" + "end;\n" ); } @@ -1381,10 +1427,11 @@ TEST(32_ParallelMOS4TransistorsDisconnectedGates) d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C1=n3a,C2=n3b,D=n0):\n" - " D d1 (S=n1,G=n3a,D=n2,B=n0) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3b,D=n2,B=n0) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C1=n3a,C2=n3b,D=n0);\n" + " device '' d1 (S=n1,G=n3a,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3b,D=n2,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); @@ -1392,10 +1439,11 @@ TEST(32_ParallelMOS4TransistorsDisconnectedGates) // not combined because gate is different: - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C1=n3a,C2=n3b,D=n0):\n" - " D d1 (S=n1,G=n3a,D=n2,B=n0) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3b,D=n2,B=n0) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C1=n3a,C2=n3b,D=n0);\n" + " device '' d1 (S=n1,G=n3a,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3b,D=n2,B=n0) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); } @@ -1461,10 +1509,11 @@ TEST(33_ParallelMOS4TransistorsDisconnectedBulk) circuit->connect_pin (pin_d2.id (), n0b); d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0b); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D1=n0a,D2=n0b):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0a) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2,B=n0b) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D1=n0a,D2=n0b);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0a) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2,B=n0b) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); // not combined because bulk is different: @@ -1472,10 +1521,11 @@ TEST(33_ParallelMOS4TransistorsDisconnectedBulk) nl.combine_devices (); nl.purge (); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D1=n0a,D2=n0b):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0a) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2,B=n0b) [L=0.5,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D1=n0a,D2=n0b);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0a) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2,B=n0b) (L=0.5,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); } @@ -1536,10 +1586,11 @@ TEST(34_ParallelMOS4TransistorsDifferentLength) d1->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); d2->connect_terminal (db::DeviceClassMOS4Transistor::terminal_id_B, n0); - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D=n0):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2,B=n0) [L=0.75,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D=n0);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2,B=n0) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); nl.combine_devices (); @@ -1547,10 +1598,11 @@ TEST(34_ParallelMOS4TransistorsDifferentLength) // not combined because length is different: - EXPECT_EQ (nl.to_string (), - "Circuit (A=n1,B=n2,C=n3,D=n0):\n" - " D d1 (S=n1,G=n3,D=n2,B=n0) [L=0.5,W=1,AS=2,AD=3,PS=12,PD=13]\n" - " D d2 (S=n1,G=n3,D=n2,B=n0) [L=0.75,W=2,AS=3,AD=4,PS=13,PD=14]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit '' (A=n1,B=n2,C=n3,D=n0);\n" + " device '' d1 (S=n1,G=n3,D=n2,B=n0) (L=0.5,W=1,AS=2,AD=3,PS=12,PD=13);\n" + " device '' d2 (S=n1,G=n3,D=n2,B=n0) (L=0.75,W=2,AS=3,AD=4,PS=13,PD=14);\n" + "end;\n" ); } diff --git a/src/db/unit_tests/dbNetlistExtractorTests.cc b/src/db/unit_tests/dbNetlistExtractorTests.cc index 9081ea214..a1beb5a78 100644 --- a/src/db/unit_tests/dbNetlistExtractorTests.cc +++ b/src/db/unit_tests/dbNetlistExtractorTests.cc @@ -280,28 +280,31 @@ TEST(1_DeviceAndNetExtraction) dump_nets_to_layout (nl, cl, ly, dump_map, cm); // compare netlist as string - EXPECT_EQ (nl.to_string (), - "Circuit RINGO ():\n" - " XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)\n" - " XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD)\n" - " XINV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD)\n" - " XINV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD)\n" - " XINV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD)\n" - " XINV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD)\n" - " XINV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD)\n" - " XINV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD)\n" - " XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)\n" - " XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " XTRANS $1 ($1=$2,$2=$4,$3=IN)\n" - " XTRANS $2 ($1=$2,$2=$5,$3=IN)\n" - " XTRANS $3 ($1=$5,$2=OUT,$3=$2)\n" - " XTRANS $4 ($1=$4,$2=OUT,$3=$2)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=$I43,OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=$I44,OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n" + " subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n" + " subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n" + " subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // use this opportunity to test serialization to and from string @@ -310,7 +313,7 @@ TEST(1_DeviceAndNetExtraction) nldup.add_device_class (i->clone ()); } nldup.from_string (nl.to_parsable_string ()); - EXPECT_EQ (nldup.to_string (), nl.to_string ()); + EXPECT_EQ (nldup.to_parsable_string (), nl.to_parsable_string ()); // doesn't do anything here, but we test that this does not destroy anything: nl.combine_devices (); @@ -320,23 +323,25 @@ TEST(1_DeviceAndNetExtraction) nl.purge (); // compare netlist as string - EXPECT_EQ (nl.to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD):\n" - " XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD)\n" - " XINV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD)\n" - " XINV2 $3 (IN=$I19,$2=(null),OUT=$I1,$4=VSS,$5=VDD)\n" - " XINV2 $4 (IN=$I1,$2=(null),OUT=$I2,$4=VSS,$5=VDD)\n" - " XINV2 $5 (IN=$I2,$2=(null),OUT=$I3,$4=VSS,$5=VDD)\n" - " XINV2 $6 (IN=$I3,$2=(null),OUT=$I4,$4=VSS,$5=VDD)\n" - " XINV2 $7 (IN=$I4,$2=(null),OUT=$I5,$4=VSS,$5=VDD)\n" - " XINV2 $8 (IN=$I5,$2=(null),OUT=$I6,$4=VSS,$5=VDD)\n" - " XINV2 $9 (IN=$I6,$2=(null),OUT=$I7,$4=VSS,$5=VDD)\n" - " XINV2 $10 (IN=$I7,$2=(null),OUT=$I8,$4=VSS,$5=VDD)\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,VSS=VSS,VDD=VDD);\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $3 (IN=$I19,$2=(null),OUT=$I1,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $4 (IN=$I1,$2=(null),OUT=$I2,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $5 (IN=$I2,$2=(null),OUT=$I3,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $6 (IN=$I3,$2=(null),OUT=$I4,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $7 (IN=$I4,$2=(null),OUT=$I5,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $8 (IN=$I5,$2=(null),OUT=$I6,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $9 (IN=$I6,$2=(null),OUT=$I7,$4=VSS,$5=VDD);\n" + " subcircuit INV2 $10 (IN=$I7,$2=(null),OUT=$I8,$4=VSS,$5=VDD);\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // compare the collected test data @@ -503,48 +508,49 @@ TEST(2_DeviceAndNetExtractionFlat) // compare netlist as string // NOTE: some of the nets are called IN,OUT but are different ones. They // happen to be the same because they share the same label. - EXPECT_EQ (nl.to_string (), - "Circuit RINGO ():\n" - " DPMOS $1 (S=$16,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=VDD,G=$16,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $3 (S=$14,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $4 (S=VDD,G=$14,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $5 (S=$12,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $6 (S=VDD,G=$12,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $7 (S='IN,FB',G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $8 (S=VDD,G='IN,FB',D='OUT,OSC') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $9 (S=$4,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $10 (S=VDD,G=$4,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $11 (S=$8,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $12 (S=VDD,G=$8,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $13 (S=$2,G='IN,FB',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $14 (S=VDD,G=$2,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $15 (S=$6,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $16 (S=VDD,G=$6,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $17 (S=$18,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $18 (S=VDD,G=$18,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DPMOS $19 (S=$10,G='IN,OUT',D=VDD) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $20 (S=VDD,G=$10,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $21 (S='IN,FB',G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $22 (S=VSS,G='IN,FB',D='OUT,OSC') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $23 (S=$18,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $24 (S=VSS,G=$18,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $25 (S=$14,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $26 (S=VSS,G=$14,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $27 (S=$12,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $28 (S=VSS,G=$12,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $29 (S=$4,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $30 (S=VSS,G=$4,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $31 (S=$2,G='IN,FB',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $32 (S=VSS,G=$2,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $33 (S=$8,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $34 (S=VSS,G=$8,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $35 (S=$6,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $36 (S=VSS,G=$6,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $37 (S=$16,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $38 (S=VSS,G=$16,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $39 (S=$10,G='IN,OUT',D=VSS) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $40 (S=VSS,G=$10,D='IN,OUT') [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit RINGO ();\n" + " device PMOS $1 (S=$16,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=VDD,G=$16,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $3 (S=$14,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $4 (S=VDD,G=$14,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $5 (S=$12,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $6 (S=VDD,G=$12,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $7 (S='IN,FB',G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $8 (S=VDD,G='IN,FB',D='OUT,OSC') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $9 (S=$4,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $10 (S=VDD,G=$4,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $11 (S=$8,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $12 (S=VDD,G=$8,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $13 (S=$2,G='IN,FB',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $14 (S=VDD,G=$2,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $15 (S=$6,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $16 (S=VDD,G=$6,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $17 (S=$18,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $18 (S=VDD,G=$18,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device PMOS $19 (S=$10,G='IN,OUT',D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $20 (S=VDD,G=$10,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $21 (S='IN,FB',G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $22 (S=VSS,G='IN,FB',D='OUT,OSC') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $23 (S=$18,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $24 (S=VSS,G=$18,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $25 (S=$14,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $26 (S=VSS,G=$14,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $27 (S=$12,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $28 (S=VSS,G=$12,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $29 (S=$4,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $30 (S=VSS,G=$4,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $31 (S=$2,G='IN,FB',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $32 (S=VSS,G=$2,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $33 (S=$8,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $34 (S=VSS,G=$8,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $35 (S=$6,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $36 (S=VSS,G=$6,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $37 (S=$16,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $38 (S=VSS,G=$16,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $39 (S=$10,G='IN,OUT',D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $40 (S=VSS,G=$10,D='IN,OUT') (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // compare the collected test data @@ -736,28 +742,31 @@ TEST(3_DeviceAndNetExtractionWithImplicitConnections) dump_nets_to_layout (nl, cl, ly, dump_map, cm); // compare netlist as string - EXPECT_EQ (nl.to_string (), - "Circuit RINGO ():\n" - " XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $3 (IN=NEXT,$2=$I43,OUT=$I5,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $4 (IN=$I3,$2=$I42,OUT=NEXT,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $5 (IN=$I5,$2=$I44,OUT=$I6,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $6 (IN=$I6,$2=$I45,OUT=$I7,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $7 (IN=$I7,$2=$I46,OUT=$I8,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $8 (IN=$I19,$2=$I39,OUT=$I1,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $9 (IN=$I1,$2=$I40,OUT=$I2,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $10 (IN=$I2,$2=$I41,OUT=$I3,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " XTRANS $1 ($1=$2,$2=$4,$3=IN)\n" - " XTRANS $2 ($1=$2,$2=$5,$3=IN)\n" - " XTRANS $3 ($1=$5,$2=OUT,$3=$2)\n" - " XTRANS $4 ($1=$4,$2=OUT,$3=$2)\n" - "Circuit TRANS ($1=$1,$2=$2,$3=$3):\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit RINGO ();\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $3 (IN=NEXT,$2=$I43,OUT=$I5,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $4 (IN=$I3,$2=$I42,OUT=NEXT,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $5 (IN=$I5,$2=$I44,OUT=$I6,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $6 (IN=$I6,$2=$I45,OUT=$I7,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $7 (IN=$I7,$2=$I46,OUT=$I8,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $8 (IN=$I19,$2=$I39,OUT=$I1,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $9 (IN=$I1,$2=$I40,OUT=$I2,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $10 (IN=$I2,$2=$I41,OUT=$I3,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " subcircuit TRANS $1 ($1=$2,$2=$4,$3=IN);\n" + " subcircuit TRANS $2 ($1=$2,$2=$5,$3=IN);\n" + " subcircuit TRANS $3 ($1=$5,$2=OUT,$3=$2);\n" + " subcircuit TRANS $4 ($1=$4,$2=OUT,$3=$2);\n" + "end;\n" + "circuit TRANS ($1=$1,$2=$2,$3=$3);\n" + "end;\n" ); // doesn't do anything here, but we test that this does not destroy anything: @@ -768,23 +777,25 @@ TEST(3_DeviceAndNetExtractionWithImplicitConnections) nl.purge (); // compare netlist as string - EXPECT_EQ (nl.to_string (), - "Circuit RINGO (FB=FB,OSC=OSC,NEXT=NEXT,'VSSZ,VSS'='VSSZ,VSS','VDDZ,VDD'='VDDZ,VDD'):\n" - " XINV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $2 (IN=FB,$2=(null),OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $3 (IN=NEXT,$2=(null),OUT=$I5,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $4 (IN=$I3,$2=(null),OUT=NEXT,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $5 (IN=$I5,$2=(null),OUT=$I6,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $6 (IN=$I6,$2=(null),OUT=$I7,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $7 (IN=$I7,$2=(null),OUT=$I8,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $8 (IN=$I19,$2=(null),OUT=$I1,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $9 (IN=$I1,$2=(null),OUT=$I2,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - " XINV2 $10 (IN=$I2,$2=(null),OUT=$I3,$4='VSSZ,VSS',$5='VDDZ,VDD')\n" - "Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):\n" - " DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" - " DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]\n" - " DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]\n" + EXPECT_EQ (nl.to_parsable_string (), + "circuit RINGO (FB=FB,OSC=OSC,NEXT=NEXT,'VSSZ,VSS'='VSSZ,VSS','VDDZ,VDD'='VDDZ,VDD');\n" + " subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $2 (IN=FB,$2=(null),OUT=$I19,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $3 (IN=NEXT,$2=(null),OUT=$I5,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $4 (IN=$I3,$2=(null),OUT=NEXT,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $5 (IN=$I5,$2=(null),OUT=$I6,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $6 (IN=$I6,$2=(null),OUT=$I7,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $7 (IN=$I7,$2=(null),OUT=$I8,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $8 (IN=$I19,$2=(null),OUT=$I1,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $9 (IN=$I1,$2=(null),OUT=$I2,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + " subcircuit INV2 $10 (IN=$I2,$2=(null),OUT=$I3,$4='VSSZ,VSS',$5='VDDZ,VDD');\n" + "end;\n" + "circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);\n" + " device PMOS $1 (S=$2,G=IN,D=$5) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device PMOS $2 (S=$5,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + " device NMOS $3 (S=$2,G=IN,D=$4) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n" + " device NMOS $4 (S=$4,G=$2,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n" + "end;\n" ); // compare the collected test data diff --git a/src/db/unit_tests/dbNetlistTests.cc b/src/db/unit_tests/dbNetlistTests.cc index 11e54ea09..95bf9844c 100644 --- a/src/db/unit_tests/dbNetlistTests.cc +++ b/src/db/unit_tests/dbNetlistTests.cc @@ -612,22 +612,26 @@ TEST(4_NetlistSubcircuits) "D:B,+c2p2\n" ); - EXPECT_EQ (nl->to_string (), - "Circuit c1 (c1p1=n1a,c1p2=n1c):\n" - " Xc2 sc1 (c2p1=n1a,c2p2=n1b)\n" - " Xc2 sc2 (c2p1=n1b,c2p2=n1c)\n" - "Circuit c2 (c2p1=n2a,c2p2=n2b):\n" - " Ddc2 D (A=n2a,B=n2b) []\n" + EXPECT_EQ (nl->to_parsable_string (), + "circuit c1 (c1p1=n1a,c1p2=n1c);\n" + " subcircuit c2 sc1 (c2p1=n1a,c2p2=n1b);\n" + " subcircuit c2 sc2 (c2p1=n1b,c2p2=n1c);\n" + "end;\n" + "circuit c2 (c2p1=n2a,c2p2=n2b);\n" + " device dc2 D (A=n2a,B=n2b) ();\n" + "end;\n" ); nldup->from_string (nl->to_parsable_string ()); - EXPECT_EQ (nldup->to_string (), - "Circuit c1 (c1p1=n1a,c1p2=n1c):\n" - " Xc2 sc1 (c2p1=n1a,c2p2=n1b)\n" - " Xc2 sc2 (c2p1=n1b,c2p2=n1c)\n" - "Circuit c2 (c2p1=n2a,c2p2=n2b):\n" - " Ddc2 D (A=n2a,B=n2b) []\n" + EXPECT_EQ (nldup->to_parsable_string (), + "circuit c1 (c1p1=n1a,c1p2=n1c);\n" + " subcircuit c2 sc1 (c2p1=n1a,c2p2=n1b);\n" + " subcircuit c2 sc2 (c2p1=n1b,c2p2=n1c);\n" + "end;\n" + "circuit c2 (c2p1=n2a,c2p2=n2b);\n" + " device dc2 D (A=n2a,B=n2b) ();\n" + "end;\n" ); EXPECT_EQ (netlist2 (*nl),