diff --git a/src/db/db/dbBoxScanner.h b/src/db/db/dbBoxScanner.h
index 07b5c8319..8183396e4 100644
--- a/src/db/db/dbBoxScanner.h
+++ b/src/db/db/dbBoxScanner.h
@@ -122,7 +122,7 @@ struct box_scanner_receiver
    *  The finish method is called when an object is no longer in the queue and can be
    *  discarded.
    */
-  virtual void finish (const Obj * /*obj*/, const Prop & /*prop*/) { }
+  virtual void finish (const Obj * /*obj*/, Prop /*prop*/) { }
 
   /**
    *  @brief Callback for an interaction of o1 with o2.
@@ -130,7 +130,7 @@ struct box_scanner_receiver
    *  This method is called when the object o1 interacts with o2 within the current 
    *  definition.
    */
-  virtual void add (const Obj * /*o1*/, const Prop & /*p1*/, const Obj * /*o2*/, const Prop & /*p2*/) { }
+  virtual void add (const Obj * /*o1*/, Prop /*p1*/, const Obj * /*o2*/, Prop /*p2*/) { }
 
   /**
    *  @brief Indicates whether the scanner may stop
@@ -1043,7 +1043,7 @@ public:
   /**
    *  @brief Implementation of the box scanner receiver class
    */
-  void finish (const Obj *obj, const Prop &prop)
+  void finish (const Obj *obj, Prop prop)
   {
     om_iterator_type omi = m_om.find (om_key_type (obj, prop));
     if (omi != m_om.end ()) {
@@ -1089,7 +1089,7 @@ public:
   /**
    *  @brief Implementation of the box scanner receiver class
    */
-  void add (const Obj *o1, const Prop &p1, const Obj *o2, const Prop &p2)
+  void add (const Obj *o1, Prop p1, const Obj *o2, Prop p2)
   {
     om_iterator_type om1 = m_om.find (om_key_type (o1, p1));
     om_iterator_type om2 = m_om.find (om_key_type (o2, p2));
diff --git a/src/db/db/dbNetlistCompare.cc b/src/db/db/dbNetlistCompare.cc
index 2bd44b72b..86016c64b 100644
--- a/src/db/db/dbNetlistCompare.cc
+++ b/src/db/db/dbNetlistCompare.cc
@@ -668,6 +668,40 @@ struct CompareData
   tl::RelativeProgress *progress;
 };
 
+// --------------------------------------------------------------------------------------------------------------------
+//  A generic triplet of object category and two IDs
+//  Used as a key for device terminal edges and subcircuit edges
+
+class CatAndIds
+{
+public:
+  CatAndIds (size_t cat, size_t id1, size_t id2)
+    : m_cat (cat), m_id1 (id1), m_id2 (id2)
+  { }
+
+  bool operator== (const CatAndIds &other) const
+  {
+    return m_cat == other.m_cat && m_id1 == other.m_id1 && m_id2 == other.m_id2;
+  }
+
+  bool operator< (const CatAndIds &other) const
+  {
+    if (m_cat != other.m_cat) {
+      return m_cat < other.m_cat;
+    }
+    if (m_id1 != other.m_id1) {
+      return m_id1 < other.m_id1;
+    }
+    if (m_id2 != other.m_id2) {
+      return m_id2 < other.m_id2;
+    }
+    return false;
+  }
+
+private:
+  size_t m_cat, m_id1, m_id2;
+};
+
 // --------------------------------------------------------------------------------------------------------------------
 //  NetGraphNode definition and implementation
 
@@ -676,6 +710,171 @@ static size_t translate_terminal_id (size_t tid, const db::Device *device)
   return device->device_class () ? device->device_class ()->normalize_terminal_id (tid) : tid;
 }
 
+/**
+ *  @brief Represents one transition within a net graph edge
+ *
+ *  Each transition connects two pins of subcircuits or terminals of devices.
+ *  An edge is basically a collection of transitions.
+ */
+class Transition
+{
+public:
+  Transition (const db::Device *device, size_t device_category, size_t terminal1_id, size_t terminal2_id)
+  {
+    m_ptr = (void *) device;
+    m_cat = device_category;
+    tl_assert (terminal1_id < std::numeric_limits<size_t>::max () / 2);
+    m_id1 = terminal1_id;
+    m_id2 = terminal2_id;
+  }
+
+  Transition (const db::SubCircuit *subcircuit, size_t subcircuit_category, size_t pin1_id, size_t pin2_id)
+  {
+    m_ptr = (void *) subcircuit;
+    m_cat = subcircuit_category;
+    //  m_id1 between max/2 and max indicates subcircuit
+    tl_assert (pin1_id < std::numeric_limits<size_t>::max () / 2);
+    m_id1 = std::numeric_limits<size_t>::max () - pin1_id;
+    m_id2 = pin2_id;
+  }
+
+  static size_t first_unique_pin_id ()
+  {
+    return std::numeric_limits<size_t>::max () / 4;
+  }
+
+  CatAndIds make_key () const
+  {
+    if (is_for_subcircuit ()) {
+      return CatAndIds (m_cat, m_id1, size_t (0));
+    } else {
+      return CatAndIds (m_cat, m_id1, m_id2);
+    }
+  }
+
+  bool operator< (const Transition &other) const
+  {
+    if (is_for_subcircuit () != other.is_for_subcircuit ()) {
+      return is_for_subcircuit () < other.is_for_subcircuit ();
+    }
+
+    if (is_for_subcircuit ()) {
+
+      if ((subcircuit () != 0) != (other.subcircuit () != 0)) {
+        return (subcircuit () != 0) < (other.subcircuit () != 0);
+      }
+
+      if (subcircuit () != 0) {
+        SubCircuitCompare scc;
+        if (! scc.equals (std::make_pair (subcircuit (), cat ()), std::make_pair (other.subcircuit (), other.cat ()))) {
+          return scc (std::make_pair (subcircuit (), cat ()), std::make_pair (other.subcircuit (), other.cat ()));
+        }
+      }
+
+      return m_id1 < other.m_id1;
+
+    } else {
+
+      if ((device () != 0) != (other.device () != 0)) {
+        return (device () != 0) < (other.device () != 0);
+      }
+
+      if (device () != 0) {
+        DeviceCompare dc;
+        if (! dc.equals (std::make_pair (device (), cat ()), std::make_pair (other.device (), other.cat ()))) {
+          return dc (std::make_pair (device (), cat ()), std::make_pair (other.device (), other.cat ()));
+        }
+      }
+
+      if (m_id1 != other.m_id1) {
+        return m_id1 < other.m_id1;
+      }
+      return m_id2 < other.m_id2;
+
+    }
+  }
+
+  bool operator== (const Transition &other) const
+  {
+    if (is_for_subcircuit () != other.is_for_subcircuit ()) {
+      return false;
+    }
+
+    if (is_for_subcircuit ()) {
+
+      if ((subcircuit () != 0) != (other.subcircuit () != 0)) {
+        return false;
+      }
+
+      if (subcircuit () != 0) {
+        SubCircuitCompare scc;
+        if (! scc.equals (std::make_pair (subcircuit (), cat ()), std::make_pair (other.subcircuit (), other.cat ()))) {
+          return false;
+        }
+      }
+
+      return (m_id1 == other.m_id1);
+
+    } else {
+
+      if ((device () != 0) != (other.device () != 0)) {
+        return false;
+      }
+
+      if (device () != 0) {
+        DeviceCompare dc;
+        if (! dc.equals (std::make_pair (device (), cat ()), std::make_pair (other.device (), other.cat ()))) {
+          return false;
+        }
+      }
+
+      return (m_id1 == other.m_id1 && m_id2 == other.m_id2);
+
+    }
+  }
+
+  std::string to_string () const
+  {
+    if (is_for_subcircuit ()) {
+      const db::SubCircuit *sc = subcircuit ();
+      const db::Circuit *c = sc->circuit_ref ();
+      return std::string ("X") + sc->expanded_name () + " " + c->name () + " " + c->pin_by_id (m_id2)->expanded_name () + " (virtual)";
+   } else {
+      size_t term_id1 = m_id1;
+      size_t term_id2 = m_id2;
+      const db::Device *d = device ();
+      const db::DeviceClass *dc = d->device_class ();
+      return std::string ("D") + d->expanded_name () + " " + dc->name () + " "
+        + "(" + dc->terminal_definitions () [term_id1].name () + ")->(" + dc->terminal_definitions () [term_id2].name () + ")";
+    }
+  }
+
+  inline bool is_for_subcircuit () const
+  {
+    return m_id1 > std::numeric_limits<size_t>::max () / 2;
+  }
+
+  const db::Device *device () const
+  {
+    return (const db::Device *) m_ptr;
+  }
+
+  const db::SubCircuit *subcircuit () const
+  {
+    return (const db::SubCircuit *) m_ptr;
+  }
+
+  size_t cat () const
+  {
+    return m_cat;
+  }
+
+private:
+  void *m_ptr;
+  size_t m_cat;
+  size_t m_id1, m_id2;
+};
+
 /**
  *  @brief A node within the net graph
  *
@@ -691,166 +890,6 @@ static size_t translate_terminal_id (size_t tid, const db::Device *device)
 class NetGraphNode
 {
 public:
-  /**
-   *  @brief Represents one transition within an edge_iterator
-   *
-   *  Each transition connects two pins of subcircuits or terminals
-   *  of devices.
-   *  An edge is basically a collection of transitions.
-   */
-  struct Transition
-  {
-
-    Transition (const db::Device *device, size_t device_category, size_t terminal1_id, size_t terminal2_id)
-    {
-      device_pair ().first = device;
-      device_pair ().second = device_category;
-      m_id1 = terminal1_id;
-      m_id2 = terminal2_id;
-    }
-
-    Transition (const db::SubCircuit *subcircuit, size_t subcircuit_category, size_t pin1_id, size_t pin2_id)
-    {
-      subcircuit_pair ().first = subcircuit;
-      subcircuit_pair ().second = subcircuit_category;
-      m_id1 = std::numeric_limits<size_t>::max () - pin1_id;
-      m_id2 = pin2_id;
-    }
-
-    size_t id1 () const
-    {
-      return m_id1;
-    }
-
-    size_t id2 () const
-    {
-      return m_id2;
-    }
-
-    bool operator< (const Transition &other) const
-    {
-      if (is_for_subcircuit () != other.is_for_subcircuit ()) {
-        return is_for_subcircuit () < other.is_for_subcircuit ();
-      }
-
-      if (is_for_subcircuit ()) {
-
-        if ((subcircuit_pair ().first != 0) != (other.subcircuit_pair ().first != 0)) {
-          return (subcircuit_pair ().first != 0) < (other.subcircuit_pair ().first != 0);
-        }
-
-        if (subcircuit_pair ().first != 0) {
-          SubCircuitCompare scc;
-          if (! scc.equals (subcircuit_pair (), other.subcircuit_pair ())) {
-            return scc (subcircuit_pair (), other.subcircuit_pair ());
-          }
-        }
-
-      } else {
-
-        if ((device_pair ().first != 0) != (other.device_pair ().first != 0)) {
-          return (device_pair ().first != 0) < (other.device_pair ().first != 0);
-        }
-
-        if (device_pair ().first != 0) {
-          DeviceCompare dc;
-          if (! dc.equals (device_pair (), other.device_pair ())) {
-            return dc (device_pair (), other.device_pair ());
-          }
-        }
-
-      }
-
-      if (m_id1 != other.m_id1) {
-        return m_id1 < other.m_id1;
-      }
-      return m_id2 < other.m_id2;
-    }
-
-    bool operator== (const Transition &other) const
-    {
-      if (is_for_subcircuit () != other.is_for_subcircuit ()) {
-        return false;
-      }
-
-      if (is_for_subcircuit ()) {
-
-        if ((subcircuit_pair ().first != 0) != (other.subcircuit_pair ().first != 0)) {
-          return false;
-        }
-
-        if (subcircuit_pair ().first != 0) {
-          SubCircuitCompare scc;
-          if (! scc.equals (subcircuit_pair (), other.subcircuit_pair ())) {
-            return false;
-          }
-        }
-
-      } else {
-
-        if ((device_pair ().first != 0) != (other.device_pair ().first != 0)) {
-          return false;
-        }
-
-        if (device_pair ().first != 0) {
-          DeviceCompare dc;
-          if (! dc.equals (device_pair (), other.device_pair ())) {
-            return false;
-          }
-        }
-
-      }
-
-      return (m_id1 == other.m_id1 && m_id2 == other.m_id2);
-    }
-
-    std::string to_string () const
-    {
-      if (is_for_subcircuit ()) {
-        const db::SubCircuit *sc = subcircuit_pair ().first;
-        size_t pin_id = std::numeric_limits<size_t>::max () - m_id1;
-        const db::Circuit *c = sc->circuit_ref ();
-        return std::string ("X") + sc->expanded_name () + " " + c->name () + " " + c->pin_by_id (pin_id)->expanded_name () + " (virtual)";
-     } else {
-        size_t term_id1 = m_id1;
-        size_t term_id2 = m_id2;
-        const db::Device *d = device_pair ().first;
-        const db::DeviceClass *dc = d->device_class ();
-        return std::string ("D") + d->expanded_name () + " " + dc->name () + " "
-          + "(" + dc->terminal_definitions () [term_id1].name () + ")->(" + dc->terminal_definitions () [term_id2].name () + ")";
-      }
-    }
-
-    inline bool is_for_subcircuit () const
-    {
-      return m_id1 > std::numeric_limits<size_t>::max () / 2;
-    }
-
-    std::pair<const db::Device *, size_t> &device_pair ()
-    {
-      return *reinterpret_cast<std::pair<const db::Device *, size_t> *> ((void *) &m_ref);
-    }
-
-    const std::pair<const db::Device *, size_t> &device_pair () const
-    {
-      return *reinterpret_cast<const std::pair<const db::Device *, size_t> *> ((const void *) &m_ref);
-    }
-
-    std::pair<const db::SubCircuit *, size_t> &subcircuit_pair ()
-    {
-      return *reinterpret_cast<std::pair<const db::SubCircuit *, size_t> *> ((void *) &m_ref);
-    }
-
-    const std::pair<const db::SubCircuit *, size_t> &subcircuit_pair () const
-    {
-      return *reinterpret_cast<const std::pair<const db::SubCircuit *, size_t> *> ((const void *) &m_ref);
-    }
-
-  private:
-    char m_ref [sizeof (std::pair<const void *, size_t>)];
-    size_t m_id1, m_id2;
-  };
-
   typedef std::pair<std::vector<Transition>, std::pair<size_t, const db::Net *> > edge_type;
 
   static void swap_edges (edge_type &e1, edge_type &e2)
@@ -878,12 +917,12 @@ public:
   /**
    *  @brief Builds a node for a net
    */
-  NetGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map);
+  NetGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map, size_t *unique_pin_id);
 
   /**
    *  @brief Builds a virtual node for a subcircuit
    */
-  NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circuit_categorizer, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map);
+  NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circuit_categorizer, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map, size_t *unique_pin_id);
 
   void expand_subcircuit_nodes (NetGraph *graph);
 
@@ -931,8 +970,18 @@ public:
 
   void apply_net_index (const std::map<const db::Net *, size_t> &ni);
 
-  bool operator< (const NetGraphNode &node) const;
-  bool operator== (const NetGraphNode &node) const;
+  bool less (const NetGraphNode &node, bool with_name) const;
+  bool equal (const NetGraphNode &node, bool with_name) const;
+
+  bool operator== (const NetGraphNode &node) const
+  {
+    return equal (node, false);
+  }
+
+  bool operator< (const NetGraphNode &node) const
+  {
+    return less (node, false);
+  }
 
   void swap (NetGraphNode &other)
   {
@@ -953,7 +1002,7 @@ public:
 
   edge_iterator find_edge (const std::vector<Transition> &edge) const
   {
-    edge_iterator res = std::lower_bound (begin (), end (), edge, NetGraphNode::EdgeToEdgeOnlyCompare ());
+    edge_iterator res = std::lower_bound (begin (), end (), edge, EdgeToEdgeOnlyCompare ());
     if (res == end () || res->first != edge) {
       return end ();
     } else {
@@ -970,13 +1019,13 @@ private:
    *  @brief Compares edges as "less"
    *  Edge comparison is based on the pins attached (name of the first pin).
    */
-  static bool net_less (const db::Net *a, const db::Net *b);
+  static bool net_less (const db::Net *a, const db::Net *b, bool with_name);
 
   /**
    *  @brief Compares edges as "equal"
    *  See edge_less for the comparison details.
    */
-  static bool edge_equal (const db::Net *a, const db::Net *b);
+  static bool net_equal (const db::Net *a, const db::Net *b, bool with_name);
 };
 
 // --------------------------------------------------------------------------------------------------------------------
@@ -999,7 +1048,7 @@ struct CompareNodePtr
 {
   bool operator() (const std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> &a, const std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> &b) const
   {
-    return *a.first < *b.first;
+    return a.first->less (*b.first, true);
   }
 };
 
@@ -1033,7 +1082,7 @@ public:
   /**
    *  @brief Builds the net graph
    */
-  void build (const db::Circuit *c, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const db::DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_and_pin_mapping, const CircuitPinMapper *circuit_pin_mapper);
+  void build (const db::Circuit *c, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const db::DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_and_pin_mapping, const CircuitPinMapper *circuit_pin_mapper, size_t *unique_pin_id);
 
   /**
    *  @brief Gets the node index for the given net
@@ -1184,7 +1233,12 @@ private:
 
 // --------------------------------------------------------------------------------------------------------------------
 
-NetGraphNode::NetGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map)
+static bool is_non_trivial_net (const db::Net *net)
+{
+  return net->pin_count () == 0 && net->terminal_count () == 0 && net->subcircuit_pin_count () == 1;
+}
+
+NetGraphNode::NetGraphNode (const db::Net *net, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map, size_t *unique_pin_id)
   : mp_net (net), m_other_net_index (invalid_id)
 {
   if (! net) {
@@ -1214,25 +1268,36 @@ NetGraphNode::NetGraphNode (const db::Net *net, DeviceCategorizer &device_catego
 
     const CircuitMapper *cm = & icm->second;
 
-    //  A pin assignment may be missing because there is no net for a pin -> skip this
+    //  A pin assignment may be missing because there is no (real) net for a pin -> skip this pin
+
+    size_t original_pin_id = pin_id;
 
     if (! cm->has_other_pin_for_this_pin (pin_id)) {
-      continue;
+
+      //  isolated pins are ignored, others are considered for the matching
+      if (! unique_pin_id || is_non_trivial_net (net)) {
+        continue;
+      } else {
+        pin_id = (*unique_pin_id)++;
+      }
+
+    } else {
+
+      //  NOTE: if cm is given, cr and pin_id are given in terms of the canonical "other" circuit.
+      //  For c1 this is the c1->c2 mapper, for c2 this is the c2->c2 dummy mapper.
+
+      pin_id = cm->other_pin_from_this_pin (pin_id);
+
+      //  realize pin swapping by normalization of pin ID
+
+      pin_id = pin_map->normalize_pin_id (cm->other (), pin_id);
+
     }
 
-    //  NOTE: if cm is given, cr and pin_id are given in terms of the canonical "other" circuit.
-    //  For c1 this is the c1->c2 mapper, for c2 this is the c2->c2 dummy mapper.
-
-    pin_id = cm->other_pin_from_this_pin (pin_id);
-
-    //  realize pin swapping by normalization of pin ID
-
-    pin_id = pin_map->normalize_pin_id (cm->other (), pin_id);
-
     //  Subcircuits are routed to a null node and descend from a virtual node inside the subcircuit.
     //  The reasoning is that this way we don't need #pins*(#pins-1) edges but rather #pins.
 
-    Transition ed (sc, circuit_cat, pin_id, pin_id);
+    Transition ed (sc, circuit_cat, pin_id, original_pin_id);
 
     std::map<const void *, size_t>::const_iterator in = n2entry.find ((const void *) sc);
     if (in == n2entry.end ()) {
@@ -1290,7 +1355,7 @@ NetGraphNode::NetGraphNode (const db::Net *net, DeviceCategorizer &device_catego
   }
 }
 
-NetGraphNode::NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circuit_categorizer, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map)
+NetGraphNode::NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circuit_categorizer, const std::map<const db::Circuit *, CircuitMapper> *circuit_map, const CircuitPinMapper *pin_map, size_t *unique_pin_id)
   : mp_net (0), m_other_net_index (invalid_id)
 {
   std::map<const db::Net *, size_t> n2entry;
@@ -1314,24 +1379,35 @@ NetGraphNode::NetGraphNode (const db::SubCircuit *sc, CircuitCategorizer &circui
       continue;
     }
 
-    //  A pin assignment may be missing because there is no net for a pin -> skip this
+    //  A pin assignment may be missing because there is no (real) net for a pin -> skip this pin
+
+    size_t original_pin_id = pin_id;
 
     if (! cm->has_other_pin_for_this_pin (pin_id)) {
-      continue;
+
+      //  isolated pins are ignored, others are considered for the matching
+      if (! unique_pin_id || is_non_trivial_net (net_at_pin)) {
+        continue;
+      } else {
+        pin_id = (*unique_pin_id)++;
+      }
+
+    } else {
+
+      //  NOTE: if cm is given, cr and pin_id are given in terms of the canonical "other" circuit.
+      //  For c1 this is the c1->c2 mapper, for c2 this is the c2->c2 dummy mapper.
+
+      pin_id = cm->other_pin_from_this_pin (pin_id);
+
+      //  realize pin swapping by normalization of pin ID
+
+      pin_id = pin_map->normalize_pin_id (cm->other (), pin_id);
+
     }
 
-    //  NOTE: if cm is given, cr and pin_id are given in terms of the canonical "other" circuit.
-    //  For c1 this is the c1->c2 mapper, for c2 this is the c2->c2 dummy mapper.
-
-    pin_id = cm->other_pin_from_this_pin (pin_id);
-
-    //  realize pin swapping by normalization of pin ID
-
-    pin_id = pin_map->normalize_pin_id (cm->other (), pin_id);
-
     //  Make the other endpoint
 
-    Transition ed (sc, circuit_cat, pin_id, pin_id);
+    Transition ed (sc, circuit_cat, pin_id, original_pin_id);
 
     std::map<const db::Net *, size_t>::const_iterator in = n2entry.find (net_at_pin);
     if (in == n2entry.end ()) {
@@ -1373,9 +1449,9 @@ NetGraphNode::expand_subcircuit_nodes (NetGraph *graph)
     for (std::vector<Transition>::const_iterator t = e->first.begin (); t != e->first.end (); ++t) {
       tl_assert (t->is_for_subcircuit ());
       if (! sc) {
-        sc = t->subcircuit_pair ().first;
+        sc = t->subcircuit ();
       } else {
-        tl_assert (sc == t->subcircuit_pair ().first);
+        tl_assert (sc == t->subcircuit ());
       }
     }
 
@@ -1456,7 +1532,7 @@ NetGraphNode::apply_net_index (const std::map<const db::Net *, size_t> &ni)
 }
 
 bool
-NetGraphNode::operator< (const NetGraphNode &node) const
+NetGraphNode::less (const NetGraphNode &node, bool with_name) const
 {
   if (m_edges.size () != node.m_edges.size ()) {
     return m_edges.size () < node.m_edges.size ();
@@ -1468,13 +1544,13 @@ NetGraphNode::operator< (const NetGraphNode &node) const
   }
   if (m_edges.empty ()) {
     //  do a more detailed analysis on the nets involved
-    return net_less (net (), node.net ());
+    return net_less (net (), node.net (), with_name);
   }
   return false;
 }
 
 bool
-NetGraphNode::operator== (const NetGraphNode &node) const
+NetGraphNode::equal (const NetGraphNode &node, bool with_name) const
 {
   if (m_edges.size () != node.m_edges.size ()) {
     return false;
@@ -1486,35 +1562,39 @@ NetGraphNode::operator== (const NetGraphNode &node) const
   }
   if (m_edges.empty ()) {
     //  do a more detailed analysis on the edges
-    return edge_equal (net (), node.net ());
+    return net_equal (net (), node.net (), with_name);
   }
   return true;
 }
 
 bool
-NetGraphNode::net_less (const db::Net *a, const db::Net *b)
+NetGraphNode::net_less (const db::Net *a, const db::Net *b, bool with_name)
 {
   if ((a != 0) != (b != 0)) {
     return (a != 0) < (b != 0);
   }
-  if (a != 0) {
-    return a->pin_count () < b->pin_count ();
-  } else {
+  if (a == 0) {
     return false;
   }
+  if (a->pin_count () != b->pin_count ()) {
+    return a->pin_count () < b->pin_count ();
+  }
+  return with_name ? name_compare (a, b) < 0 : false;
 }
 
 bool
-NetGraphNode::edge_equal (const db::Net *a, const db::Net *b)
+NetGraphNode::net_equal (const db::Net *a, const db::Net *b, bool with_name)
 {
   if ((a != 0) != (b != 0)) {
     return false;
   }
-  if (a != 0) {
-    return a->pin_count () == b->pin_count ();
-  } else {
+  if (a == 0) {
     return true;
   }
+  if (a->pin_count () != b->pin_count ()) {
+    return false;
+  }
+  return with_name ? name_compare (a, b) == 0 : true;
 }
 
 // --------------------------------------------------------------------------------------------------------------------
@@ -1524,53 +1604,27 @@ NetGraphNode::edge_equal (const db::Net *a, const db::Net *b)
  */
 struct NodeRange
 {
-  NodeRange (size_t _num, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _n1, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _nn1,
-                          std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _n2, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _nn2)
-    : num (_num), n1 (_n1), nn1 (_nn1), n2 (_n2), nn2 (_nn2)
+  NodeRange (size_t _num1, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _n1, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _nn1,
+             size_t _num2, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _n2, std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator _nn2)
+    : num1 (_num1), num2 (_num2), n1 (_n1), nn1 (_nn1), n2 (_n2), nn2 (_nn2)
   {
     //  .. nothing yet ..
   }
 
   bool operator< (const NodeRange &other) const
   {
-    return num < other.num;
+    if (num1 != other.num1) {
+      return num1 < other.num1;
+    }
+    return num2 < other.num2;
   }
 
-  size_t num;
+  size_t num1, num2;
   std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator n1, nn1, n2, nn2;
 };
 
 // --------------------------------------------------------------------------------------------------------------------
 
-struct CatAndIds
-{
-public:
-  CatAndIds (size_t _cat, size_t _id1, size_t _id2)
-    : cat (_cat), id1 (_id1), id2 (_id2)
-  { }
-
-  bool operator== (const CatAndIds &other) const
-  {
-    return cat == other.cat && id1 == other.id1 && id2 == other.id2;
-  }
-
-  bool operator< (const CatAndIds &other) const
-  {
-    if (cat != other.cat) {
-      return cat < other.cat;
-    }
-    if (id1 != other.id1) {
-      return id1 < other.id1;
-    }
-    if (id2 != other.id2) {
-      return id2 < other.id2;
-    }
-    return false;
-  }
-
-  size_t cat, id1, id2;
-};
-
 template <class Obj>
 class generic_mapper_for_target_node
 {
@@ -1659,9 +1713,9 @@ public:
 
     size_t ni = e.second.first;
     std::set<std::pair<CatAndIds, const Device *> > &dev = for_node_nc (ni);
-    for (std::vector<NetGraphNode::Transition>::const_iterator j = e.first.begin (); j != e.first.end (); ++j) {
+    for (std::vector<Transition>::const_iterator j = e.first.begin (); j != e.first.end (); ++j) {
       if (! j->is_for_subcircuit ()) {
-        dev.insert (std::make_pair (CatAndIds (j->device_pair ().second, j->id1 (), j->id2 ()), j->device_pair ().first));
+        dev.insert (std::make_pair (j->make_key (), j->device ()));
       }
     }
   }
@@ -1686,9 +1740,9 @@ public:
 
     size_t ni = e.second.first;
     std::set<std::pair<CatAndIds, const SubCircuit *> > &sc = for_node_nc (ni);
-    for (std::vector<NetGraphNode::Transition>::const_iterator j = e.first.begin (); j != e.first.end (); ++j) {
+    for (std::vector<Transition>::const_iterator j = e.first.begin (); j != e.first.end (); ++j) {
       if (j->is_for_subcircuit ()) {
-        sc.insert (std::make_pair (CatAndIds (j->subcircuit_pair ().second, j->id1 (), j->id2 ()), j->subcircuit_pair ().first));
+        sc.insert (std::make_pair (j->make_key (), j->subcircuit ()));
       }
     }
   }
@@ -1829,7 +1883,7 @@ private:
 //  NetGraph implementation
 
 void
-NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const db::DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_and_pin_mapping, const CircuitPinMapper *circuit_pin_mapper)
+NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, CircuitCategorizer &circuit_categorizer, const db::DeviceFilter &device_filter, const std::map<const db::Circuit *, CircuitMapper> *circuit_and_pin_mapping, const CircuitPinMapper *circuit_pin_mapper, size_t *unique_pin_id)
 {
   tl::SelfTimer timer (tl::verbosity () >= 31, tl::to_string (tr ("Building net graph for circuit: ")) + c->name ());
 
@@ -1839,7 +1893,7 @@ NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, Ci
   m_net_index.clear ();
 
   //  create a dummy node for a null net
-  m_nodes.push_back (NetGraphNode (0, device_categorizer, circuit_categorizer, device_filter, circuit_and_pin_mapping, circuit_pin_mapper));
+  m_nodes.push_back (NetGraphNode (0, device_categorizer, circuit_categorizer, device_filter, circuit_and_pin_mapping, circuit_pin_mapper, unique_pin_id));
 
   size_t nets = 0;
   for (db::Circuit::const_net_iterator n = c->begin_nets (); n != c->end_nets (); ++n) {
@@ -1848,7 +1902,7 @@ NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, Ci
   m_nodes.reserve (nets);
 
   for (db::Circuit::const_net_iterator n = c->begin_nets (); n != c->end_nets (); ++n) {
-    NetGraphNode node (n.operator-> (), device_categorizer, circuit_categorizer, device_filter, circuit_and_pin_mapping, circuit_pin_mapper);
+    NetGraphNode node (n.operator-> (), device_categorizer, circuit_categorizer, device_filter, circuit_and_pin_mapping, circuit_pin_mapper, unique_pin_id);
     if (! node.empty () || n->pin_count () > 0) {
       m_nodes.push_back (node);
     }
@@ -1883,7 +1937,7 @@ NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, Ci
       continue;
     }
 
-    m_virtual_nodes.insert (std::make_pair (i.operator-> (), NetGraphNode (i.operator-> (), circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper)));
+    m_virtual_nodes.insert (std::make_pair (i.operator-> (), NetGraphNode (i.operator-> (), circuit_categorizer, circuit_and_pin_mapping, circuit_pin_mapper, unique_pin_id)));
 
   }
 
@@ -1903,21 +1957,21 @@ NetGraph::build (const db::Circuit *c, DeviceCategorizer &device_categorizer, Ci
  */
 static bool edges_are_compatible (const NetGraphNode::edge_type &e, const NetGraphNode::edge_type &e_other, const DeviceEquivalenceTracker &device_eq, const SubCircuitEquivalenceTracker &sc_eq)
 {
-  std::vector<NetGraphNode::Transition>::const_iterator t1 = e.first.begin (), tt1 = e.first.end ();
-  std::vector<NetGraphNode::Transition>::const_iterator t2 = e_other.first.begin (), tt2 = e_other.first.end ();
+  std::vector<Transition>::const_iterator t1 = e.first.begin (), tt1 = e.first.end ();
+  std::vector<Transition>::const_iterator t2 = e_other.first.begin (), tt2 = e_other.first.end ();
 
   std::vector<void *> p1, p2;
 
   while (t1 != tt1 && t2 != tt2) {
 
-    std::vector<NetGraphNode::Transition>::const_iterator t10 = t1, t20 = t2;
+    std::vector<Transition>::const_iterator t10 = t1, t20 = t2;
 
     p1.clear ();
     while (t1 != tt1 && *t1 == *t10) {
       if (t1->is_for_subcircuit ()) {
-        p1.push_back ((void *) sc_eq.other (t1->subcircuit_pair ().first));
+        p1.push_back ((void *) sc_eq.other (t1->subcircuit ()));
       } else {
-        p1.push_back ((void *) device_eq.other (t1->device_pair ().first));
+        p1.push_back ((void *) device_eq.other (t1->device ()));
       }
       ++t1;
     }
@@ -1925,9 +1979,9 @@ static bool edges_are_compatible (const NetGraphNode::edge_type &e, const NetGra
     p2.clear ();
     while (t2 != tt2 && *t2 == *t20) {
       if (t2->is_for_subcircuit ()) {
-        p2.push_back ((void *) (sc_eq.other (t2->subcircuit_pair ().first) ? t2->subcircuit_pair ().first : 0));
+        p2.push_back ((void *) (sc_eq.other (t2->subcircuit ()) ? t2->subcircuit () : 0));
       } else {
-        p2.push_back ((void *) (device_eq.other (t2->device_pair ().first) ? t2->device_pair ().first : 0));
+        p2.push_back ((void *) (device_eq.other (t2->device ()) ? t2->device () : 0));
       }
       ++t2;
     }
@@ -2004,7 +2058,7 @@ NetGraph::derive_node_identities_for_edges (NetGraphNode::edge_iterator e, NetGr
         first = false;
       }
       tl::info << indent (depth) << "    " << (nn->net () ? nn->net ()->expanded_name ().c_str() : "(null)") << " via: " << tl::noendl;
-      for (std::vector<NetGraphNode::Transition>::const_iterator t = i->second->first.begin (); t != i->second->first.end(); ++t) {
+      for (std::vector<Transition>::const_iterator t = i->second->first.begin (); t != i->second->first.end(); ++t) {
         tl::info << (t != i->second->first.begin () ? "; " : "") << t->to_string() << tl::noendl;
       }
       tl::info << "";
@@ -2019,7 +2073,7 @@ NetGraph::derive_node_identities_for_edges (NetGraphNode::edge_iterator e, NetGr
         first = false;
       }
       tl::info << indent(depth) << "    " << (nn->net() ? nn->net()->expanded_name().c_str() : "(null)") << " via: " << tl::noendl;
-      for (std::vector<NetGraphNode::Transition>::const_iterator t = i->second->first.begin (); t != i->second->first.end(); ++t) {
+      for (std::vector<Transition>::const_iterator t = i->second->first.begin (); t != i->second->first.end(); ++t) {
         tl::info << (t != i->second->first.begin () ? "; " : "") << t->to_string() << tl::noendl;
       }
       tl::info << "";
@@ -2079,7 +2133,7 @@ NetGraph::derive_node_identities_for_edges (NetGraphNode::edge_iterator e, NetGr
 static bool has_subcircuits (db::NetGraphNode::edge_iterator e, db::NetGraphNode::edge_iterator ee)
 {
   while (e != ee) {
-    for (std::vector<NetGraphNode::Transition>::const_iterator t = e->first.begin (); t != e->first.end (); ++t) {
+    for (std::vector<Transition>::const_iterator t = e->first.begin (); t != e->first.end (); ++t) {
       if (t->is_for_subcircuit ()) {
         return true;
       }
@@ -2348,7 +2402,7 @@ NetGraph::derive_node_identities_from_ambiguity_group (const NodeRange &nr, Devi
   }
 
   size_t new_nodes = 0;
-  size_t complexity = nr.num;
+  size_t complexity = std::max (nr.num1, nr.num2);
 
   //  sort the ambiguity group such that net names match best
 
@@ -2751,30 +2805,32 @@ NetGraph::derive_node_identities_from_node_set (std::vector<std::pair<const NetG
 
     std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::iterator nn1 = n1, nn2 = n2;
 
-    size_t num = 1;
     ++nn1;
     ++nn2;
-    while (nn1 != nodes.end () && nn2 != other_nodes.end ()) {
-      if (nn1->first->has_other ()) {
-        ++nn1;
-      } else if (nn2->first->has_other ()) {
-        ++nn2;
-      } else if (! (*nn1->first == *n1->first) || ! (*nn2->first == *n2->first)) {
-        break;
-      } else {
-        ++num;
-        ++nn1;
-        ++nn2;
+
+    size_t num1 = 1;
+    while (nn1 != nodes.end () && *nn1->first == *n1->first) {
+      if (! nn1->first->has_other ()) {
+        ++num1;
       }
+      ++nn1;
     }
 
-    if (num == 1 || data->with_ambiguous) {
-      node_ranges.push_back (NodeRange (num, n1, nn1, n2, nn2));
+    size_t num2 = 1;
+    while (nn2 != other_nodes.end () && *nn2->first == *n2->first) {
+      if (! nn2->first->has_other ()) {
+        ++num2;
+      }
+      ++nn2;
+    }
+
+    if ((num1 == 1 && num2 == 1) || data->with_ambiguous) {
+      node_ranges.push_back (NodeRange (num1, n1, nn1, num2, n2, nn2));
     }
 
     //  in tentative mode ambiguous nodes don't make a match without
     //  with_ambiguous
-    if (num > 1 && tentative && ! data->with_ambiguous) {
+    if ((num1 > 1 || num2 > 1) && tentative && ! data->with_ambiguous) {
       return failed_match;
     }
 
@@ -2801,26 +2857,25 @@ NetGraph::derive_node_identities_from_node_set (std::vector<std::pair<const NetG
       }
     }
 
-    nr->num = 0;
-    std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::const_iterator i1 = nr->n1, i2 = nr->n2;
-
-    while (i1 != nr->nn1 && i2 != nr->nn2) {
-      if (i1->first->has_other ()) {
-        ++i1;
-      } else if (i2->first->has_other ()) {
-        ++i2;
-      } else {
-        ++nr->num;
-        ++i1;
-        ++i2;
+    nr->num1 = 0;
+    for (std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::const_iterator i = nr->n1; i != nr->nn1; ++i) {
+      if (! i->first->has_other ()) {
+        ++nr->num1;
       }
     }
 
-    if (nr->num < 1) {
+    nr->num2 = 0;
+    for (std::vector<std::pair<const NetGraphNode *, NetGraphNode::edge_iterator> >::const_iterator i = nr->n2; i != nr->nn2; ++i) {
+      if (! i->first->has_other ()) {
+        ++nr->num2;
+      }
+    }
+
+    if (nr->num1 < 1 || nr->num2 < 1) {
 
       //  ignore this - it got obsolete.
 
-    } else if (nr->num == 1) {
+    } else if (nr->num1 == 1 && nr->num2 == 1) {
 
       size_t n = derive_node_identities_from_singular_match (nr->n1->first, nr->n1->second, nr->n2->first, nr->n2->second, dm, dm_other, scm, scm_other, depth, n_branch, tentative, data, ! data->dont_consider_net_names);
       if (n == failed_match) {
@@ -2829,17 +2884,17 @@ NetGraph::derive_node_identities_from_node_set (std::vector<std::pair<const NetG
 
       new_nodes += n;
 
-    } else if (data->max_n_branch != std::numeric_limits<size_t>::max () && double (nr->num) * double (n_branch) > double (data->max_n_branch)) {
+    } else if (data->max_n_branch != std::numeric_limits<size_t>::max () && double (std::max (nr->num1, nr->num2)) * double (n_branch) > double (data->max_n_branch)) {
 
       if (options ()->debug_netcompare) {
-        tl::info << indent_s << "max. complexity exhausted (" << nr->num << "*" << n_branch << ">" << data->max_n_branch << ") - mismatch.";
+        tl::info << indent_s << "max. complexity exhausted (" << std::max (nr->num1, nr->num2) << "*" << n_branch << ">" << data->max_n_branch << ") - mismatch.";
       }
       return failed_match;
 
     } else {
 
       if (options ()->debug_netcompare) {
-        tl::info << indent_s << "analyzing ambiguity group with " << nr->num << " members";
+        tl::info << indent_s << "analyzing ambiguity group with " << nr->num1 << "/" << nr->num2 << " members";
       }
 
       size_t n = derive_node_identities_from_ambiguity_group (*nr, dm, dm_other, scm, scm_other, depth, n_branch, tentative, data);
@@ -2850,7 +2905,7 @@ NetGraph::derive_node_identities_from_node_set (std::vector<std::pair<const NetG
       new_nodes += n;
 
       if (options ()->debug_netcompare) {
-        tl::info << indent_s << "finished analysis of ambiguity group with " << nr->num << " members";
+        tl::info << indent_s << "finished analysis of ambiguity group with " << nr->num1 << "/" << nr->num2 << " members";
       }
 
     }
@@ -3569,16 +3624,21 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2,
 
   db::NetGraph g1, g2;
 
+  size_t unique_pin_id = Transition::first_unique_pin_id ();
+
   //  NOTE: for normalization we map all subcircuits of c1 to c2.
   //  Also, pin swapping will only happen there.
   if (options ()->debug_netgraph) {
     tl::info << "Netlist graph:";
   }
-  g1.build (c1, device_categorizer, circuit_categorizer, device_filter, &c12_circuit_and_pin_mapping, &circuit_pin_mapper);
+  g1.build (c1, device_categorizer, circuit_categorizer, device_filter, &c12_circuit_and_pin_mapping, &circuit_pin_mapper, (size_t *)0);
+
   if (options ()->debug_netgraph) {
     tl::info << "Other netlist graph:";
   }
-  g2.build (c2, device_categorizer, circuit_categorizer, device_filter, &c22_circuit_and_pin_mapping, &circuit_pin_mapper);
+  //  NOTE: the second netlist graph is the reference (schematic). We treat it a little more carefully by using pins from subcircuits which
+  //  lead to passive nets but connect to non-trivial nets on the outside. This is done by specifying a unique_pin_id counter for the last argument.
+  g2.build (c2, device_categorizer, circuit_categorizer, device_filter, &c22_circuit_and_pin_mapping, &circuit_pin_mapper, &unique_pin_id);
 
   //  Match dummy nodes for null nets
   g1.identify (0, 0);
@@ -4251,6 +4311,11 @@ NetlistComparer::do_subcircuit_assignment (const db::Circuit *c1, const db::NetG
     } else if (valid) {
       //  TODO: report devices which cannot be distinguished topologically?
       subcircuit_map.insert (std::make_pair (k, std::make_pair (sc.operator-> (), sc_cat)));
+    } else {
+      //  emit a mismatch event but do not consider that an error - this may happen if the circuit has been dropped intentionally (e.g. via cells)
+      if (mp_logger) {
+        mp_logger->subcircuit_mismatch (sc.operator-> (), 0);
+      }
     }
 
   }
@@ -4540,7 +4605,7 @@ NetlistComparer::join_symmetric_nets (db::Circuit *circuit)
   db::NetGraph graph;
   db::CircuitCategorizer circuit_categorizer;
   db::DeviceCategorizer device_categorizer;
-  graph.build (circuit, device_categorizer, circuit_categorizer, device_filter, &circuit_and_pin_mapping, &circuit_pin_mapper);
+  graph.build (circuit, device_categorizer, circuit_categorizer, device_filter, &circuit_and_pin_mapping, &circuit_pin_mapper, (size_t *) 0);
 
   //  sort the nodes so we can easily identify the identical ones (in terms of topology)
   //  nodes are identical if the attached devices and circuits are of the same kind and with the same parameters
diff --git a/src/db/db/dbRegionUtils.cc b/src/db/db/dbRegionUtils.cc
index ef0b5ac0a..e4e33e563 100644
--- a/src/db/db/dbRegionUtils.cc
+++ b/src/db/db/dbRegionUtils.cc
@@ -108,7 +108,7 @@ static inline bool shields (const db::EdgePair &ep, const db::Edge &q)
 }
 
 void
-Edge2EdgeCheckBase::finish (const Edge *o, const size_t &p)
+Edge2EdgeCheckBase::finish (const Edge *o, size_t p)
 {
   if (m_has_negative_edge_output && m_pass == 1 && m_pseudo_edges.find (std::make_pair (*o, p)) == m_pseudo_edges.end ()) {
 
diff --git a/src/db/db/dbRegionUtils.h b/src/db/db/dbRegionUtils.h
index cd759cb4f..62fca5cd3 100644
--- a/src/db/db/dbRegionUtils.h
+++ b/src/db/db/dbRegionUtils.h
@@ -611,7 +611,7 @@ public:
   /**
    *  @brief Reimplementation of the box_scanner_receiver interface
    */
-  void finish (const Edge *o, const size_t &);
+  void finish (const Edge *o, size_t);
 
   /**
    *  @brief Gets a value indicating whether the check requires different layers
diff --git a/src/db/unit_tests/dbLayoutToNetlistTests.cc b/src/db/unit_tests/dbLayoutToNetlistTests.cc
index 155a371fd..7acad9839 100644
--- a/src/db/unit_tests/dbLayoutToNetlistTests.cc
+++ b/src/db/unit_tests/dbLayoutToNetlistTests.cc
@@ -1140,17 +1140,17 @@ TEST(3_GlobalNetConnections)
   CHECKPOINT ();
   db::compare_netlist (_this, *l2n.netlist (),
     "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
-    "  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD);\n"
-    "  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n"
-    "  subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD);\n"
-    "  subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD);\n"
-    "  subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD);\n"
+    "  subcircuit INV2PAIR $1 ($2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD);\n"
+    "  subcircuit INV2PAIR $2 ($2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n"
+    "  subcircuit INV2PAIR $3 ($2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD);\n"
+    "  subcircuit INV2PAIR $4 ($2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD);\n"
+    "  subcircuit INV2PAIR $5 ($2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD);\n"
     "end;\n"
-    "circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n"
-    "  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK);\n"
-    "  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK);\n"
+    "circuit INV2PAIR ($2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1);\n"
+    "  subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6);\n"
+    "  subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6);\n"
     "end;\n"
-    "circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK);\n"
+    "circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD);\n"
     "  device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
     "  device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
     "  device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
diff --git a/src/db/unit_tests/dbNetlistCompareTests.cc b/src/db/unit_tests/dbNetlistCompareTests.cc
index 081351a47..7ef82e780 100644
--- a/src/db/unit_tests/dbNetlistCompareTests.cc
+++ b/src/db/unit_tests/dbNetlistCompareTests.cc
@@ -939,8 +939,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
     "match_nets VDD VDD\n"
     "match_nets VSS VSS\n"
     "match_nets OUT OUT\n"
-    "match_nets INT $10\n"
     "net_mismatch IN IN\n"
+    "match_nets INT $10\n"
     "net_mismatch INT2 $11\n"
     "match_pins $0 $1\n"
     "match_pins $1 $3\n"
@@ -995,8 +995,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
     "match_nets VDD VDD\n"
     "match_nets VSS VSS\n"
     "match_nets OUT OUT\n"
-    "match_nets INT $10\n"
     "net_mismatch IN IN\n"
+    "match_nets INT $10\n"
     "net_mismatch INT2 $11\n"
     "match_pins $0 $1\n"
     "match_pins $1 $3\n"
@@ -1023,8 +1023,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
     "match_nets VDD VDD\n"
     "match_nets VSS VSS\n"
     "match_nets OUT OUT\n"
-    "match_nets INT $10\n"
     "net_mismatch IN IN\n"
+    "match_nets INT $10\n"
     "net_mismatch INT2 $11\n"
     "match_pins $0 $1\n"
     "match_pins $1 $3\n"
@@ -1109,8 +1109,8 @@ TEST(5_BufferTwoPathsDifferentParameters)
     "match_nets VDD VDD\n"
     "match_nets VSS VSS\n"
     "match_nets OUT OUT\n"
-    "match_nets INT $10\n"
     "net_mismatch IN IN\n"
+    "match_nets INT $10\n"
     "net_mismatch INT2 $11\n"
     "match_pins $0 $1\n"
     "match_pins $1 $3\n"
@@ -1557,15 +1557,15 @@ TEST(8_DiodesDontMatchOnSwappedPins)
 
   EXPECT_EQ (logger.text (),
     "begin_circuit TRIANGLE TRIANGLE\n"
-    "match_nets P1 P3\n"
-    "net_mismatch P2 P1\n"
-    "net_mismatch P3 P2\n"
-    "match_pins $0 $2\n"
-    "match_pins $1 $0\n"
-    "match_pins $2 $1\n"
-    "match_devices $1 $1\n"
-    "match_devices $3 $3\n"
-    "device_mismatch $2 $2\n"
+    "match_nets P3 P3\n"
+    "net_mismatch P1 P1\n"
+    "net_mismatch P2 P2\n"
+    "match_pins $0 $0\n"
+    "match_pins $1 $1\n"
+    "match_pins $2 $2\n"
+    "match_devices $3 $1\n"
+    "match_devices $2 $3\n"
+    "device_mismatch $1 $2\n"
     "end_circuit TRIANGLE TRIANGLE NOMATCH"
   );
   EXPECT_EQ (good, false);
@@ -1984,6 +1984,7 @@ TEST(13_MismatchingSubcircuitsAdditionalHierarchy)
     "match_pins $1 $0\n"
     "match_pins $2 $2\n"
     "match_pins $3 $3\n"
+    "subcircuit_mismatch $2 (null)\n"
     "match_subcircuits $3 $1\n"
     "match_subcircuits $1 $2\n"
     "end_circuit TOP TOP MATCH"
@@ -3931,25 +3932,6 @@ TEST(21_BusLikeAmbiguousConnections)
 TEST(22_NodesRemoved)
 {
   const char *nls1 =
-    "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
-    "  subcircuit INV2PAIR $1 ($2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC);\n"
-    "  subcircuit INV2PAIR $2 ($2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I21);\n"
-    "  subcircuit INV2PAIR $3 ($2=$I23,$3=VDD,$4=VSS,$5=$I21,$6=$I5);\n"
-    "  subcircuit INV2PAIR $4 ($2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6);\n"
-    "  subcircuit INV2PAIR $5 ($2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7);\n"
-    "end;\n"
-    "circuit INV2PAIR ($2=$I8,$3=$I5,$4=$I4,$5=$I3,$6=$I2);\n"
-    "  subcircuit INV2 $1 (IN=$I3,$3=$I7,OUT=$I6,VSS=$I4,VDD=$I5);\n"
-    "  subcircuit INV2 $2 (IN=$I6,$3=$I8,OUT=$I2,VSS=$I4,VDD=$I5);\n"
-    "end;\n"
-    "circuit INV2 (IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD);\n"
-    "  device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
-    "  device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
-    "  device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
-    "  device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
-    "end;\n";
-
-  const char *nls2 =
     "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
     "  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD);\n"
     "  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n"
@@ -3968,6 +3950,25 @@ TEST(22_NodesRemoved)
     "  device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
     "end;\n";
 
+  const char *nls2 =
+    "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
+    "  subcircuit INV2PAIR $1 ($2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC);\n"
+    "  subcircuit INV2PAIR $2 ($2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I21);\n"
+    "  subcircuit INV2PAIR $3 ($2=$I23,$3=VDD,$4=VSS,$5=$I21,$6=$I5);\n"
+    "  subcircuit INV2PAIR $4 ($2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6);\n"
+    "  subcircuit INV2PAIR $5 ($2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7);\n"
+    "end;\n"
+    "circuit INV2PAIR ($2=$I8,$3=$I5,$4=$I4,$5=$I3,$6=$I2);\n"
+    "  subcircuit INV2 $1 (IN=$I3,$3=$I7,OUT=$I6,VSS=$I4,VDD=$I5);\n"
+    "  subcircuit INV2 $2 (IN=$I6,$3=$I8,OUT=$I2,VSS=$I4,VDD=$I5);\n"
+    "end;\n"
+    "circuit INV2 (IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD);\n"
+    "  device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
+    "  device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
+    "  device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
+    "  device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
+    "end;\n";
+
   db::Netlist nl1, nl2;
   prep_nl (nl1, nls1);
   prep_nl (nl2, nls2);
@@ -3980,6 +3981,79 @@ TEST(22_NodesRemoved)
 
   std::string txt = logger.text ();
 
+  EXPECT_EQ (txt,
+    "begin_circuit INV2 INV2\n"
+    "match_nets VDD VDD\n"
+    "match_nets OUT OUT\n"
+    "match_nets $3 $3\n"
+    "match_nets IN IN\n"
+    "match_nets VSS VSS\n"
+    "match_nets $1 (null)\n"
+    "match_nets BULK (null)\n"
+    "match_pins IN IN\n"
+    "match_pins $2 $1\n"
+    "match_pins OUT OUT\n"
+    "match_pins VSS VSS\n"
+    "match_pins VDD VDD\n"
+    "match_pins $0 (null)\n"
+    "match_pins BULK (null)\n"
+    "match_devices $1 $1\n"
+    "match_devices $2 $2\n"
+    "match_devices $3 $3\n"
+    "match_devices $4 $4\n"
+    "end_circuit INV2 INV2 MATCH\n"
+    "begin_circuit INV2PAIR INV2PAIR\n"
+    "match_nets $I2 $I2\n"
+    "match_nets $I6 $I5\n"
+    "match_nets $I5 $I4\n"
+    "match_nets $I4 $I6\n"
+    "match_nets $I3 $I3\n"
+    "match_nets $I7 $I7\n"
+    "match_nets $I8 $I8\n"
+    "match_nets BULK (null)\n"
+    "match_nets $I1 (null)\n"
+    "match_pins $1 $0\n"
+    "match_pins $2 $1\n"
+    "match_pins $3 $2\n"
+    "match_pins $4 $3\n"
+    "match_pins $5 $4\n"
+    "match_pins BULK (null)\n"
+    "match_pins $6 (null)\n"
+    "match_subcircuits $1 $1\n"
+    "match_subcircuits $2 $2\n"
+    "end_circuit INV2PAIR INV2PAIR MATCH\n"
+    "begin_circuit RINGO RINGO\n"
+    "match_nets OSC OSC\n"
+    "match_nets $I7 $I7\n"
+    "match_nets $I6 $I6\n"
+    "match_nets $I5 $I5\n"
+    "match_nets $I13 $I21\n"
+    "match_nets FB FB\n"
+    "match_nets VSS VSS\n"
+    "match_nets VDD VDD\n"
+    "match_nets $I22 $I22\n"
+    "match_nets $I23 $I23\n"
+    "match_nets $I24 $I24\n"
+    "match_nets $I25 $I25\n"
+    "match_pins FB FB\n"
+    "match_pins OSC OSC\n"
+    "match_pins VDD VDD\n"
+    "match_pins VSS VSS\n"
+    "match_subcircuits $1 $1\n"
+    "match_subcircuits $2 $2\n"
+    "match_subcircuits $3 $3\n"
+    "match_subcircuits $4 $4\n"
+    "match_subcircuits $5 $5\n"
+    "end_circuit RINGO RINGO MATCH"
+  );
+  EXPECT_EQ (good, true);
+
+  logger.clear ();
+  good = comp.compare (&nl2, &nl1);
+
+  txt = logger.text ();
+
+  //  additional nodes are not ignored when they come from the reference side (second)
   EXPECT_EQ (txt,
     "begin_circuit INV2 INV2\n"
     "match_nets VDD VDD\n"
@@ -4028,24 +4102,28 @@ TEST(22_NodesRemoved)
     "match_nets $I5 $I5\n"
     "match_nets $I21 $I13\n"
     "match_nets FB FB\n"
-    "match_nets VSS VSS\n"
-    "match_nets VDD VDD\n"
     "match_nets $I22 $I22\n"
     "match_nets $I23 $I23\n"
     "match_nets $I24 $I24\n"
     "match_nets $I25 $I25\n"
+    "net_mismatch VDD (null)\n"
+    "net_mismatch VSS (null)\n"
+    "net_mismatch (null) VDD\n"
+    "net_mismatch (null) VSS\n"
     "match_pins FB FB\n"
     "match_pins OSC OSC\n"
-    "match_pins VDD VDD\n"
-    "match_pins VSS VSS\n"
-    "match_subcircuits $1 $1\n"
-    "match_subcircuits $2 $2\n"
-    "match_subcircuits $3 $3\n"
-    "match_subcircuits $4 $4\n"
-    "match_subcircuits $5 $5\n"
-    "end_circuit RINGO RINGO MATCH"
+    "match_pins VDD (null)\n"
+    "match_pins VSS (null)\n"
+    "match_pins (null) VDD\n"
+    "match_pins (null) VSS\n"
+    "subcircuit_mismatch $1 $1\n"
+    "subcircuit_mismatch $2 $2\n"
+    "subcircuit_mismatch $3 $3\n"
+    "subcircuit_mismatch $4 $4\n"
+    "subcircuit_mismatch $5 $5\n"
+    "end_circuit RINGO RINGO NOMATCH"
   );
-  EXPECT_EQ (good, true);
+  EXPECT_EQ (good, false);
 }
 
 TEST(23_NodesRemovedWithError)
@@ -4103,12 +4181,12 @@ TEST(23_NodesRemovedWithError)
 
   EXPECT_EQ (txt,
     "begin_circuit INV2 INV2\n"
-    "match_nets $1 $1\n"
     "match_nets VDD VDD\n"
     "match_nets OUT OUT\n"
     "match_nets $3 $3\n"
     "match_nets IN IN\n"
     "match_nets VSS VSS\n"
+    "match_ambiguous_nets $1 $1\n"
     "match_nets (null) BULK\n"
     "match_pins $0 $0\n"
     "match_pins IN IN\n"
@@ -4150,25 +4228,6 @@ TEST(23_NodesRemovedWithError)
 TEST(24_NodesRemovedButConnectedInOther)
 {
   const char *nls1 =
-    "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
-    "  subcircuit INV2PAIR $1 ($2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC);\n"
-    "  subcircuit INV2PAIR $2 ($2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I21);\n"
-    "  subcircuit INV2PAIR $3 ($2=$I23,$3=VDD,$4=VSS,$5=$I21,$6=$I5);\n"
-    "  subcircuit INV2PAIR $4 ($2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6);\n"
-    "  subcircuit INV2PAIR $5 ($2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7);\n"
-    "end;\n"
-    "circuit INV2PAIR ($2=$I8,$3=$I5,$4=$I4,$5=$I3,$6=$I2);\n"
-    "  subcircuit INV2 $1 (IN=$I3,$3=$I7,OUT=$I6,VSS=$I4,VDD=$I5);\n"
-    "  subcircuit INV2 $2 (IN=$I6,$3=$I8,OUT=$I2,VSS=$I4,VDD=$I5);\n"
-    "end;\n"
-    "circuit INV2 (IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD);\n"
-    "  device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
-    "  device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
-    "  device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
-    "  device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
-    "end;\n";
-
-  const char *nls2 =
     "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
     "  subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD);\n"
     "  subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD);\n"
@@ -4189,6 +4248,25 @@ TEST(24_NodesRemovedButConnectedInOther)
     "  device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
     "end;\n";
 
+  const char *nls2 =
+    "circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS);\n"
+    "  subcircuit INV2PAIR $1 ($2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC);\n"
+    "  subcircuit INV2PAIR $2 ($2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I21);\n"
+    "  subcircuit INV2PAIR $3 ($2=$I23,$3=VDD,$4=VSS,$5=$I21,$6=$I5);\n"
+    "  subcircuit INV2PAIR $4 ($2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6);\n"
+    "  subcircuit INV2PAIR $5 ($2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7);\n"
+    "end;\n"
+    "circuit INV2PAIR ($2=$I8,$3=$I5,$4=$I4,$5=$I3,$6=$I2);\n"
+    "  subcircuit INV2 $1 (IN=$I3,$3=$I7,OUT=$I6,VSS=$I4,VDD=$I5);\n"
+    "  subcircuit INV2 $2 (IN=$I6,$3=$I8,OUT=$I2,VSS=$I4,VDD=$I5);\n"
+    "end;\n"
+    "circuit INV2 (IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD);\n"
+    "  device PMOS $1 (S=$3,G=IN,D=VDD) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
+    "  device PMOS $2 (S=VDD,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
+    "  device NMOS $3 (S=$3,G=IN,D=VSS) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5);\n"
+    "  device NMOS $4 (S=VSS,G=$3,D=OUT) (L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95);\n"
+    "end;\n";
+
   db::Netlist nl1, nl2;
   prep_nl (nl1, nls1);
   prep_nl (nl2, nls2);
@@ -4208,15 +4286,15 @@ TEST(24_NodesRemovedButConnectedInOther)
     "match_nets $3 $3\n"
     "match_nets IN IN\n"
     "match_nets VSS VSS\n"
-    "match_nets (null) $1\n"
-    "match_nets (null) BULK\n"
+    "match_nets $1 (null)\n"
+    "match_nets BULK (null)\n"
     "match_pins IN IN\n"
-    "match_pins $1 $2\n"
+    "match_pins $2 $1\n"
     "match_pins OUT OUT\n"
     "match_pins VSS VSS\n"
     "match_pins VDD VDD\n"
-    "match_pins (null) $0\n"
-    "match_pins (null) BULK\n"
+    "match_pins $0 (null)\n"
+    "match_pins BULK (null)\n"
     "match_devices $1 $1\n"
     "match_devices $2 $2\n"
     "match_devices $3 $3\n"
@@ -4224,21 +4302,21 @@ TEST(24_NodesRemovedButConnectedInOther)
     "end_circuit INV2 INV2 MATCH\n"
     "begin_circuit INV2PAIR INV2PAIR\n"
     "match_nets $I2 $I2\n"
-    "match_nets $I5 $I6\n"
-    "match_nets $I4 $I5\n"
-    "match_nets $I6 $I4\n"
+    "match_nets $I6 $I5\n"
+    "match_nets $I5 $I4\n"
+    "match_nets $I4 $I6\n"
     "match_nets $I3 $I3\n"
     "match_nets $I7 $I7\n"
     "match_nets $I8 $I8\n"
-    "match_nets (null) BULK\n"
-    "match_nets (null) $I1\n"
-    "match_pins $0 $1\n"
-    "match_pins $1 $2\n"
-    "match_pins $2 $3\n"
-    "match_pins $3 $4\n"
-    "match_pins $4 $5\n"
-    "match_pins (null) BULK\n"
-    "match_pins (null) $6\n"
+    "match_nets BULK (null)\n"
+    "match_nets $I1 (null)\n"
+    "match_pins $1 $0\n"
+    "match_pins $2 $1\n"
+    "match_pins $3 $2\n"
+    "match_pins $4 $3\n"
+    "match_pins $5 $4\n"
+    "match_pins BULK (null)\n"
+    "match_pins $6 (null)\n"
     "match_subcircuits $1 $1\n"
     "match_subcircuits $2 $2\n"
     "end_circuit INV2PAIR INV2PAIR MATCH\n"
@@ -4247,7 +4325,7 @@ TEST(24_NodesRemovedButConnectedInOther)
     "match_nets $I7 $I7\n"
     "match_nets $I6 $I6\n"
     "match_nets $I5 $I5\n"
-    "match_nets $I21 $I13\n"
+    "match_nets $I13 $I21\n"
     "match_nets FB FB\n"
     "match_nets VSS VSS\n"
     "match_nets VDD VDD\n"
@@ -4267,6 +4345,62 @@ TEST(24_NodesRemovedButConnectedInOther)
     "end_circuit RINGO RINGO MATCH"
   );
   EXPECT_EQ (good, true);
+
+
+  logger.clear ();
+  good = comp.compare (&nl2, &nl1);
+
+  txt = logger.text ();
+
+  //  NOTE: additional nets are ignored in the first netlist but not from the second
+  EXPECT_EQ (txt,
+    "begin_circuit INV2 INV2\n"
+    "match_nets VDD VDD\n"
+    "match_nets OUT OUT\n"
+    "match_nets $3 $3\n"
+    "match_nets IN IN\n"
+    "match_nets VSS VSS\n"
+    "match_nets (null) $1\n"
+    "match_nets (null) BULK\n"
+    "match_pins IN IN\n"
+    "match_pins $1 $2\n"
+    "match_pins OUT OUT\n"
+    "match_pins VSS VSS\n"
+    "match_pins VDD VDD\n"
+    "match_pins (null) $0\n"
+    "match_pins (null) BULK\n"
+    "match_devices $1 $1\n"
+    "match_devices $2 $2\n"
+    "match_devices $3 $3\n"
+    "match_devices $4 $4\n"
+    "end_circuit INV2 INV2 MATCH\n"
+    "begin_circuit INV2PAIR INV2PAIR\n"
+    "match_nets $I2 $I2\n"
+    "match_nets $I5 $I6\n"
+    "match_nets $I8 $I8\n"
+    "match_nets $I7 $I7\n"
+    "net_mismatch $I6 $I4\n"
+    "net_mismatch $I4 (null)\n"
+    "net_mismatch $I3 (null)\n"
+    "net_mismatch (null) BULK\n"
+    "net_mismatch (null) $I5\n"
+    "net_mismatch (null) $I3\n"
+    "net_mismatch (null) $I1\n"
+    "match_pins $0 $1\n"
+    "match_pins $1 $2\n"
+    "match_pins $4 $5\n"
+    "pin_mismatch $2 (null)\n"
+    "pin_mismatch $3 (null)\n"
+    "pin_mismatch (null) BULK\n"
+    "pin_mismatch (null) $3\n"
+    "pin_mismatch (null) $4\n"
+    "pin_mismatch (null) $6\n"
+    "subcircuit_mismatch $1 $1\n"
+    "subcircuit_mismatch $2 $2\n"
+    "end_circuit INV2PAIR INV2PAIR NOMATCH\n"
+    "circuit_skipped RINGO RINGO"
+  );
+  EXPECT_EQ (good, false);
 }
 
 TEST(25_JoinSymmetricNets)
diff --git a/src/lay/lay/layTechSetupDialog.cc b/src/lay/lay/layTechSetupDialog.cc
index 6ab86f668..17c7ef644 100644
--- a/src/lay/lay/layTechSetupDialog.cc
+++ b/src/lay/lay/layTechSetupDialog.cc
@@ -708,7 +708,7 @@ TechSetupDialog::update ()
 }
 
 int
-TechSetupDialog::exec (db::Technologies &technologies)
+TechSetupDialog::exec_dialog (db::Technologies &technologies)
 {
   if (s_first_show) {
     TipDialog td (this,
diff --git a/src/lay/lay/layTechSetupDialog.h b/src/lay/lay/layTechSetupDialog.h
index 03b608e4b..27bf8b3fb 100644
--- a/src/lay/lay/layTechSetupDialog.h
+++ b/src/lay/lay/layTechSetupDialog.h
@@ -149,7 +149,7 @@ public:
   TechSetupDialog (QWidget *parent);
   ~TechSetupDialog ();
 
-  int exec (db::Technologies &technologies);
+  int exec_dialog (db::Technologies &technologies);
 
 protected slots:
   void current_tech_changed (QTreeWidgetItem *current, QTreeWidgetItem *previous);
diff --git a/src/lay/lay/layTechnologyController.cc b/src/lay/lay/layTechnologyController.cc
index 441163065..883869709 100644
--- a/src/lay/lay/layTechnologyController.cc
+++ b/src/lay/lay/layTechnologyController.cc
@@ -436,7 +436,7 @@ TechnologyController::show_editor ()
 {
   db::Technologies new_tech = *db::Technologies ().instance ();
 
-  if (mp_editor && mp_editor->exec (new_tech)) {
+  if (mp_editor && mp_editor->exec_dialog (new_tech)) {
 
     std::string err_msg;
 
diff --git a/src/laybasic/laybasic/layLibrariesView.cc b/src/laybasic/laybasic/layLibrariesView.cc
index 55cff7d47..e80568f15 100644
--- a/src/laybasic/laybasic/layLibrariesView.cc
+++ b/src/laybasic/laybasic/layLibrariesView.cc
@@ -669,7 +669,7 @@ LibrariesView::do_update_content (int lib_index)
     mp_cell_lists.pop_back ();
   }
 
-  for (size_t i = imin; i < m_libraries.size () && i < mp_selector->count () && i <= imax; ++i) {
+  for (size_t i = imin; i < m_libraries.size () && i < size_t (mp_selector->count ()) && i <= imax; ++i) {
     mp_selector->setItemText (int (i), tl::to_qstring (display_string (int (i))));
   }
   while (mp_selector->count () < int (m_libraries.size ())) {
diff --git a/src/lvs/unit_tests/lvsSimpleTests.cc b/src/lvs/unit_tests/lvsSimpleTests.cc
index 2ce66d2b2..bb8e3b4c6 100644
--- a/src/lvs/unit_tests/lvsSimpleTests.cc
+++ b/src/lvs/unit_tests/lvsSimpleTests.cc
@@ -241,3 +241,23 @@ TEST(26_enableWandL)
   run_test (_this, "enable_wl2", "resistor.gds");
   run_test (_this, "enable_wl3", "resistor.gds");
 }
+
+TEST(27_BlackBoxDevicesWithAlign)
+{
+  run_test (_this, "bbdevices1", "bbdevices1.gds");
+  run_test (_this, "bbdevices2", "bbdevices2.gds");
+  run_test (_this, "bbdevices3", "bbdevices3.gds");
+  run_test (_this, "bbdevices4", "bbdevices4.gds");
+  run_test (_this, "bbdevices5", "bbdevices5.gds");
+  run_test (_this, "bbdevices6", "bbdevices6.gds");
+}
+
+TEST(28_BlackBoxDevicesWithBlank)
+{
+  run_test (_this, "bbdevices1b", "bbdevices1.gds");
+  run_test (_this, "bbdevices2b", "bbdevices2.gds");
+  run_test (_this, "bbdevices3b", "bbdevices3.gds");
+  run_test (_this, "bbdevices4b", "bbdevices4.gds");
+  run_test (_this, "bbdevices5b", "bbdevices5.gds");
+  run_test (_this, "bbdevices6b", "bbdevices6.gds");
+}
diff --git a/src/plugins/streamers/dxf/db_plugin/dbDXFReader.cc b/src/plugins/streamers/dxf/db_plugin/dbDXFReader.cc
index 8b0d598af..56b5113c2 100644
--- a/src/plugins/streamers/dxf/db_plugin/dbDXFReader.cc
+++ b/src/plugins/streamers/dxf/db_plugin/dbDXFReader.cc
@@ -3037,7 +3037,7 @@ DXFReader::read_int64 ()
     if (! ex.try_read (x) || ! ex.at_end ()) {
       error ("Expected an ASCII numerical value");
     }
-    if (x < std::numeric_limits<long long>::min() || x > std::numeric_limits<long long>::max()) {
+    if (x < double (std::numeric_limits<long long>::min()) || x > double (std::numeric_limits<long long>::max())) {
       error ("Value is out of limits for a 64 bit signed integer");
     }
     return (long long) x;
diff --git a/src/plugins/tools/net_tracer/lay_plugin/layNetTracerDialog.cc b/src/plugins/tools/net_tracer/lay_plugin/layNetTracerDialog.cc
index 7b8b24dc8..3c7da9d8b 100644
--- a/src/plugins/tools/net_tracer/lay_plugin/layNetTracerDialog.cc
+++ b/src/plugins/tools/net_tracer/lay_plugin/layNetTracerDialog.cc
@@ -1428,7 +1428,7 @@ NetTracerDialog::get_trace_depth()
     QString depth = depth_le->text ().trimmed ();
     if (! depth.isEmpty ()) {
       tl::from_string (tl::to_string (depth), n);
-      if (n < 0 || n > std::numeric_limits<size_t>::max ()) {
+      if (n < 0 || n > double (std::numeric_limits<size_t>::max ())) {
         n = 0.0;
       }
     }
diff --git a/testdata/lvs/bbdevices.net b/testdata/lvs/bbdevices.net
new file mode 100644
index 000000000..5c07dde5c
--- /dev/null
+++ b/testdata/lvs/bbdevices.net
@@ -0,0 +1,32 @@
+.SUBCKT TESTALL
+
+XUFBGA A1 B1 FBGATEST
+XUFWB C1 G1 FWBTEST
+XUFDP B1 C1 FDPTEST
+XUDP C1 D1 DPTEST
+XUBDP D1 E1 BDPTEST
+XUBWB D1 H1 BWBTEST
+XUBBGA E1 F1 BBGATEST
+
+.SUBCKT FBGATEST A B
+.ENDS
+
+.SUBCKT FWBTEST A B
+.ENDS
+
+.SUBCKT FDPTEST A B
+.ENDS
+
+.SUBCKT DPTEST A B
+.ENDS
+
+.SUBCKT BDPTEST A B
+.ENDS
+
+.SUBCKT BWBTEST A B
+.ENDS
+
+.SUBCKT BBGATEST A B
+.ENDS
+
+.ENDS
diff --git a/testdata/lvs/bbdevices1.cir b/testdata/lvs/bbdevices1.cir
new file mode 100644
index 000000000..80ce62dca
--- /dev/null
+++ b/testdata/lvs/bbdevices1.cir
@@ -0,0 +1,75 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $10 r0 *1 0,0
+X$10 3 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 4 BBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+* net 1 A
+* net 2 B
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 2
+* net 1 B
+* net 2 A
+* net 3 BBGATEST
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+* net 1 B
+* net 2 A
+* net 3 FBGATEST
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 FWBTEST
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin A
+.SUBCKT BWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 BWBTEST
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices1.gds b/testdata/lvs/bbdevices1.gds
new file mode 100644
index 000000000..221cc5514
Binary files /dev/null and b/testdata/lvs/bbdevices1.gds differ
diff --git a/testdata/lvs/bbdevices1.lvs b/testdata/lvs/bbdevices1.lvs
new file mode 100644
index 000000000..cb4938f40
--- /dev/null
+++ b/testdata/lvs/bbdevices1.lvs
@@ -0,0 +1,74 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+align
+
+compare
diff --git a/testdata/lvs/bbdevices1.lvsdb b/testdata/lvs/bbdevices1.lvsdb
new file mode 100644
index 000000000..cb3ae8cc0
--- /dev/null
+++ b/testdata/lvs/bbdevices1.lvsdb
@@ -0,0 +1,464 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (832000 -242000) (93500 75500))
+   rect(l15 (-46751 -37751) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (576500 -249000) (105500 81500))
+   rect(l15 (-52751 -40751) (2 2))
+  )
+  net(3 name(BWBTEST)
+   rect(l15 (754499 -114001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (793500 427000) (120500 82000))
+   rect(l3 (-60251 -41001) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (572500 432500) (74500 73500))
+   rect(l3 (-37251 -36751) (2 2))
+  )
+  net(3 name(FWBTEST)
+   rect(l3 (797999 565499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (-221000 412500) (162000 152500))
+   rect(l3 (-81001 -76251) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (-449500 422500) (146000 144500))
+   rect(l3 (-71001 -71251) (2 2))
+  )
+  net(3 name(FBGATEST)
+   rect(l3 (-417001 610499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (-468000 -280000) (177000 189000))
+   rect(l15 (-88501 -94501) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (-218500 -290000) (193000 203000))
+   rect(l15 (-94001 -101501) (2 2))
+  )
+  net(3 name(BBGATEST)
+   rect(l15 (-422001 -313001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l16 (317000 -232000) (92000 92000))
+   rect(l16 (-46001 -46001) (2 2))
+  )
+  net(2 name(B)
+   rect(l16 (95500 -231000) (116000 97000))
+   rect(l16 (-58001 -48501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l11 (323000 151500) (76000 83000))
+   rect(l11 (-38001 -41501) (2 2))
+  )
+  net(2 name(A)
+   rect(l11 (96500 159500) (90000 73000))
+   rect(l11 (-45001 -36501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l1 (327000 436500) (72000 93000))
+   rect(l1 (-36001 -46501) (2 2))
+  )
+  net(2 name(A)
+   rect(l1 (101500 443500) (82000 84000))
+   rect(l1 (-41001 -42001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-270500 7500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(10 BWBTEST location(0 0) pin(0 3))
+  circuit(14 BBGATEST location(0 0) pin(0 4))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   net(() 1 match)
+   net(1 2 match)
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL match
+  xref(
+   net(2 2 match)
+   net(1 3 match)
+   net(3 5 match)
+   net(4 6 match)
+   circuit(14 7 match)
+   circuit(9 5 match)
+   circuit(10 6 match)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices1b.cir b/testdata/lvs/bbdevices1b.cir
new file mode 100644
index 000000000..82dcb589b
--- /dev/null
+++ b/testdata/lvs/bbdevices1b.cir
@@ -0,0 +1,57 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $10 r0 *1 0,0
+X$10 3 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 4 BBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 1
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 1
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin A
+.SUBCKT BWBTEST 1
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices1b.lvs b/testdata/lvs/bbdevices1b.lvs
new file mode 100644
index 000000000..cba829291
--- /dev/null
+++ b/testdata/lvs/bbdevices1b.lvs
@@ -0,0 +1,75 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+blank_circuit("*TEST")
+netlist.simplify
+
+compare
diff --git a/testdata/lvs/bbdevices1b.lvsdb b/testdata/lvs/bbdevices1b.lvsdb
new file mode 100644
index 000000000..30d688cef
--- /dev/null
+++ b/testdata/lvs/bbdevices1b.lvsdb
@@ -0,0 +1,340 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-270500 7500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(10 BWBTEST location(0 0) pin(0 3))
+  circuit(14 BBGATEST location(0 0) pin(0 4))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL match
+  xref(
+   net(2 2 match)
+   net(1 3 match)
+   net(3 5 match)
+   net(4 6 match)
+   circuit(14 7 match)
+   circuit(9 5 match)
+   circuit(10 6 match)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices2.cir b/testdata/lvs/bbdevices2.cir
new file mode 100644
index 000000000..bac395789
--- /dev/null
+++ b/testdata/lvs/bbdevices2.cir
@@ -0,0 +1,79 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 4 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 5 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 3 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 5 6 BDPTEST
+* cell instance $10 r0 *1 0,0
+X$10 8 5 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 7 6 BBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+* net 1 A
+* net 2 B
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin B
+* pin A
+.SUBCKT BBGATEST 1 2
+* net 1 B
+* net 2 A
+* net 3 BBGATEST
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+* pin A
+.SUBCKT FBGATEST 1 2
+* net 1 B
+* net 2 A
+* net 3 FBGATEST
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin B
+* pin A
+.SUBCKT FWBTEST 1 2
+* net 1 B
+* net 2 A
+* net 3 FWBTEST
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin B
+* pin A
+.SUBCKT BWBTEST 1 2
+* net 1 B
+* net 2 A
+* net 3 BWBTEST
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices2.gds b/testdata/lvs/bbdevices2.gds
new file mode 100644
index 000000000..45c7268ad
Binary files /dev/null and b/testdata/lvs/bbdevices2.gds differ
diff --git a/testdata/lvs/bbdevices2.lvs b/testdata/lvs/bbdevices2.lvs
new file mode 100644
index 000000000..cb4938f40
--- /dev/null
+++ b/testdata/lvs/bbdevices2.lvs
@@ -0,0 +1,74 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+align
+
+compare
diff --git a/testdata/lvs/bbdevices2.lvsdb b/testdata/lvs/bbdevices2.lvsdb
new file mode 100644
index 000000000..5a782379a
--- /dev/null
+++ b/testdata/lvs/bbdevices2.lvsdb
@@ -0,0 +1,496 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (832000 -242000) (93500 75500))
+   rect(l15 (-46751 -37751) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (576500 -249000) (105500 81500))
+   rect(l15 (-52751 -40751) (2 2))
+  )
+  net(3 name(BWBTEST)
+   rect(l15 (754499 -114001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (793500 427000) (120500 82000))
+   rect(l3 (-60251 -41001) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (572500 432500) (74500 73500))
+   rect(l3 (-37251 -36751) (2 2))
+  )
+  net(3 name(FWBTEST)
+   rect(l3 (797999 565499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (-221000 412500) (162000 152500))
+   rect(l3 (-81001 -76251) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (-449500 422500) (146000 144500))
+   rect(l3 (-71001 -71251) (2 2))
+  )
+  net(3 name(FBGATEST)
+   rect(l3 (-417001 610499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (-468000 -280000) (177000 189000))
+   rect(l15 (-88501 -94501) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (-218500 -290000) (193000 203000))
+   rect(l15 (-94001 -101501) (2 2))
+  )
+  net(3 name(BBGATEST)
+   rect(l15 (-422001 -313001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l16 (317000 -232000) (92000 92000))
+   rect(l16 (-46001 -46001) (2 2))
+  )
+  net(2 name(B)
+   rect(l16 (95500 -231000) (116000 97000))
+   rect(l16 (-58001 -48501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l11 (323000 151500) (76000 83000))
+   rect(l11 (-38001 -41501) (2 2))
+  )
+  net(2 name(A)
+   rect(l11 (96500 159500) (90000 73000))
+   rect(l11 (-45001 -36501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l1 (327000 436500) (72000 93000))
+   rect(l1 (-36001 -46501) (2 2))
+  )
+  net(2 name(A)
+   rect(l1 (101500 443500) (82000 84000))
+   rect(l1 (-41001 -42001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l2 (-401420 456500) (50730 78500))
+  )
+  net(4
+   rect(l2 (822690 427000) (63970 82000))
+  )
+  net(5
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-270500 7500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(6
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+  net(7
+   rect(l14 (-410240 -216150) (83240 87150))
+  )
+  net(8
+   rect(l14 (846960 -242000) (77190 75500))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0)
+   pin(0 4)
+   pin(1 1)
+  )
+  circuit(7 DPTEST location(0 0)
+   pin(0 5)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(9 BDPTEST location(0 0)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(10 BWBTEST location(0 0)
+   pin(0 8)
+   pin(1 5)
+  )
+  circuit(14 BBGATEST location(0 0)
+   pin(0 7)
+   pin(1 6)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(testall TESTALL match
+  xref(
+   net(3 1 match)
+   net(2 2 match)
+   net(1 3 match)
+   net(5 5 match)
+   net(6 6 match)
+   net(7 8 match)
+   net(4 4 match)
+   net(8 7 match)
+   circuit(14 7 match)
+   circuit(9 5 match)
+   circuit(10 6 match)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices2b.cir b/testdata/lvs/bbdevices2b.cir
new file mode 100644
index 000000000..c47a97097
--- /dev/null
+++ b/testdata/lvs/bbdevices2b.cir
@@ -0,0 +1,61 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 4 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 5 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 3 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 5 6 BDPTEST
+* cell instance $10 r0 *1 0,0
+X$10 8 5 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 7 6 BBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin B
+* pin A
+.SUBCKT BBGATEST 1 2
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+* pin A
+.SUBCKT FBGATEST 1 2
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin B
+* pin A
+.SUBCKT FWBTEST 1 2
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin B
+* pin A
+.SUBCKT BWBTEST 1 2
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices2b.lvs b/testdata/lvs/bbdevices2b.lvs
new file mode 100644
index 000000000..cba829291
--- /dev/null
+++ b/testdata/lvs/bbdevices2b.lvs
@@ -0,0 +1,75 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+blank_circuit("*TEST")
+netlist.simplify
+
+compare
diff --git a/testdata/lvs/bbdevices2b.lvsdb b/testdata/lvs/bbdevices2b.lvsdb
new file mode 100644
index 000000000..5e44f84c1
--- /dev/null
+++ b/testdata/lvs/bbdevices2b.lvsdb
@@ -0,0 +1,372 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l2 (-401420 456500) (50730 78500))
+  )
+  net(4
+   rect(l2 (822690 427000) (63970 82000))
+  )
+  net(5
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-270500 7500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(6
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+  net(7
+   rect(l14 (-410240 -216150) (83240 87150))
+  )
+  net(8
+   rect(l14 (846960 -242000) (77190 75500))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0)
+   pin(0 4)
+   pin(1 1)
+  )
+  circuit(7 DPTEST location(0 0)
+   pin(0 5)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(9 BDPTEST location(0 0)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(10 BWBTEST location(0 0)
+   pin(0 8)
+   pin(1 5)
+  )
+  circuit(14 BBGATEST location(0 0)
+   pin(0 7)
+   pin(1 6)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(testall TESTALL match
+  xref(
+   net(3 1 match)
+   net(2 2 match)
+   net(1 3 match)
+   net(5 5 match)
+   net(6 6 match)
+   net(7 8 match)
+   net(4 4 match)
+   net(8 7 match)
+   circuit(14 7 match)
+   circuit(9 5 match)
+   circuit(10 6 match)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices3.cir b/testdata/lvs/bbdevices3.cir
new file mode 100644
index 000000000..82abe4cee
--- /dev/null
+++ b/testdata/lvs/bbdevices3.cir
@@ -0,0 +1,75 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $10 r0 *1 0,0
+X$10 3 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 4 BBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+* net 1 A
+* net 2 B
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 2
+* net 1 B
+* net 2 A
+* net 3 BBGATEST
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+* net 1 B
+* net 2 A
+* net 3 FBGATEST
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 FWBTEST
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin B
+.SUBCKT BWBTEST 1
+* net 1 B
+* net 2 A
+* net 3 BWBTEST
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices3.gds b/testdata/lvs/bbdevices3.gds
new file mode 100644
index 000000000..07ea60b33
Binary files /dev/null and b/testdata/lvs/bbdevices3.gds differ
diff --git a/testdata/lvs/bbdevices3.lvs b/testdata/lvs/bbdevices3.lvs
new file mode 100644
index 000000000..cb4938f40
--- /dev/null
+++ b/testdata/lvs/bbdevices3.lvs
@@ -0,0 +1,74 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+align
+
+compare
diff --git a/testdata/lvs/bbdevices3.lvsdb b/testdata/lvs/bbdevices3.lvsdb
new file mode 100644
index 000000000..e870f11be
--- /dev/null
+++ b/testdata/lvs/bbdevices3.lvsdb
@@ -0,0 +1,465 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (586500 -242000) (93500 75500))
+   rect(l15 (-46751 -37751) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (830000 -249000) (105500 81500))
+   rect(l15 (-52751 -40751) (2 2))
+  )
+  net(3 name(BWBTEST)
+   rect(l15 (757499 -114001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (793500 427000) (120500 82000))
+   rect(l3 (-60251 -41001) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (572500 432500) (74500 73500))
+   rect(l3 (-37251 -36751) (2 2))
+  )
+  net(3 name(FWBTEST)
+   rect(l3 (797999 565499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (-221000 412500) (162000 152500))
+   rect(l3 (-81001 -76251) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (-449500 422500) (146000 144500))
+   rect(l3 (-71001 -71251) (2 2))
+  )
+  net(3 name(FBGATEST)
+   rect(l3 (-417001 610499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (-468000 -280000) (177000 189000))
+   rect(l15 (-88501 -94501) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (-218500 -290000) (193000 203000))
+   rect(l15 (-94001 -101501) (2 2))
+  )
+  net(3 name(BBGATEST)
+   rect(l15 (-422001 -313001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l16 (317000 -232000) (92000 92000))
+   rect(l16 (-46001 -46001) (2 2))
+  )
+  net(2 name(B)
+   rect(l16 (95500 -231000) (116000 97000))
+   rect(l16 (-58001 -48501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l11 (323000 151500) (76000 83000))
+   rect(l11 (-38001 -41501) (2 2))
+  )
+  net(2 name(A)
+   rect(l11 (96500 159500) (90000 73000))
+   rect(l11 (-45001 -36501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l1 (327000 436500) (72000 93000))
+   rect(l1 (-36001 -46501) (2 2))
+  )
+  net(2 name(A)
+   rect(l1 (101500 443500) (82000 84000))
+   rect(l1 (-41001 -42001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-270500 7500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(10 BWBTEST location(0 0) pin(0 3))
+  circuit(14 BBGATEST location(0 0) pin(0 4))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   net(() 1 match)
+   net(1 2 match)
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   net(() 1 match)
+   net(1 2 match)
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL nomatch
+  xref(
+   net(() 7 mismatch)
+   net(2 2 match)
+   net(1 3 match)
+   net(3 5 mismatch)
+   net(4 6 match)
+   circuit(14 7 match)
+   circuit(9 5 match)
+   circuit(10 6 mismatch)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices3b.cir b/testdata/lvs/bbdevices3b.cir
new file mode 100644
index 000000000..45442d14f
--- /dev/null
+++ b/testdata/lvs/bbdevices3b.cir
@@ -0,0 +1,57 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $10 r0 *1 0,0
+X$10 3 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 4 BBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 1
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 1
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin B
+.SUBCKT BWBTEST 1
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices3b.lvs b/testdata/lvs/bbdevices3b.lvs
new file mode 100644
index 000000000..cba829291
--- /dev/null
+++ b/testdata/lvs/bbdevices3b.lvs
@@ -0,0 +1,75 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+blank_circuit("*TEST")
+netlist.simplify
+
+compare
diff --git a/testdata/lvs/bbdevices3b.lvsdb b/testdata/lvs/bbdevices3b.lvsdb
new file mode 100644
index 000000000..bae0d36a5
--- /dev/null
+++ b/testdata/lvs/bbdevices3b.lvsdb
@@ -0,0 +1,329 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-270500 7500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(10 BWBTEST location(0 0) pin(0 3))
+  circuit(14 BBGATEST location(0 0) pin(0 4))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST nomatch
+  xref(
+   pin(() 0 mismatch)
+   pin(0 1 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL skipped description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n  B: BWBTEST')
+  xref(
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices4.cir b/testdata/lvs/bbdevices4.cir
new file mode 100644
index 000000000..61fcf18da
--- /dev/null
+++ b/testdata/lvs/bbdevices4.cir
@@ -0,0 +1,72 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $13 r0 *1 0,0
+X$13 4 BBGATEST
+.ENDS testall
+
+* cell BWBTEST
+.SUBCKT BWBTEST
+* net 1 B
+* net 2 A
+* net 3 BWBTEST
+.ENDS BWBTEST
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+* net 1 A
+* net 2 B
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 2
+* net 1 B
+* net 2 A
+* net 3 BBGATEST
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+* net 1 B
+* net 2 A
+* net 3 FBGATEST
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 FWBTEST
+.ENDS FWBTEST
diff --git a/testdata/lvs/bbdevices4.gds b/testdata/lvs/bbdevices4.gds
new file mode 100644
index 000000000..035b7fc2a
Binary files /dev/null and b/testdata/lvs/bbdevices4.gds differ
diff --git a/testdata/lvs/bbdevices4.lvs b/testdata/lvs/bbdevices4.lvs
new file mode 100644
index 000000000..cb4938f40
--- /dev/null
+++ b/testdata/lvs/bbdevices4.lvs
@@ -0,0 +1,74 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+align
+
+compare
diff --git a/testdata/lvs/bbdevices4.lvsdb b/testdata/lvs/bbdevices4.lvsdb
new file mode 100644
index 000000000..47cbefd91
--- /dev/null
+++ b/testdata/lvs/bbdevices4.lvsdb
@@ -0,0 +1,459 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (793500 427000) (120500 82000))
+   rect(l3 (-60251 -41001) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (572500 432500) (74500 73500))
+   rect(l3 (-37251 -36751) (2 2))
+  )
+  net(3 name(FWBTEST)
+   rect(l3 (797999 565499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (-221000 412500) (162000 152500))
+   rect(l3 (-81001 -76251) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (-449500 422500) (146000 144500))
+   rect(l3 (-71001 -71251) (2 2))
+  )
+  net(3 name(FBGATEST)
+   rect(l3 (-417001 610499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (-468000 -280000) (177000 189000))
+   rect(l15 (-88501 -94501) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (-218500 -290000) (193000 203000))
+   rect(l15 (-94001 -101501) (2 2))
+  )
+  net(3 name(BBGATEST)
+   rect(l15 (-422001 -313001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l16 (317000 -232000) (92000 92000))
+   rect(l16 (-46001 -46001) (2 2))
+  )
+  net(2 name(B)
+   rect(l16 (95500 -231000) (116000 97000))
+   rect(l16 (-58001 -48501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l11 (323000 151500) (76000 83000))
+   rect(l11 (-38001 -41501) (2 2))
+  )
+  net(2 name(A)
+   rect(l11 (96500 159500) (90000 73000))
+   rect(l11 (-45001 -36501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l1 (327000 436500) (72000 93000))
+   rect(l1 (-36001 -46501) (2 2))
+  )
+  net(2 name(A)
+   rect(l1 (101500 443500) (82000 84000))
+   rect(l1 (-41001 -42001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (832000 -242000) (93500 75500))
+   rect(l15 (-46751 -37751) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (576500 -249000) (105500 81500))
+   rect(l15 (-52751 -40751) (2 2))
+  )
+  net(3 name(BWBTEST)
+   rect(l15 (754499 -114001) (2 2))
+  )
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-25000 -193000) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(13 BBGATEST location(0 0) pin(0 4))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   net(() 1 match)
+   net(() 2 match)
+   pin(() 0 match)
+   pin(() 1 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   net(() 1 match)
+   net(1 2 match)
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL nomatch
+  xref(
+   net(2 2 match)
+   net(1 3 match)
+   net(3 5 mismatch)
+   net(4 6 match)
+   circuit(() 6 mismatch)
+   circuit(13 7 match)
+   circuit(9 5 match)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices4b.cir b/testdata/lvs/bbdevices4b.cir
new file mode 100644
index 000000000..ab5462ce3
--- /dev/null
+++ b/testdata/lvs/bbdevices4b.cir
@@ -0,0 +1,54 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $13 r0 *1 0,0
+X$13 4 BBGATEST
+.ENDS testall
+
+* cell BWBTEST
+.SUBCKT BWBTEST
+.ENDS BWBTEST
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 1
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 1
+.ENDS FWBTEST
diff --git a/testdata/lvs/bbdevices4b.lvs b/testdata/lvs/bbdevices4b.lvs
new file mode 100644
index 000000000..cba829291
--- /dev/null
+++ b/testdata/lvs/bbdevices4b.lvs
@@ -0,0 +1,75 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+blank_circuit("*TEST")
+netlist.simplify
+
+compare
diff --git a/testdata/lvs/bbdevices4b.lvsdb b/testdata/lvs/bbdevices4b.lvsdb
new file mode 100644
index 000000000..e26fe15c3
--- /dev/null
+++ b/testdata/lvs/bbdevices4b.lvsdb
@@ -0,0 +1,324 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-25000 -193000) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(13 BBGATEST location(0 0) pin(0 4))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST nomatch
+  xref(
+   pin(() 0 mismatch)
+   pin(() 1 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL skipped description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n  B: BWBTEST')
+  xref(
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices5.cir b/testdata/lvs/bbdevices5.cir
new file mode 100644
index 000000000..de64bad72
--- /dev/null
+++ b/testdata/lvs/bbdevices5.cir
@@ -0,0 +1,75 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $13 r0 *1 0,0
+X$13 4 BBGATEST
+* cell instance $14 r0 *1 0,0
+X$14 5 BWBTEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+* net 1 A
+* net 2 B
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 2
+* net 1 B
+* net 2 A
+* net 3 BBGATEST
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+* net 1 B
+* net 2 A
+* net 3 FBGATEST
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 FWBTEST
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin A
+.SUBCKT BWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 BWBTEST
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices5.gds b/testdata/lvs/bbdevices5.gds
new file mode 100644
index 000000000..0b3d8a90e
Binary files /dev/null and b/testdata/lvs/bbdevices5.gds differ
diff --git a/testdata/lvs/bbdevices5.lvs b/testdata/lvs/bbdevices5.lvs
new file mode 100644
index 000000000..cb4938f40
--- /dev/null
+++ b/testdata/lvs/bbdevices5.lvs
@@ -0,0 +1,74 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+align
+
+compare
diff --git a/testdata/lvs/bbdevices5.lvsdb b/testdata/lvs/bbdevices5.lvsdb
new file mode 100644
index 000000000..cf5b49052
--- /dev/null
+++ b/testdata/lvs/bbdevices5.lvsdb
@@ -0,0 +1,469 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (832000 -242000) (93500 75500))
+   rect(l15 (-46751 -37751) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (576500 -249000) (105500 81500))
+   rect(l15 (-52751 -40751) (2 2))
+  )
+  net(3 name(BWBTEST)
+   rect(l15 (754499 -114001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (793500 427000) (120500 82000))
+   rect(l3 (-60251 -41001) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (572500 432500) (74500 73500))
+   rect(l3 (-37251 -36751) (2 2))
+  )
+  net(3 name(FWBTEST)
+   rect(l3 (797999 565499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (-221000 412500) (162000 152500))
+   rect(l3 (-81001 -76251) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (-449500 422500) (146000 144500))
+   rect(l3 (-71001 -71251) (2 2))
+  )
+  net(3 name(FBGATEST)
+   rect(l3 (-417001 610499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (-468000 -280000) (177000 189000))
+   rect(l15 (-88501 -94501) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (-218500 -290000) (193000 203000))
+   rect(l15 (-94001 -101501) (2 2))
+  )
+  net(3 name(BBGATEST)
+   rect(l15 (-422001 -313001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l16 (317000 -232000) (92000 92000))
+   rect(l16 (-46001 -46001) (2 2))
+  )
+  net(2 name(B)
+   rect(l16 (95500 -231000) (116000 97000))
+   rect(l16 (-58001 -48501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l11 (323000 151500) (76000 83000))
+   rect(l11 (-38001 -41501) (2 2))
+  )
+  net(2 name(A)
+   rect(l11 (96500 159500) (90000 73000))
+   rect(l11 (-45001 -36501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l1 (327000 436500) (72000 93000))
+   rect(l1 (-36001 -46501) (2 2))
+  )
+  net(2 name(A)
+   rect(l1 (101500 443500) (82000 84000))
+   rect(l1 (-41001 -42001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-25000 -193000) (25000 193000))
+   rect(l14 (-24000 -225500) (118960 25000))
+   rect(l14 (-182460 113000) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+  net(5
+   rect(l14 (509690 -219000) (113310 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(13 BBGATEST location(0 0) pin(0 4))
+  circuit(14 BWBTEST location(0 0) pin(0 5))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   net(() 1 match)
+   net(1 2 match)
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL nomatch
+  xref(
+   net(5 () mismatch)
+   net(2 2 match)
+   net(1 3 match)
+   net(3 5 mismatch)
+   net(4 6 match)
+   circuit(() 6 mismatch)
+   circuit(13 7 match)
+   circuit(9 5 match)
+   circuit(14 () mismatch)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices5b.cir b/testdata/lvs/bbdevices5b.cir
new file mode 100644
index 000000000..964a8d4b2
--- /dev/null
+++ b/testdata/lvs/bbdevices5b.cir
@@ -0,0 +1,57 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 2 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 3 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 FBGATEST
+* cell instance $9 r0 *1 0,0
+X$9 3 4 BDPTEST
+* cell instance $13 r0 *1 0,0
+X$13 4 BBGATEST
+* cell instance $14 r0 *1 0,0
+X$14 5 BWBTEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 1
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 1
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin A
+.SUBCKT BWBTEST 1
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices5b.lvs b/testdata/lvs/bbdevices5b.lvs
new file mode 100644
index 000000000..cba829291
--- /dev/null
+++ b/testdata/lvs/bbdevices5b.lvs
@@ -0,0 +1,75 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+blank_circuit("*TEST")
+netlist.simplify
+
+compare
diff --git a/testdata/lvs/bbdevices5b.lvsdb b/testdata/lvs/bbdevices5b.lvsdb
new file mode 100644
index 000000000..624a9a521
--- /dev/null
+++ b/testdata/lvs/bbdevices5b.lvsdb
@@ -0,0 +1,345 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+  net(3
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-25000 -193000) (25000 193000))
+   rect(l14 (-24000 -225500) (118960 25000))
+   rect(l14 (-182460 113000) (150000 150000))
+  )
+  net(4
+   rect(l14 (-126000 -195000) (292000 25000))
+  )
+  net(5
+   rect(l14 (509690 -219000) (113310 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 3)
+   pin(1 1)
+  )
+  circuit(8 FBGATEST location(0 0) pin(0 2))
+  circuit(9 BDPTEST location(0 0)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(13 BBGATEST location(0 0) pin(0 4))
+  circuit(14 BWBTEST location(0 0) pin(0 5))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL nomatch
+  xref(
+   net(5 () mismatch)
+   net(2 2 match)
+   net(1 3 match)
+   net(3 5 mismatch)
+   net(4 6 match)
+   circuit(() 6 mismatch)
+   circuit(13 7 match)
+   circuit(9 5 match)
+   circuit(14 () mismatch)
+   circuit(7 4 match)
+   circuit(8 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices6.cir b/testdata/lvs/bbdevices6.cir
new file mode 100644
index 000000000..39fba7dc1
--- /dev/null
+++ b/testdata/lvs/bbdevices6.cir
@@ -0,0 +1,75 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 3 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 2 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 2 BDPTEST
+* cell instance $9 r0 *1 0,0
+X$9 2 BBGATEST
+* cell instance $10 r0 *1 0,0
+X$10 2 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 3 FBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+* net 1 B
+* net 2 A
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+* net 1 A
+* net 2 B
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 2
+* net 1 B
+* net 2 A
+* net 3 BBGATEST
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+* net 1 B
+* net 2 A
+* net 3 FBGATEST
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 FWBTEST
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin A
+.SUBCKT BWBTEST 2
+* net 1 B
+* net 2 A
+* net 3 BWBTEST
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices6.gds b/testdata/lvs/bbdevices6.gds
new file mode 100644
index 000000000..f40e24516
Binary files /dev/null and b/testdata/lvs/bbdevices6.gds differ
diff --git a/testdata/lvs/bbdevices6.lvs b/testdata/lvs/bbdevices6.lvs
new file mode 100644
index 000000000..cb4938f40
--- /dev/null
+++ b/testdata/lvs/bbdevices6.lvs
@@ -0,0 +1,74 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+align
+
+compare
diff --git a/testdata/lvs/bbdevices6.lvsdb b/testdata/lvs/bbdevices6.lvsdb
new file mode 100644
index 000000000..09a133d7a
--- /dev/null
+++ b/testdata/lvs/bbdevices6.lvsdb
@@ -0,0 +1,463 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (832000 -242000) (93500 75500))
+   rect(l15 (-46751 -37751) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (576500 -249000) (105500 81500))
+   rect(l15 (-52751 -40751) (2 2))
+  )
+  net(3 name(BWBTEST)
+   rect(l15 (754499 -114001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (793500 427000) (120500 82000))
+   rect(l3 (-60251 -41001) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (572500 432500) (74500 73500))
+   rect(l3 (-37251 -36751) (2 2))
+  )
+  net(3 name(FWBTEST)
+   rect(l3 (797999 565499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l3 (-221000 412500) (162000 152500))
+   rect(l3 (-81001 -76251) (2 2))
+  )
+  net(2 name(A)
+   rect(l3 (-449500 422500) (146000 144500))
+   rect(l3 (-71001 -71251) (2 2))
+  )
+  net(3 name(FBGATEST)
+   rect(l3 (-417001 610499) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l15 (-468000 -280000) (177000 189000))
+   rect(l15 (-88501 -94501) (2 2))
+  )
+  net(2 name(A)
+   rect(l15 (-218500 -290000) (193000 203000))
+   rect(l15 (-94001 -101501) (2 2))
+  )
+  net(3 name(BBGATEST)
+   rect(l15 (-422001 -313001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(2 name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l16 (317000 -232000) (92000 92000))
+   rect(l16 (-46001 -46001) (2 2))
+  )
+  net(2 name(B)
+   rect(l16 (95500 -231000) (116000 97000))
+   rect(l16 (-58001 -48501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l11 (323000 151500) (76000 83000))
+   rect(l11 (-38001 -41501) (2 2))
+  )
+  net(2 name(A)
+   rect(l11 (96500 159500) (90000 73000))
+   rect(l11 (-45001 -36501) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l1 (327000 436500) (72000 93000))
+   rect(l1 (-36001 -46501) (2 2))
+  )
+  net(2 name(A)
+   rect(l1 (101500 443500) (82000 84000))
+   rect(l1 (-41001 -42001) (2 2))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-457140 -10680) (187640 34680))
+   rect(l14 (-479500 -25000) (292000 25000))
+   rect(l14 (186500 -16500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(3
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 3)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 2)
+   pin(1 1)
+  )
+  circuit(8 BDPTEST location(0 0)
+   pin(0 2)
+   pin(1 2)
+  )
+  circuit(9 BBGATEST location(0 0) pin(0 2))
+  circuit(10 BWBTEST location(0 0) pin(0 2))
+  circuit(14 FBGATEST location(0 0) pin(0 3))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(DPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   net(() 1 match)
+   net(1 2 match)
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   net(2 1 match)
+   net(1 2 match)
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   net(() 2 match)
+   net(2 1 match)
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL nomatch
+  xref(
+   net(() 6 mismatch)
+   net(3 2 match)
+   net(1 3 match)
+   net(2 5 mismatch)
+   circuit(9 7 mismatch)
+   circuit(8 5 mismatch)
+   circuit(10 6 match)
+   circuit(7 4 match)
+   circuit(14 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/bbdevices6b.cir b/testdata/lvs/bbdevices6b.cir
new file mode 100644
index 000000000..d3d48a01c
--- /dev/null
+++ b/testdata/lvs/bbdevices6b.cir
@@ -0,0 +1,57 @@
+* Extracted by KLayout
+
+* cell testall
+.SUBCKT testall
+* cell instance $2 r0 *1 0,0
+X$2 1 3 FDPTEST
+* cell instance $3 r0 *1 0,0
+X$3 1 FWBTEST
+* cell instance $7 r0 *1 0,0
+X$7 2 1 DPTEST
+* cell instance $8 r0 *1 0,0
+X$8 2 2 BDPTEST
+* cell instance $9 r0 *1 0,0
+X$9 2 BBGATEST
+* cell instance $10 r0 *1 0,0
+X$10 2 BWBTEST
+* cell instance $14 r0 *1 0,0
+X$14 3 FBGATEST
+.ENDS testall
+
+* cell FDPTEST
+* pin B
+* pin A
+.SUBCKT FDPTEST 1 2
+.ENDS FDPTEST
+
+* cell DPTEST
+* pin B
+* pin A
+.SUBCKT DPTEST 1 2
+.ENDS DPTEST
+
+* cell BDPTEST
+* pin A
+* pin B
+.SUBCKT BDPTEST 1 2
+.ENDS BDPTEST
+
+* cell BBGATEST
+* pin A
+.SUBCKT BBGATEST 1
+.ENDS BBGATEST
+
+* cell FBGATEST
+* pin B
+.SUBCKT FBGATEST 1
+.ENDS FBGATEST
+
+* cell FWBTEST
+* pin A
+.SUBCKT FWBTEST 1
+.ENDS FWBTEST
+
+* cell BWBTEST
+* pin A
+.SUBCKT BWBTEST 1
+.ENDS BWBTEST
diff --git a/testdata/lvs/bbdevices6b.lvs b/testdata/lvs/bbdevices6b.lvs
new file mode 100644
index 000000000..cba829291
--- /dev/null
+++ b/testdata/lvs/bbdevices6b.lvs
@@ -0,0 +1,75 @@
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("bbdevices.net")
+
+deep
+
+class Layers 
+  attr_accessor :selected, :fdpPad, :fdp, :fsm, :ftp, :fm7, :fv7, :fm6, :fv6, :fm5, :fv5, :fm4, :fv4, :fm3, :fv3, :fm2, :fv2, :fm1, :fv1, :dpPad, :dp, :package, :tsv, :bv1, :bm1, :bv2, :bm2, :bv3, :bm3, :bv4, :bm4, :bv5, :bm5, :bv6, :bm6, :bv7, :bm7, :btp, :bsm, :bdpPad, :bdp, :text, :fm, :fv, :bm, :bv
+end
+
+layer = Layers.new
+layer.package = input(20,0)
+layer.fdp = input(70,0)
+layer.fdpPad = input(73,0)
+layer.fsm = input(45,0)
+layer.ftp = input(44,0)
+layer.fm7 = input(43,0)
+layer.fv7 = input(42,0)
+layer.fm6 = input(41,0)
+layer.fv6 = input(40,0)
+layer.fm5 = input(39,0)
+layer.fv5 = input(38,0)
+layer.fm4 = input(37,0)
+layer.fv4 = input(36,0)
+layer.fm3 = input(35,0)
+layer.fv3 = input(34,0)
+layer.fm2 = input(33,0)
+layer.fv2 = input(32,0)
+layer.fm1 = input(31,0)
+layer.fv1 = input(30,0)
+layer.dpPad = input(75,0)
+layer.dp = input(21,0)
+layer.tsv = input(19,0)
+layer.bv1 = input(50,0)
+layer.bm1 = input(51,0)
+layer.bv2 = input(52,0)
+layer.bm2 = input(53,0)
+layer.bv3 = input(54,0)
+layer.bm3 = input(55,0)
+layer.bv4 = input(56,0)
+layer.bm4 = input(57,0)
+layer.bv5 = input(58,0)
+layer.bm5 = input(59,0)
+layer.bv6 = input(60,0)
+layer.bm6 = input(61,0)
+layer.bv7 = input(62,0)
+layer.bm7 = input(63,0)
+layer.btp = input(64,0)
+layer.bsm = input(65,0)
+layer.bdpPad = input(78,0)
+layer.bdp = input(71,0)
+layer.text = input(230,0)
+
+connect(layer.fdpPad, layer.fm4)
+connect(layer.ftp, layer.fm4)
+connect(layer.fm4, layer.fv4)
+connect(layer.fv4, layer.fm3)
+connect(layer.fm3, layer.fv3)
+connect(layer.fv3, layer.fm2)
+connect(layer.fm2, layer.fv2)
+connect(layer.fv2, layer.fm1)
+connect(layer.fm1, layer.fv1)
+connect(layer.dpPad, layer.fv1)
+connect(layer.fv1, layer.tsv)
+connect(layer.tsv, layer.bv1)
+connect(layer.bv1, layer.bm1)
+connect(layer.btp, layer.bm1)
+connect(layer.bdpPad, layer.bm1)
+
+blank_circuit("*TEST")
+netlist.simplify
+
+compare
diff --git a/testdata/lvs/bbdevices6b.lvsdb b/testdata/lvs/bbdevices6b.lvsdb
new file mode 100644
index 000000000..71432c4f9
--- /dev/null
+++ b/testdata/lvs/bbdevices6b.lvsdb
@@ -0,0 +1,339 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(testall)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '73/0')
+ layer(l3 '44/0')
+ layer(l2 '37/0')
+ layer(l4 '36/0')
+ layer(l5 '35/0')
+ layer(l6 '34/0')
+ layer(l7 '33/0')
+ layer(l8 '32/0')
+ layer(l9 '31/0')
+ layer(l10 '30/0')
+ layer(l11 '75/0')
+ layer(l12 '19/0')
+ layer(l13 '50/0')
+ layer(l14 '51/0')
+ layer(l15 '64/0')
+ layer(l16 '78/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l3 l3 l2)
+ connect(l2 l1 l3 l2 l4)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5 l6)
+ connect(l6 l5 l6 l7)
+ connect(l7 l6 l7 l8)
+ connect(l8 l7 l8 l9)
+ connect(l9 l8 l9 l10)
+ connect(l10 l9 l10 l11 l12)
+ connect(l11 l10 l11)
+ connect(l12 l10 l12 l13)
+ connect(l13 l12 l13 l14)
+ connect(l14 l13 l14 l15 l16)
+ connect(l15 l14 l15)
+ connect(l16 l14 l16)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BWBTEST
+
+  # Circuit boundary
+  rect((554500 -276000) (403000 162001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FWBTEST
+
+  # Circuit boundary
+  rect((536500 386500) (404000 179001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(FBGATEST
+
+  # Circuit boundary
+  rect((-449500 412500) (390500 198001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Circuit boundary
+  rect((-468000 -313001) (442500 226001))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+
+ )
+ circuit(BDPTEST
+
+  # Circuit boundary
+  rect((71500 -290000) (371500 194000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Circuit boundary
+  rect((64500 86000) (371500 214500))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(FDPTEST
+
+  # Circuit boundary
+  rect((59500 359500) (375500 241000))
+
+  # Outgoing pins and their connections to nets
+  pin(name(B))
+  pin(name(A))
+
+ )
+ circuit(testall
+
+  # Circuit boundary
+  rect((-577500 -1123000) (1868000 1796000))
+
+  # Nets with their geometries
+  net(1
+   rect(l2 (345500 455000) (256500 25000))
+   rect(l2 (-256500 -146000) (25000 146000))
+   rect(l2 (-47000 -183500) (75000 75000))
+   rect(l4 (-50000 -50000) (25000 25000))
+   rect(l5 (-134000 -25000) (134000 25000))
+   rect(l5 (-50000 -50000) (75000 75000))
+   rect(l5 (-184000 -78500) (75000 75000))
+   rect(l6 (-50000 -50000) (25000 25000))
+   rect(l7 (-133500 -21500) (134500 25000))
+   rect(l7 (-51000 -53500) (75000 75000))
+   rect(l7 (-183500 -73000) (75000 75000))
+   rect(l8 (-50000 -50000) (25000 25000))
+   rect(l9 (-25000 -152000) (25000 152000))
+   rect(l9 (-50000 -50000) (75000 75000))
+   rect(l9 (-80500 -217500) (90000 90000))
+   rect(l10 (-57500 -57500) (25000 25000))
+   rect(l11 (-25000 -25000) (25000 25000))
+  )
+  net(2
+   rect(l9 (348500 26500) (25000 179000))
+   rect(l9 (-57500 -58000) (90000 90000))
+   rect(l9 (-86000 -288500) (90000 90000))
+   rect(l10 (-61500 141000) (25000 25000))
+   rect(l10 (-21000 -223500) (25000 25000))
+   rect(l11 (-29000 173500) (25000 25000))
+   rect(l12 (-58500 -261000) (100000 100000))
+   rect(l12 (-100000 -100000) (100000 100000))
+   rect(l13 (-62500 -62500) (25000 25000))
+   rect(l14 (-24000 -225500) (269500 25000))
+   rect(l14 (-457140 -10680) (187640 34680))
+   rect(l14 (-479500 -25000) (292000 25000))
+   rect(l14 (186500 -16500) (25000 193000))
+   rect(l14 (-87500 -87500) (150000 150000))
+  )
+  net(3
+   rect(l2 (-148000 463000) (300000 25000))
+  )
+
+  # Subcircuits and their connections
+  circuit(2 FDPTEST location(0 0)
+   pin(0 1)
+   pin(1 3)
+  )
+  circuit(3 FWBTEST location(0 0) pin(0 1))
+  circuit(7 DPTEST location(0 0)
+   pin(0 2)
+   pin(1 1)
+  )
+  circuit(8 BDPTEST location(0 0)
+   pin(0 2)
+   pin(1 2)
+  )
+  circuit(9 BBGATEST location(0 0) pin(0 2))
+  circuit(10 BWBTEST location(0 0) pin(0 2))
+  circuit(14 FBGATEST location(0 0) pin(0 3))
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(FBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(FDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(DPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BDPTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BWBTEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(BBGATEST
+
+  # Outgoing pins and their connections to nets
+  pin(name(A))
+  pin(name(B))
+
+ )
+ circuit(TESTALL
+
+  # Nets
+  net(1 name(A1))
+  net(2 name(B1))
+  net(3 name(C1))
+  net(4 name(G1))
+  net(5 name(D1))
+  net(6 name(E1))
+  net(7 name(H1))
+  net(8 name(F1))
+
+  # Subcircuits and their connections
+  circuit(1 FBGATEST name(UFBGA)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 FWBTEST name(UFWB)
+   pin(0 3)
+   pin(1 4)
+  )
+  circuit(3 FDPTEST name(UFDP)
+   pin(0 2)
+   pin(1 3)
+  )
+  circuit(4 DPTEST name(UDP)
+   pin(0 3)
+   pin(1 5)
+  )
+  circuit(5 BDPTEST name(UBDP)
+   pin(0 5)
+   pin(1 6)
+  )
+  circuit(6 BWBTEST name(UBWB)
+   pin(0 5)
+   pin(1 7)
+  )
+  circuit(7 BBGATEST name(UBBGA)
+   pin(0 6)
+   pin(1 8)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(BBGATEST BBGATEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(BDPTEST BDPTEST match
+  xref(
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(BWBTEST BWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(DPTEST DPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FBGATEST FBGATEST match
+  xref(
+   pin(() 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FDPTEST FDPTEST match
+  xref(
+   pin(1 0 match)
+   pin(0 1 match)
+  )
+ )
+ circuit(FWBTEST FWBTEST match
+  xref(
+   pin(() 1 match)
+   pin(0 0 match)
+  )
+ )
+ circuit(testall TESTALL nomatch
+  xref(
+   net(() 6 mismatch)
+   net(3 2 match)
+   net(1 3 match)
+   net(2 5 mismatch)
+   circuit(9 7 mismatch)
+   circuit(8 5 mismatch)
+   circuit(10 6 match)
+   circuit(7 4 match)
+   circuit(14 1 match)
+   circuit(2 3 match)
+   circuit(3 2 match)
+  )
+ )
+)
diff --git a/testdata/ruby/dbNetlistCompare.rb b/testdata/ruby/dbNetlistCompare.rb
index 9fe3b704d..9c05c6c8a 100644
--- a/testdata/ruby/dbNetlistCompare.rb
+++ b/testdata/ruby/dbNetlistCompare.rb
@@ -464,8 +464,8 @@ begin_circuit BUF BUF
 match_nets VDD VDD
 match_nets VSS VSS
 match_nets OUT OUT
-match_nets INT $10
 net_mismatch IN IN
+match_nets INT $10
 net_mismatch INT2 $11
 match_pins $0 $1
 match_pins $1 $3
@@ -524,8 +524,8 @@ begin_circuit BUF BUF
 match_nets VDD VDD
 match_nets VSS VSS
 match_nets OUT OUT
-match_nets INT $10
 net_mismatch IN IN
+match_nets INT $10
 net_mismatch INT2 $11
 match_pins $0 $1
 match_pins $1 $3