From c81388d830cf3994196398abeea26c168ba9e128 Mon Sep 17 00:00:00 2001
From: Matthias Koefferlein <matthias@klayout.de>
Date: Sat, 23 Sep 2023 17:33:44 +0200
Subject: [PATCH] Updated tests

---
 src/db/db/dbLayoutToNetlist.cc                |   7 +-
 src/drc/drc/built-in-macros/_drc_netter.rb    |  79 +-
 src/lvs/unit_tests/lvsTests.cc                |   2 +-
 testdata/lvs/bbdevices3b.lvsdb                |   3 +
 testdata/lvs/bbdevices4b.lvsdb                |   3 +
 testdata/lvs/double_height2.lvsdb             |   1 +
 testdata/lvs/double_height2_texts.lvsdb       |   1 +
 testdata/lvs/ringo_simple_dmos.lvsdb.1        |   3 +
 testdata/lvs/ringo_simple_dmos.lvsdb.2        | 886 -----------------
 .../ringo_simple_implicit_connections.lvsdb.1 |  64 +-
 .../ringo_simple_implicit_connections.lvsdb.2 | 927 ------------------
 11 files changed, 93 insertions(+), 1883 deletions(-)
 delete mode 100644 testdata/lvs/ringo_simple_dmos.lvsdb.2
 delete mode 100644 testdata/lvs/ringo_simple_implicit_connections.lvsdb.2

diff --git a/src/db/db/dbLayoutToNetlist.cc b/src/db/db/dbLayoutToNetlist.cc
index 53a88e01f..d9b4aa299 100644
--- a/src/db/db/dbLayoutToNetlist.cc
+++ b/src/db/db/dbLayoutToNetlist.cc
@@ -485,6 +485,7 @@ void LayoutToNetlist::check_must_connect (const db::Circuit &c, const db::Net &a
     return;
   }
 
+  //  @@@ raise a warning for top level cells?
   if (c.begin_refs () != c.end_refs ()) {
     if (a.begin_pins () == a.end_pins ()) {
       error (tl::sprintf (tl::to_string (tr ("Must-connect net %s from circuit %s is not connected to outside")), a.expanded_name (), c.name ()));
@@ -506,7 +507,11 @@ void LayoutToNetlist::check_must_connect (const db::Circuit &c, const db::Net &a
         error (tl::sprintf (tl::to_string (tr ("Must-connect net %s from circuit %s is not connected at all %s")), b.expanded_name (), c.name (), subcircuit_to_string (sc)));
       }
       if (net_a && net_b && net_a != net_b) {
-        error (tl::sprintf (tl::to_string (tr ("Must-connect nets %s and %s from circuit %s are not connected %s")), a.expanded_name (), b.expanded_name (), c.name (), subcircuit_to_string (sc)));
+        if (net_a->expanded_name () == net_b->expanded_name ()) {
+          error (tl::sprintf (tl::to_string (tr ("Must-connect nets %s from circuit %s are not connected %s")), a.expanded_name (), c.name (), subcircuit_to_string (sc)));
+        } else {
+          error (tl::sprintf (tl::to_string (tr ("Must-connect nets %s and %s from circuit %s are not connected %s")), a.expanded_name (), b.expanded_name (), c.name (), subcircuit_to_string (sc)));
+        }
       }
     }
   }
diff --git a/src/drc/drc/built-in-macros/_drc_netter.rb b/src/drc/drc/built-in-macros/_drc_netter.rb
index d56466183..f7ea6f2ec 100644
--- a/src/drc/drc/built-in-macros/_drc_netter.rb
+++ b/src/drc/drc/built-in-macros/_drc_netter.rb
@@ -249,26 +249,31 @@ module DRC
     
     # %DRC%
     # @name connect_implicit
-    # @brief Specifies a search pattern for labels which create implicit net connections
+    # @brief Specifies a search pattern for implicit net connections ("must connect" nets)
     # @synopsis connect_implicit(label_pattern)
     # @synopsis connect_implicit(cell_pattern, label_pattern)
-    # Use this method to supply label strings which create implicit net connections
-    # on the top level circuit in the first version. This feature is useful to connect identically labelled nets
-    # while a component isn't integrated yet. If the component is integrated, nets may be connected
-    # on a higher hierarchy level - e.g. by a power mesh. Inside the component this net consists
-    # of individual islands. To properly perform netlist extraction and comparison, these islands
-    # need to be connected even though there isn't a physical connection. "connect_implicit" can
-    # achive this if these islands are labelled with the same text on the top level of the
-    # component.
+    # This method specifies a net name search pattern, either for all cells or for
+    # certain cells, given by a name search pattern. Search pattern follow the usual glob
+    # form (e.g. "A*" for all cells or nets with names starting with "A").
+    # 
+    # Then, for nets matching the net name pattern and for which there is more than
+    # one subnet, the subnets are connected. "Subnets" are physically disconnected parts
+    # of a net which carry the same name.
     #
-    # In the second version, the pattern can be specified for a cell range (given by a cell name pattern or a 
-    # single cell name). These pattern are applied to non-top cells. The unspecific pattern
-    # has priority over the cell-specific ones. As the cell selector is a pattern itself, a
-    # single cell may fall into more than one category. In this case, the label filters are
-    # combined.
+    # This feature is useful for example for power nets which are complete in a cell,
+    # but are supposed to be connected upwards in the hierarchy ("must connect" nets).
+    # Physically there are multiple nets, logically - and specifically in the schematic for
+    # the purpose of LVS - there is only one net. 
+    # "connect_implicit" now creates a virtual, combined physical net that matches the logical net.
+    # 
+    # This is general bears the risk of missing a physical connection. The "connect_implicit"
+    # feature therefore checks whether the connection is made physically on the next hierarchy
+    # level, except for top-level cells for which it is assumed that this connection is made
+    # later. A warning is raised instead for top level cells.
     #
     # The implicit connections are applied on the next net extraction and cleared
-    # on "clear_connections".
+    # on "clear_connections". Another feature is \connect_explicit which allows connecting
+    # differently named subnets in a similar fashion.
 
     def connect_implicit(arg1, arg2 = nil)
 
@@ -290,27 +295,24 @@ module DRC
 
     # %DRC%
     # @name connect_explicit
-    # @brief Specifies a list of net names for nets to connect explicitly
+    # @brief Specifies a list of net names for nets to connect ("must connect" nets)
     # @synopsis connect_explicit(net_names)
     # @synopsis connect_explicit(cell_pattern, net_names)
     # Use this method to explicitly connect nets even if there is no physical connection.
-    # As this breaks with the concept of physical verification, this feature should be used 
-    # with care. 
+    # The concept is similar to implicit connection (see \connect_implicit). The method gets
+    # a list of nets which are connected virtually, even if there is no physical connection.
+    # The first version applies this scheme to all cells, the second version to cells matching
+    # the cell name pattern. The cell name pattern follows the usual glob style form (e.g. "A*"
+    # applies the connection in all cells whose name starts with "A").
     #
-    # The first version of this function will connect all nets listed in the "net_names" array 
-    # in the top level cell. The second version takes a cell name pattern and connects all nets listed
-    # in "net_names" for cells matching this pattern.
-    #
-    # A use case for this method is the following: consider a set of standard cells. These do not have a bulk
-    # or n-well pin in the schematics. They also do not have build in tie-down diodes for the 
-    # substrate connections. In this case there is a build-in discrepancy between the 
-    # schematics and the layout: bulk and VSS are separate nets within the layout, but the 
-    # schematic does not list them as separate. The solution is to make an explicit connection
-    # between VDD and n-well and VSS and bulk, provided VDD and VSS are properly labelled as "VDD" and "VSS"
-    # and n-well and bulk are accessible as named nets (for bulk you can use "connect_global").
-    #
-    # The following code will establish an explicit connection for all cells called "INV.." between 
-    # BULK and VSS nets:
+    # This method is useful to establish a logical connection which is made later up on the 
+    # next level of hierarchy. For example, a standard cell my not contain substrate or well
+    # taps as these may be made by tap or spare cells. Logically however, the cell only has
+    # one power or ground pin for the devices and substrate or well. In order to match both
+    # representations - for example for the purpose of LVS - the dual power or ground pins have
+    # to be connected. Assuming that there is a global net "BULK" for the substrate and a
+    # net "VSS" for the sources of the NMOS devices, the following statement will create this
+    # connection for all cell names beginning with "INV":
     #
     # @code
     # connect_global(bulk, "BULK")
@@ -318,14 +320,19 @@ module DRC
     # connect_explicit("INV*", [ "BULK", "VSS" ])
     # @/code
     #
+    # The resulting net and pin will carry a name made from the combination of the connected
+    # nets. In this case it will be "BULK,VSS".
+    #
+    # The virtual connection in general bears the risk of missing a physical connection. 
+    # The "connect_explicit" feature therefore checks whether the connection is made physically 
+    # on the next hierarchy level ("must connect" nets), except for top-level cells for which 
+    # it is assumed that this connection is made later. 
+    # A warning is raised instead for top level cells.
+    # 
     # Explicit connections also imply implicit connections between different parts of 
     # one of the nets. In the example before, "VSS" pieces without a physical connection
     # will also be connected.
     #
-    # When you use explicit connections you should make sure by other ways that the connection
-    # is made physically. For example, for the bulk/n-well pin example above, by enforcing at least one
-    # tie-down diode per n-well island and in the substrate by means of a DRC rule.
-    #
     # The explicit connections are applied on the next net extraction and cleared
     # on "clear_connections".
 
diff --git a/src/lvs/unit_tests/lvsTests.cc b/src/lvs/unit_tests/lvsTests.cc
index 18c0810bf..53584222b 100644
--- a/src/lvs/unit_tests/lvsTests.cc
+++ b/src/lvs/unit_tests/lvsTests.cc
@@ -165,7 +165,7 @@ TEST(20_private)
 
 TEST(21_private)
 {
-  run_test (_this, "test_21.lylvs", "test_21.cir.gz", "test_21.gds.gz", true, "test_21_2.lvsdb");
+  run_test (_this, "test_21.lylvs", "test_21.cir.gz", "test_21.gds.gz", true, "test_21_3.lvsdb");
 }
 
 //  issue #1021
diff --git a/testdata/lvs/bbdevices3b.lvsdb b/testdata/lvs/bbdevices3b.lvsdb
index 95ff6ee8b..d4573f7a4 100644
--- a/testdata/lvs/bbdevices3b.lvsdb
+++ b/testdata/lvs/bbdevices3b.lvsdb
@@ -280,6 +280,9 @@ reference(
 
 # Cross reference
 xref(
+ log(
+  entry(error description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n  B: BWBTEST'))
+ )
  circuit(BBGATEST BBGATEST match
   xref(
    pin(() 1 match)
diff --git a/testdata/lvs/bbdevices4b.lvsdb b/testdata/lvs/bbdevices4b.lvsdb
index b91a05e0c..90993b7b2 100644
--- a/testdata/lvs/bbdevices4b.lvsdb
+++ b/testdata/lvs/bbdevices4b.lvsdb
@@ -275,6 +275,9 @@ reference(
 
 # Cross reference
 xref(
+ log(
+  entry(error description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n  B: BWBTEST'))
+ )
  circuit(BBGATEST BBGATEST match
   xref(
    pin(() 1 match)
diff --git a/testdata/lvs/double_height2.lvsdb b/testdata/lvs/double_height2.lvsdb
index e794e299c..8bad8efaa 100644
--- a/testdata/lvs/double_height2.lvsdb
+++ b/testdata/lvs/double_height2.lvsdb
@@ -27,6 +27,7 @@ J(
  C(l2 l6 l2)
  C(l5 l6 l5)
  G(l14 SUBSTRATE)
+ H(E B('Must-connect nets R from circuit INV2 are not connected in INVCHAIN'))
  K(PMOS MOS3)
  K(NMOS MOS3)
  D(D$PMOS PMOS
diff --git a/testdata/lvs/double_height2_texts.lvsdb b/testdata/lvs/double_height2_texts.lvsdb
index 2c986d071..ec8dc1494 100644
--- a/testdata/lvs/double_height2_texts.lvsdb
+++ b/testdata/lvs/double_height2_texts.lvsdb
@@ -27,6 +27,7 @@ J(
  C(l2 l6 l2)
  C(l5 l6 l5)
  G(l14 SUBSTRATE)
+ H(E B('Must-connect nets R from circuit INV2 are not connected in INVCHAIN'))
  K(PMOS MOS3)
  K(NMOS MOS3)
  D(D$PMOS PMOS
diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.1 b/testdata/lvs/ringo_simple_dmos.lvsdb.1
index 59c0c5194..155a4128c 100644
--- a/testdata/lvs/ringo_simple_dmos.lvsdb.1
+++ b/testdata/lvs/ringo_simple_dmos.lvsdb.1
@@ -832,6 +832,9 @@ reference(
 
 # Cross reference
 xref(
+ log(
+  entry(error description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n  A: ND2X1\n  B: ND2X1'))
+ )
  circuit(INVX1 INVX1 match
   xref(
    net(4 4 match)
diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.2 b/testdata/lvs/ringo_simple_dmos.lvsdb.2
deleted file mode 100644
index 94072e582..000000000
--- a/testdata/lvs/ringo_simple_dmos.lvsdb.2
+++ /dev/null
@@ -1,886 +0,0 @@
-#%lvsdb-klayout
-
-# Layout
-layout(
- top(RINGO)
- unit(0.001)
-
- # Layer section
- # This section lists the mask layers (drawing or derived) and their connections.
-
- # Mask layers
- layer(l4 '1/0')
- layer(l5 '5/0')
- layer(l10 '8/0')
- layer(l13 '9/0')
- layer(l14 '10/0')
- layer(l15 '11/0')
- layer(l9)
- layer(l3)
- layer(l1)
- layer(l11)
- layer(l8)
- layer(l6)
- layer(l12)
-
- # Mask layer connectivity
- connect(l4 l4 l11)
- connect(l5 l5 l10)
- connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
- connect(l13 l10 l13 l14)
- connect(l14 l13 l14 l15)
- connect(l15 l14 l15)
- connect(l9 l9)
- connect(l3 l10 l3)
- connect(l1 l10 l1)
- connect(l11 l4 l10 l11)
- connect(l8 l10 l8)
- connect(l6 l10 l6)
- connect(l12 l10 l12)
-
- # Global nets and connectivity
- global(l9 SUBSTRATE)
- global(l12 SUBSTRATE)
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Device abstracts section
- # Device abstracts list the pin shapes of the devices.
- device(D$PMOS PMOS
-  terminal(S
-   rect(l3 (125 -750) (450 1500))
-  )
-  terminal(G
-   rect(l5 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l1 (-550 -750) (425 1500))
-  )
-  terminal(B
-   rect(l4 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$1 PMOS
-  terminal(S
-   rect(l3 (-575 -750) (450 1500))
-  )
-  terminal(G
-   rect(l5 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l1 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l4 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$2 PMOS
-  terminal(S
-   rect(l3 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l5 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l1 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l4 (-125 -750) (250 1500))
-  )
- )
- device(D$NMOS NMOS
-  terminal(S
-   rect(l8 (125 -475) (450 950))
-  )
-  terminal(G
-   rect(l5 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (-550 -475) (425 950))
-  )
-  terminal(B
-   rect(l9 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$1 NMOS
-  terminal(S
-   rect(l8 (-575 -475) (450 950))
-  )
-  terminal(G
-   rect(l5 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l9 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$2 NMOS
-  terminal(S
-   rect(l8 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l5 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l9 (-125 -475) (250 950))
-  )
- )
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Circuit boundary
-  rect((-100 400) (2600 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l10 (1110 5160) (180 180))
-   rect(l10 (-180 920) (180 180))
-   rect(l10 (-180 -730) (180 180))
-   rect(l13 (-240 -790) (300 1700))
-   rect(l13 (-1350 0) (2400 800))
-   rect(l13 (-1150 -400) (0 0))
-   rect(l3 (-250 -2150) (425 1500))
-   rect(l3 (-450 -1500) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l10 (1810 1770) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l10 (-1580 3760) (180 180))
-   rect(l10 (-180 -730) (180 180))
-   rect(l10 (-180 -730) (180 180))
-   rect(l10 (1220 920) (180 180))
-   rect(l10 (-180 -1280) (180 180))
-   rect(l10 (-180 370) (180 180))
-   polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
-   rect(l13 (-110 1390) (300 1400))
-   polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
-   rect(l13 (-140 -500) (0 0))
-   rect(l13 (-1750 1100) (300 1400))
-   rect(l13 (1100 -1700) (300 300))
-   rect(l13 (-300 0) (300 1400))
-   rect(l1 (-1750 -1450) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-   rect(l6 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l10 (410 1770) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l13 (-240 -1300) (300 1360))
-   rect(l13 (-650 -2160) (2400 800))
-   rect(l13 (-1150 -400) (0 0))
-   rect(l6 (-950 860) (425 950))
-  )
-  net(4
-   rect(l8 (1000 1660) (425 950))
-   rect(l8 (-450 -950) (425 950))
-  )
-  net(5
-   rect(l4 (-100 4500) (2600 3500))
-  )
-  net(6 name(B)
-   rect(l5 (1425 2860) (250 1940))
-   rect(l5 (-345 -950) (300 300))
-   rect(l5 (-205 650) (250 2000))
-   rect(l5 (-250 -2000) (250 2000))
-   rect(l5 (-250 -5390) (250 1450))
-   rect(l10 (-285 1050) (180 180))
-   rect(l13 (-70 -90) (0 0))
-   rect(l13 (-170 -150) (300 300))
-  )
-  net(7 name(A)
-   rect(l5 (725 2860) (250 1940))
-   rect(l5 (-325 -1850) (300 300))
-   rect(l5 (-225 1550) (250 2000))
-   rect(l5 (-250 -2000) (250 2000))
-   rect(l5 (-250 -5390) (250 1450))
-   rect(l10 (-265 150) (180 180))
-   rect(l13 (-90 -90) (0 0))
-   rect(l13 (-150 -150) (300 300))
-  )
-  net(8 name(SUBSTRATE))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(5)
-  pin(6 name(B))
-  pin(7 name(A))
-  pin(8 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.3375)
-   param(AD 0.6375)
-   param(PS 1.95)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 7)
-   terminal(D 2)
-   terminal(B 5)
-  )
-  device(2 D$PMOS$1
-   location(1550 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.3375)
-   param(AD 0.6375)
-   param(PS 1.95)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 6)
-   terminal(D 2)
-   terminal(B 5)
-  )
-  device(3 D$NMOS
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.21375)
-   param(AD 0.40375)
-   param(PS 1.4)
-   param(PD 2.75)
-   terminal(S 4)
-   terminal(G 7)
-   terminal(D 3)
-   terminal(B 8)
-  )
-  device(4 D$NMOS$1
-   location(1550 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.21375)
-   param(AD 0.40375)
-   param(PS 1.4)
-   param(PD 2.75)
-   terminal(S 4)
-   terminal(G 6)
-   terminal(D 2)
-   terminal(B 8)
-  )
-
- )
- circuit(INVX1
-
-  # Circuit boundary
-  rect((-100 400) (2000 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l10 (410 6260) (180 180))
-   rect(l10 (-180 -730) (180 180))
-   rect(l10 (-180 -730) (180 180))
-   rect(l13 (-240 -240) (300 1400))
-   rect(l13 (-650 300) (1800 800))
-   rect(l13 (-1450 -1100) (300 300))
-   rect(l13 (300 400) (0 0))
-   rect(l3 (-650 -2150) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l10 (1110 5160) (180 180))
-   rect(l10 (-180 920) (180 180))
-   rect(l10 (-180 -730) (180 180))
-   rect(l10 (-180 -4120) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l13 (-240 -790) (300 4790))
-   rect(l13 (-150 -2500) (0 0))
-   rect(l1 (-225 1050) (425 1500))
-   rect(l6 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l10 (410 1770) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l13 (-240 -1300) (300 1360))
-   rect(l13 (-650 -2160) (1800 800))
-   rect(l13 (-850 -400) (0 0))
-   rect(l8 (-650 860) (425 950))
-  )
-  net(4
-   rect(l4 (-100 4500) (2000 3500))
-  )
-  net(5 name(IN)
-   rect(l5 (725 2860) (250 1940))
-   rect(l5 (-525 -1850) (300 300))
-   rect(l5 (-25 1550) (250 2000))
-   rect(l5 (-250 -2000) (250 2000))
-   rect(l5 (-250 -5390) (250 1450))
-   rect(l10 (-465 150) (180 180))
-   rect(l13 (-90 -90) (0 0))
-   rect(l13 (-150 -150) (300 300))
-  )
-  net(6 name(SUBSTRATE))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(IN))
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS$2
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 D$NMOS$2
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.40375)
-   param(PS 2.75)
-   param(PD 2.75)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Circuit boundary
-  rect((0 350) (25800 7650))
-
-  # Nets with their geometries
-  net(1
-   rect(l13 (4040 2950) (610 300))
-  )
-  net(2
-   rect(l13 (5550 2950) (900 300))
-  )
-  net(3
-   rect(l13 (7350 2950) (900 300))
-  )
-  net(4
-   rect(l13 (9150 2950) (900 300))
-  )
-  net(5
-   rect(l13 (10950 2950) (900 300))
-  )
-  net(6
-   rect(l13 (12750 2950) (900 300))
-  )
-  net(7
-   rect(l13 (14550 2950) (900 300))
-  )
-  net(8
-   rect(l13 (16350 2950) (900 300))
-  )
-  net(9
-   rect(l13 (18150 2950) (900 300))
-  )
-  net(10
-   rect(l13 (19950 2950) (900 300))
-  )
-  net(11 name(FB)
-   rect(l13 (21750 2950) (900 300))
-   rect(l13 (-19530 590) (320 320))
-   rect(l13 (17820 -320) (320 320))
-   rect(l14 (-18400 -260) (200 200))
-   rect(l14 (17940 -200) (200 200))
-   rect(l15 (-18040 -300) (17740 400))
-   rect(l15 (-17920 -200) (0 0))
-   rect(l15 (-220 -200) (400 400))
-   rect(l15 (17740 -400) (400 400))
-  )
-  net(12 name(VDD)
-   rect(l4 (500 4500) (1400 3500))
-   rect(l4 (-1900 -3500) (600 3500))
-   rect(l4 (23300 -3500) (1400 3500))
-   rect(l4 (-100 -3500) (600 3500))
-   rect(l10 (-24690 -1240) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l10 (-180 -1280) (180 180))
-   rect(l10 (23220 370) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l10 (-180 -1280) (180 180))
-   rect(l13 (-21740 860) (0 0))
-   rect(l13 (-2350 -450) (1200 800))
-   rect(l13 (-750 -1450) (300 1400))
-   rect(l13 (-100 -350) (0 0))
-   rect(l13 (-1250 -400) (600 800))
-   rect(l13 (23400 -800) (1200 800))
-   rect(l13 (-750 -1450) (300 1400))
-   rect(l13 (-100 -350) (0 0))
-   rect(l13 (550 -400) (600 800))
-   rect(l11 (-24850 -1500) (500 1500))
-   rect(l11 (22900 -1500) (500 1500))
-  )
-  net(13 name(OUT)
-   rect(l13 (23440 3840) (320 320))
-   rect(l14 (-260 -260) (200 200))
-   rect(l15 (-100 -100) (0 0))
-   rect(l15 (-200 -200) (400 400))
-  )
-  net(14 name(ENABLE)
-   rect(l13 (2440 2940) (320 320))
-   rect(l14 (-260 -260) (200 200))
-   rect(l15 (-100 -100) (0 0))
-   rect(l15 (-200 -200) (400 400))
-  )
-  net(15 name(VSS)
-   rect(l10 (1110 1610) (180 180))
-   rect(l10 (-180 -1280) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l10 (23220 370) (180 180))
-   rect(l10 (-180 -1280) (180 180))
-   rect(l10 (-180 370) (180 180))
-   rect(l13 (-21740 -390) (0 0))
-   rect(l13 (-1900 -400) (300 1400))
-   rect(l13 (-750 -1450) (1200 800))
-   rect(l13 (-550 -400) (0 0))
-   rect(l13 (-1250 -400) (600 800))
-   rect(l13 (23850 -750) (300 1400))
-   rect(l13 (-750 -1450) (1200 800))
-   rect(l13 (-550 -400) (0 0))
-   rect(l13 (550 -400) (600 800))
-   rect(l12 (-24850 -800) (500 1500))
-   rect(l12 (22900 -1500) (500 1500))
-  )
-
-  # Outgoing pins and their connections to nets
-  pin(11 name(FB))
-  pin(12 name(VDD))
-  pin(13 name(OUT))
-  pin(14 name(ENABLE))
-  pin(15 name(VSS))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 location(1800 0)
-   pin(0 12)
-   pin(1 1)
-   pin(2 15)
-   pin(3 12)
-   pin(4 11)
-   pin(5 14)
-   pin(6 15)
-  )
-  circuit(2 INVX1 location(4200 0)
-   pin(0 12)
-   pin(1 2)
-   pin(2 15)
-   pin(3 12)
-   pin(4 1)
-   pin(5 15)
-  )
-  circuit(3 INVX1 location(6000 0)
-   pin(0 12)
-   pin(1 3)
-   pin(2 15)
-   pin(3 12)
-   pin(4 2)
-   pin(5 15)
-  )
-  circuit(4 INVX1 location(7800 0)
-   pin(0 12)
-   pin(1 4)
-   pin(2 15)
-   pin(3 12)
-   pin(4 3)
-   pin(5 15)
-  )
-  circuit(5 INVX1 location(9600 0)
-   pin(0 12)
-   pin(1 5)
-   pin(2 15)
-   pin(3 12)
-   pin(4 4)
-   pin(5 15)
-  )
-  circuit(6 INVX1 location(11400 0)
-   pin(0 12)
-   pin(1 6)
-   pin(2 15)
-   pin(3 12)
-   pin(4 5)
-   pin(5 15)
-  )
-  circuit(7 INVX1 location(13200 0)
-   pin(0 12)
-   pin(1 7)
-   pin(2 15)
-   pin(3 12)
-   pin(4 6)
-   pin(5 15)
-  )
-  circuit(8 INVX1 location(15000 0)
-   pin(0 12)
-   pin(1 8)
-   pin(2 15)
-   pin(3 12)
-   pin(4 7)
-   pin(5 15)
-  )
-  circuit(9 INVX1 location(16800 0)
-   pin(0 12)
-   pin(1 9)
-   pin(2 15)
-   pin(3 12)
-   pin(4 8)
-   pin(5 15)
-  )
-  circuit(10 INVX1 location(18600 0)
-   pin(0 12)
-   pin(1 10)
-   pin(2 15)
-   pin(3 12)
-   pin(4 9)
-   pin(5 15)
-  )
-  circuit(11 INVX1 location(20400 0)
-   pin(0 12)
-   pin(1 11)
-   pin(2 15)
-   pin(3 12)
-   pin(4 10)
-   pin(5 15)
-  )
-  circuit(12 INVX1 location(22200 0)
-   pin(0 12)
-   pin(1 13)
-   pin(2 15)
-   pin(3 12)
-   pin(4 11)
-   pin(5 15)
-  )
-
- )
-)
-
-# Reference netlist
-reference(
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(B))
-  net(6 name(A))
-  net(7 name(BULK))
-  net(8 name('1'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 6)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 PMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 NMOS
-   name($3)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 NMOS
-   name($4)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(IN))
-  pin(6 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Nets
-  net(1 name(VSS))
-  net(2 name(VDD))
-  net(3 name(FB))
-  net(4 name(ENABLE))
-  net(5 name(OUT))
-  net(6 name('1'))
-  net(7 name('2'))
-  net(8 name('3'))
-  net(9 name('4'))
-  net(10 name('5'))
-  net(11 name('6'))
-  net(12 name('7'))
-  net(13 name('8'))
-  net(14 name('9'))
-  net(15 name('10'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VSS))
-  pin(2 name(VDD))
-  pin(3 name(FB))
-  pin(4 name(ENABLE))
-  pin(5 name(OUT))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 name($1)
-   pin(0 2)
-   pin(1 6)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 4)
-   pin(6 1)
-  )
-  circuit(2 INVX1 name($2)
-   pin(0 2)
-   pin(1 7)
-   pin(2 1)
-   pin(3 2)
-   pin(4 6)
-   pin(5 1)
-  )
-  circuit(3 INVX1 name($3)
-   pin(0 2)
-   pin(1 8)
-   pin(2 1)
-   pin(3 2)
-   pin(4 7)
-   pin(5 1)
-  )
-  circuit(4 INVX1 name($4)
-   pin(0 2)
-   pin(1 9)
-   pin(2 1)
-   pin(3 2)
-   pin(4 8)
-   pin(5 1)
-  )
-  circuit(5 INVX1 name($5)
-   pin(0 2)
-   pin(1 10)
-   pin(2 1)
-   pin(3 2)
-   pin(4 9)
-   pin(5 1)
-  )
-  circuit(6 INVX1 name($6)
-   pin(0 2)
-   pin(1 11)
-   pin(2 1)
-   pin(3 2)
-   pin(4 10)
-   pin(5 1)
-  )
-  circuit(7 INVX1 name($7)
-   pin(0 2)
-   pin(1 12)
-   pin(2 1)
-   pin(3 2)
-   pin(4 11)
-   pin(5 1)
-  )
-  circuit(8 INVX1 name($8)
-   pin(0 2)
-   pin(1 13)
-   pin(2 1)
-   pin(3 2)
-   pin(4 12)
-   pin(5 1)
-  )
-  circuit(9 INVX1 name($9)
-   pin(0 2)
-   pin(1 14)
-   pin(2 1)
-   pin(3 2)
-   pin(4 13)
-   pin(5 1)
-  )
-  circuit(10 INVX1 name($10)
-   pin(0 2)
-   pin(1 15)
-   pin(2 1)
-   pin(3 2)
-   pin(4 14)
-   pin(5 1)
-  )
-  circuit(11 INVX1 name($11)
-   pin(0 2)
-   pin(1 3)
-   pin(2 1)
-   pin(3 2)
-   pin(4 15)
-   pin(5 1)
-  )
-  circuit(12 INVX1 name($12)
-   pin(0 2)
-   pin(1 5)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 1)
-  )
-
- )
-)
-
-# Cross reference
-xref(
- circuit(INVX1 INVX1 match
-  xref(
-   net(4 4 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(6 6 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(5 5 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(2 2 match)
-   device(1 1 match)
-  )
- )
- circuit(ND2X1 ND2X1 nomatch
-  log(
-   entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
-   entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
-   entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
-  )
-  xref(
-   net(5 4 match)
-   net(4 3 mismatch)
-   net(7 6 match)
-   net(6 5 match)
-   net(2 2 match)
-   net(8 7 mismatch)
-   net(1 1 match)
-   net(3 8 mismatch)
-   pin(() 2 mismatch)
-   pin(3 3 match)
-   pin(5 5 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(6 6 match)
-   pin(0 0 match)
-   pin(2 () mismatch)
-   device(3 3 match)
-   device(4 4 mismatch)
-   device(1 1 match)
-   device(2 2 match)
-  )
- )
- circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n  A: ND2X1\n  B: ND2X1')
-  xref(
-  )
- )
-)
diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1
index 179fe4455..24fa78ec9 100644
--- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1
+++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1
@@ -404,36 +404,36 @@ layout(
   )
   net(12 name(VDD)
    rect(l3 (22600 4500) (1400 3500))
-   rect(l3 (-23500 -3500) (1400 3500))
-   rect(l3 (-1900 -3500) (600 3500))
-   rect(l3 (25800 -3500) (1400 3500))
+   rect(l3 (2400 -3500) (1400 3500))
    rect(l3 (-100 -3500) (600 3500))
-   rect(l8 (-5090 -1240) (180 180))
+   rect(l3 (-27800 -3500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l8 (22610 -1240) (180 180))
    rect(l8 (-180 370) (180 180))
    rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-22280 370) (180 180))
+   rect(l8 (3620 370) (180 180))
    rect(l8 (-180 370) (180 180))
    rect(l8 (-180 -1280) (180 180))
-   rect(l8 (25720 370) (180 180))
+   rect(l8 (-26080 370) (180 180))
    rect(l8 (-180 370) (180 180))
    rect(l8 (-180 -1280) (180 180))
-   rect(l11 (-4890 1010) (0 0))
+   rect(l11 (21010 1010) (0 0))
    rect(l11 (2800 -50) (0 0))
    rect(l11 (-22150 -100) (0 0))
    rect(l11 (19750 -450) (1200 800))
    rect(l11 (-750 -1450) (300 1400))
    rect(l11 (-100 -350) (0 0))
-   rect(l11 (-22750 -400) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-100 -350) (0 0))
-   rect(l11 (-1250 -400) (600 800))
-   rect(l11 (25900 -800) (1200 800))
+   rect(l11 (3150 -400) (1200 800))
    rect(l11 (-750 -1450) (300 1400))
    rect(l11 (-100 -350) (0 0))
    rect(l11 (550 -400) (600 800))
-   rect(l9 (-5250 -1500) (500 1500))
-   rect(l9 (-22600 -1500) (500 1500))
-   rect(l9 (25400 -1500) (500 1500))
+   rect(l11 (-27700 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l9 (22450 -1500) (500 1500))
+   rect(l9 (3300 -1500) (500 1500))
+   rect(l9 (-26400 -1500) (500 1500))
   )
   net(13 name(OUT)
    rect(l11 (25990 3840) (320 320))
@@ -448,32 +448,32 @@ layout(
    rect(l13 (-150 -200) (400 400))
   )
   net(15 name(VSS)
-   rect(l8 (27010 1610) (180 180))
+   rect(l8 (1110 1610) (180 180))
    rect(l8 (-180 -1280) (180 180))
    rect(l8 (-180 370) (180 180))
-   rect(l8 (-3980 370) (180 180))
+   rect(l8 (21920 370) (180 180))
    rect(l8 (-180 -1280) (180 180))
    rect(l8 (-180 370) (180 180))
-   rect(l8 (-22280 370) (180 180))
+   rect(l8 (3620 370) (180 180))
    rect(l8 (-180 -1280) (180 180))
    rect(l8 (-180 370) (180 180))
-   rect(l11 (24710 -290) (0 0))
-   rect(l11 (-3850 0) (0 0))
-   rect(l11 (-19200 -100) (0 0))
-   rect(l11 (24000 -400) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (550 -400) (600 800))
-   rect(l11 (-5150 -750) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (-22300 -350) (300 1400))
+   rect(l11 (-24240 -390) (0 0))
+   rect(l11 (19200 100) (0 0))
+   rect(l11 (3850 0) (0 0))
+   rect(l11 (-24950 -500) (300 1400))
    rect(l11 (-750 -1450) (1200 800))
    rect(l11 (-550 -400) (0 0))
    rect(l11 (-1250 -400) (600 800))
-   rect(l10 (26250 -800) (500 1500))
-   rect(l10 (-4300 -1500) (500 1500))
-   rect(l10 (-22600 -1500) (500 1500))
+   rect(l11 (22550 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (3600 -350) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-27350 -800) (500 1500))
+   rect(l10 (21600 -1500) (500 1500))
+   rect(l10 (3300 -1500) (500 1500))
   )
 
   # Outgoing pins and their connections to nets
diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2
deleted file mode 100644
index 6ae8d34f4..000000000
--- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2
+++ /dev/null
@@ -1,927 +0,0 @@
-#%lvsdb-klayout
-
-# Layout
-layout(
- top(RINGO)
- unit(0.001)
-
- # Layer section
- # This section lists the mask layers (drawing or derived) and their connections.
-
- # Mask layers
- layer(l3 '1/0')
- layer(l4 '5/0')
- layer(l8 '8/0')
- layer(l11 '9/0')
- layer(l12 '10/0')
- layer(l13 '11/0')
- layer(l7)
- layer(l2)
- layer(l9)
- layer(l6)
- layer(l10)
-
- # Mask layer connectivity
- connect(l3 l3 l9)
- connect(l4 l4 l8)
- connect(l8 l4 l8 l11 l2 l9 l6 l10)
- connect(l11 l8 l11 l12)
- connect(l12 l11 l12 l13)
- connect(l13 l12 l13)
- connect(l7 l7)
- connect(l2 l8 l2)
- connect(l9 l3 l8 l9)
- connect(l6 l8 l6)
- connect(l10 l8 l10)
-
- # Global nets and connectivity
- global(l7 SUBSTRATE)
- global(l10 SUBSTRATE)
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Device abstracts section
- # Device abstracts list the pin shapes of the devices.
- device(D$PMOS PMOS
-  terminal(S
-   rect(l2 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l2 (125 -750) (450 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$1 PMOS
-  terminal(S
-   rect(l2 (-575 -750) (450 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l2 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$PMOS$2 PMOS
-  terminal(S
-   rect(l2 (-550 -750) (425 1500))
-  )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
-  )
-  terminal(D
-   rect(l2 (125 -750) (425 1500))
-  )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
-  )
- )
- device(D$NMOS NMOS
-  terminal(S
-   rect(l6 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (450 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$1 NMOS
-  terminal(S
-   rect(l6 (-575 -475) (450 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
- device(D$NMOS$2 NMOS
-  terminal(S
-   rect(l6 (-550 -475) (425 950))
-  )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
-  )
-  terminal(D
-   rect(l6 (125 -475) (425 950))
-  )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
-  )
- )
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Circuit boundary
-  rect((-100 400) (2600 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -790) (300 1700))
-   rect(l11 (-1350 0) (2400 800))
-   rect(l11 (-1150 -400) (0 0))
-   rect(l2 (-275 -2150) (425 1500))
-   rect(l2 (-400 -1500) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1810 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-1580 3760) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (1220 920) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
-   rect(l11 (-110 1390) (300 1400))
-   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
-   rect(l11 (-140 -500) (0 0))
-   rect(l11 (-1750 1100) (300 1400))
-   rect(l11 (1100 -1700) (300 300))
-   rect(l11 (-300 0) (300 1400))
-   rect(l2 (-375 -1450) (425 1500))
-   rect(l2 (-1800 -1500) (425 1500))
-   rect(l6 (950 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (2400 800))
-   rect(l11 (-1150 -400) (0 0))
-   rect(l6 (-950 860) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2600 3500))
-  )
-  net(5 name(B)
-   rect(l4 (1425 2860) (250 1940))
-   rect(l4 (-345 -950) (300 300))
-   rect(l4 (-205 650) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-285 1050) (180 180))
-   rect(l11 (-70 -90) (0 0))
-   rect(l11 (-170 -150) (300 300))
-  )
-  net(6 name(A)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-325 -1850) (300 300))
-   rect(l4 (-225 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-265 150) (180 180))
-   rect(l11 (-90 -90) (0 0))
-   rect(l11 (-150 -150) (300 300))
-  )
-  net(7 name(SUBSTRATE))
-  net(8
-   rect(l6 (975 1660) (425 950))
-   rect(l6 (-400 -950) (425 950))
-  )
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.3375)
-   param(PS 3.85)
-   param(PD 1.95)
-   terminal(S 2)
-   terminal(G 6)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 D$PMOS$1
-   location(1550 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.3375)
-   param(AD 0.6375)
-   param(PS 1.95)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 D$NMOS
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.21375)
-   param(PS 2.75)
-   param(PD 1.4)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 D$NMOS$1
-   location(1550 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.21375)
-   param(AD 0.40375)
-   param(PS 1.4)
-   param(PD 2.75)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Circuit boundary
-  rect((-100 400) (2000 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (410 6260) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -240) (300 1400))
-   rect(l11 (-650 300) (1800 800))
-   rect(l11 (-1450 -1100) (300 300))
-   rect(l11 (300 400) (0 0))
-   rect(l2 (-650 -2150) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -4120) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -790) (300 4790))
-   rect(l11 (-150 -2500) (0 0))
-   rect(l2 (-225 1050) (425 1500))
-   rect(l6 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (1800 800))
-   rect(l11 (-850 -400) (0 0))
-   rect(l6 (-650 860) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2000 3500))
-  )
-  net(5 name(IN)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-525 -1850) (300 300))
-   rect(l4 (-25 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-465 150) (180 180))
-   rect(l11 (-90 -90) (0 0))
-   rect(l11 (-150 -150) (300 300))
-  )
-  net(6 name(SUBSTRATE))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(IN))
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS$2
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 D$NMOS$2
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.40375)
-   param(PS 2.75)
-   param(PD 2.75)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Circuit boundary
-  rect((0 350) (28300 7650))
-
-  # Nets with their geometries
-  net(1
-   rect(l11 (4040 2950) (1160 300))
-  )
-  net(2
-   rect(l11 (6050 2950) (900 300))
-  )
-  net(3
-   rect(l11 (7850 2950) (900 300))
-  )
-  net(4
-   rect(l11 (9650 2950) (900 300))
-  )
-  net(5
-   rect(l11 (11450 2950) (900 300))
-  )
-  net(6
-   rect(l11 (13250 2950) (900 300))
-  )
-  net(7
-   rect(l11 (15050 2950) (900 300))
-  )
-  net(8
-   rect(l11 (16850 2950) (900 300))
-  )
-  net(9
-   rect(l11 (18650 2950) (900 300))
-  )
-  net(10
-   rect(l11 (20450 2950) (900 300))
-  )
-  net(11 name(FB)
-   rect(l11 (22250 2950) (2900 300))
-   rect(l11 (-21980 590) (320 320))
-   rect(l11 (18570 -320) (320 320))
-   rect(l12 (-19150 -260) (200 200))
-   rect(l12 (18690 -200) (200 200))
-   rect(l13 (-18840 -300) (18890 400))
-   rect(l13 (-19070 -200) (0 0))
-   rect(l13 (-170 -200) (400 400))
-   rect(l13 (18490 -400) (400 400))
-  )
-  net(12 name(VDD)
-   rect(l3 (22600 4500) (1400 3500))
-   rect(l3 (-23500 -3500) (1400 3500))
-   rect(l3 (-1900 -3500) (600 3500))
-   rect(l3 (25800 -3500) (1400 3500))
-   rect(l3 (-100 -3500) (600 3500))
-   rect(l8 (-5090 -1240) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-22280 370) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (25720 370) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l11 (-4890 1010) (0 0))
-   rect(l11 (2800 -50) (0 0))
-   rect(l11 (-22150 -100) (0 0))
-   rect(l11 (19750 -450) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-100 -350) (0 0))
-   rect(l11 (-22750 -400) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-100 -350) (0 0))
-   rect(l11 (-1250 -400) (600 800))
-   rect(l11 (25900 -800) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-100 -350) (0 0))
-   rect(l11 (550 -400) (600 800))
-   rect(l9 (-5250 -1500) (500 1500))
-   rect(l9 (-22600 -1500) (500 1500))
-   rect(l9 (25400 -1500) (500 1500))
-  )
-  net(13 name(OUT)
-   rect(l11 (25990 3840) (320 320))
-   rect(l12 (-260 -260) (200 200))
-   rect(l13 (-150 -100) (0 0))
-   rect(l13 (-150 -200) (400 400))
-  )
-  net(14 name(ENABLE)
-   rect(l11 (2490 2940) (320 320))
-   rect(l12 (-260 -260) (200 200))
-   rect(l13 (-150 -100) (0 0))
-   rect(l13 (-150 -200) (400 400))
-  )
-  net(15 name(VSS)
-   rect(l8 (27010 1610) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-3980 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-22280 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (24710 -290) (0 0))
-   rect(l11 (-3850 0) (0 0))
-   rect(l11 (-19200 -100) (0 0))
-   rect(l11 (24000 -400) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (550 -400) (600 800))
-   rect(l11 (-5150 -750) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (-22300 -350) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-550 -400) (0 0))
-   rect(l11 (-1250 -400) (600 800))
-   rect(l10 (26250 -800) (500 1500))
-   rect(l10 (-4300 -1500) (500 1500))
-   rect(l10 (-22600 -1500) (500 1500))
-  )
-
-  # Outgoing pins and their connections to nets
-  pin(11 name(FB))
-  pin(12 name(VDD))
-  pin(13 name(OUT))
-  pin(14 name(ENABLE))
-  pin(15 name(VSS))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 location(1800 0)
-   pin(0 12)
-   pin(1 1)
-   pin(2 15)
-   pin(3 12)
-   pin(4 11)
-   pin(5 14)
-   pin(6 15)
-  )
-  circuit(2 INVX1 location(4700 0)
-   pin(0 12)
-   pin(1 2)
-   pin(2 15)
-   pin(3 12)
-   pin(4 1)
-   pin(5 15)
-  )
-  circuit(3 INVX1 location(6500 0)
-   pin(0 12)
-   pin(1 3)
-   pin(2 15)
-   pin(3 12)
-   pin(4 2)
-   pin(5 15)
-  )
-  circuit(4 INVX1 location(8300 0)
-   pin(0 12)
-   pin(1 4)
-   pin(2 15)
-   pin(3 12)
-   pin(4 3)
-   pin(5 15)
-  )
-  circuit(5 INVX1 location(10100 0)
-   pin(0 12)
-   pin(1 5)
-   pin(2 15)
-   pin(3 12)
-   pin(4 4)
-   pin(5 15)
-  )
-  circuit(6 INVX1 location(11900 0)
-   pin(0 12)
-   pin(1 6)
-   pin(2 15)
-   pin(3 12)
-   pin(4 5)
-   pin(5 15)
-  )
-  circuit(7 INVX1 location(13700 0)
-   pin(0 12)
-   pin(1 7)
-   pin(2 15)
-   pin(3 12)
-   pin(4 6)
-   pin(5 15)
-  )
-  circuit(8 INVX1 location(15500 0)
-   pin(0 12)
-   pin(1 8)
-   pin(2 15)
-   pin(3 12)
-   pin(4 7)
-   pin(5 15)
-  )
-  circuit(9 INVX1 location(17300 0)
-   pin(0 12)
-   pin(1 9)
-   pin(2 15)
-   pin(3 12)
-   pin(4 8)
-   pin(5 15)
-  )
-  circuit(10 INVX1 location(19100 0)
-   pin(0 12)
-   pin(1 10)
-   pin(2 15)
-   pin(3 12)
-   pin(4 9)
-   pin(5 15)
-  )
-  circuit(11 INVX1 location(20900 0)
-   pin(0 12)
-   pin(1 11)
-   pin(2 15)
-   pin(3 12)
-   pin(4 10)
-   pin(5 15)
-  )
-  circuit(12 INVX1 location(24700 0)
-   pin(0 12)
-   pin(1 13)
-   pin(2 15)
-   pin(3 12)
-   pin(4 11)
-   pin(5 15)
-  )
-
- )
-)
-
-# Reference netlist
-reference(
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(B))
-  net(6 name(A))
-  net(7 name(BULK))
-  net(8 name('1'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 6)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 PMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 NMOS
-   name($3)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 NMOS
-   name($4)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4 name(NWELL))
-  pin(5 name(IN))
-  pin(6 name(BULK))
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Nets
-  net(1 name(VSS))
-  net(2 name(VDD))
-  net(3 name(FB))
-  net(4 name(ENABLE))
-  net(5 name(OUT))
-  net(6 name('1'))
-  net(7 name('2'))
-  net(8 name('3'))
-  net(9 name('4'))
-  net(10 name('5'))
-  net(11 name('6'))
-  net(12 name('7'))
-  net(13 name('8'))
-  net(14 name('9'))
-  net(15 name('10'))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VSS))
-  pin(2 name(VDD))
-  pin(3 name(FB))
-  pin(4 name(ENABLE))
-  pin(5 name(OUT))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 name($1)
-   pin(0 2)
-   pin(1 6)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 4)
-   pin(6 1)
-  )
-  circuit(2 INVX1 name($2)
-   pin(0 2)
-   pin(1 7)
-   pin(2 1)
-   pin(3 2)
-   pin(4 6)
-   pin(5 1)
-  )
-  circuit(3 INVX1 name($3)
-   pin(0 2)
-   pin(1 8)
-   pin(2 1)
-   pin(3 2)
-   pin(4 7)
-   pin(5 1)
-  )
-  circuit(4 INVX1 name($4)
-   pin(0 2)
-   pin(1 9)
-   pin(2 1)
-   pin(3 2)
-   pin(4 8)
-   pin(5 1)
-  )
-  circuit(5 INVX1 name($5)
-   pin(0 2)
-   pin(1 10)
-   pin(2 1)
-   pin(3 2)
-   pin(4 9)
-   pin(5 1)
-  )
-  circuit(6 INVX1 name($6)
-   pin(0 2)
-   pin(1 11)
-   pin(2 1)
-   pin(3 2)
-   pin(4 10)
-   pin(5 1)
-  )
-  circuit(7 INVX1 name($7)
-   pin(0 2)
-   pin(1 12)
-   pin(2 1)
-   pin(3 2)
-   pin(4 11)
-   pin(5 1)
-  )
-  circuit(8 INVX1 name($8)
-   pin(0 2)
-   pin(1 13)
-   pin(2 1)
-   pin(3 2)
-   pin(4 12)
-   pin(5 1)
-  )
-  circuit(9 INVX1 name($9)
-   pin(0 2)
-   pin(1 14)
-   pin(2 1)
-   pin(3 2)
-   pin(4 13)
-   pin(5 1)
-  )
-  circuit(10 INVX1 name($10)
-   pin(0 2)
-   pin(1 15)
-   pin(2 1)
-   pin(3 2)
-   pin(4 14)
-   pin(5 1)
-  )
-  circuit(11 INVX1 name($11)
-   pin(0 2)
-   pin(1 3)
-   pin(2 1)
-   pin(3 2)
-   pin(4 15)
-   pin(5 1)
-  )
-  circuit(12 INVX1 name($12)
-   pin(0 2)
-   pin(1 5)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 1)
-  )
-
- )
-)
-
-# Cross reference
-xref(
- circuit(INVX1 INVX1 match
-  xref(
-   net(4 4 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(6 6 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(5 5 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(2 2 match)
-   device(1 1 match)
-  )
- )
- circuit(ND2X1 ND2X1 match
-  xref(
-   net(8 8 match)
-   net(4 4 match)
-   net(6 6 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(7 7 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(5 5 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(6 6 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(3 3 match)
-   device(4 4 match)
-   device(1 1 match)
-   device(2 2 match)
-  )
- )
- circuit(RINGO RINGO match
-  xref(
-   net(1 6 match)
-   net(10 15 match)
-   net(2 7 match)
-   net(3 8 match)
-   net(4 9 match)
-   net(5 10 match)
-   net(6 11 match)
-   net(7 12 match)
-   net(8 13 match)
-   net(9 14 match)
-   net(14 4 match)
-   net(11 3 match)
-   net(13 5 match)
-   net(12 2 match)
-   net(15 1 match)
-   pin(3 3 match)
-   pin(0 2 match)
-   pin(2 4 match)
-   pin(1 1 match)
-   pin(4 0 match)
-   circuit(2 2 match)
-   circuit(3 3 match)
-   circuit(4 4 match)
-   circuit(5 5 match)
-   circuit(6 6 match)
-   circuit(7 7 match)
-   circuit(8 8 match)
-   circuit(9 9 match)
-   circuit(10 10 match)
-   circuit(11 11 match)
-   circuit(12 12 match)
-   circuit(1 1 match)
-  )
- )
-)