From c7ee35a4e39f86961056daea25a047b03a1b9589 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 1 Sep 2019 17:37:23 +0200 Subject: [PATCH] WIP: documentation --- src/lay/lay/doc/manual/lvs_compare.xml | 5 ++-- src/lay/lay/doc/manual/lvs_connect.xml | 2 +- src/lay/lay/doc/manual/lvs_intro.xml | 32 +++++++++++++++++++++++++- src/lay/lay/doc/manual/lvs_tweaks.xml | 11 +++++++-- src/lay/lay/doc/manual/net_tracing.xml | 2 +- 5 files changed, 45 insertions(+), 7 deletions(-) diff --git a/src/lay/lay/doc/manual/lvs_compare.xml b/src/lay/lay/doc/manual/lvs_compare.xml index 72e60825e..01dd882fc 100644 --- a/src/lay/lay/doc/manual/lvs_compare.xml +++ b/src/lay/lay/doc/manual/lvs_compare.xml @@ -46,7 +46,7 @@ 
same_nets("LOGIC", "VDD", "VDD:P")

- In this example it is assumed that the power net is labelled "VDD" in the + In this example it is assumed that the power net is labeled "VDD" in the layout and called "VDD:P" in the schematic. Don't leave this statement in the script for final verification as it may mask real errors.

@@ -160,7 +160,8 @@ same_device_classes("NMOS_IN_LAYOUT", "NMOS_IN_SCHEMATIC")

- In general, it's a good idea to include "align" before the "compare" step. + In general, it's a good idea to include "align" before "netlist.simplify" or + similar netlist manipulation and the "compare" step.

diff --git a/src/lay/lay/doc/manual/lvs_connect.xml b/src/lay/lay/doc/manual/lvs_connect.xml index d05b817d7..e47efff0e 100644 --- a/src/lay/lay/doc/manual/lvs_connect.xml +++ b/src/lay/lay/doc/manual/lvs_connect.xml @@ -70,7 +70,7 @@ connect(metal2, metal2_labels)

If labels are connected to metal layers, their text strings will be used to assign - net names to the resulting nets. Ideally, one net is labelled with a single text + net names to the resulting nets. Ideally, one net is labeled with a single text or with texts with the same text string. In this case, the net name will be non-ambiguous. If multiple labels with different strings are present on a net, the net name will be made from a combination of these names. diff --git a/src/lay/lay/doc/manual/lvs_intro.xml b/src/lay/lay/doc/manual/lvs_intro.xml index d3278dd8e..ebd4cd94e 100644 --- a/src/lay/lay/doc/manual/lvs_intro.xml +++ b/src/lay/lay/doc/manual/lvs_intro.xml @@ -156,6 +156,9 @@ connect_global(nwell, "NWELL") schematic("inv.cir") +align # flattens unpaired circuits +netlist.simplify # removes floating nets, combines devices + compare

@@ -336,11 +339,35 @@ connect_global(nwell, "NWELL")

We have now provided all the essential inputs for the netlist formation. - We only have to specify the reference netlist: + We now have to specify the reference netlist: 

schematic("inv.cir")
+

+ Two optional, but recommended steps are hierarchy alignment and extracted + netlist simplification: +

+ + 
align              # flattens unpaired circuits 
+netlist.simplify   # removes floating nets, combines devices
+
+ +

+ "align" will remove circuits which are not present in the other netlist by + integrating their content into the parent cell. This will remove auxiliary cells + which are usually present in a layout but don't map to a schematic cell (e.g. + device PCells). "netlist.simplify" reduces the netlist by floating nets, + performs device combination (e.g. fingered transistors). This method will + also create pins from labeled nets in the top level circuit. +

+ +

+ The order should be "align", then "netlist.simplify". Both have to happen before + "compare" to be effective. "align" is described in , + "netlist.simplify" in . +

+

Finally after having set this up, we can trigger the compare step:

@@ -498,6 +525,9 @@ connect_global(ptie, "SUBSTRATE") schematic("inv2.cir") +align +netlist.simplify + compare

diff --git a/src/lay/lay/doc/manual/lvs_tweaks.xml b/src/lay/lay/doc/manual/lvs_tweaks.xml index 997104258..f0300a18d 100644 --- a/src/lay/lay/doc/manual/lvs_tweaks.xml +++ b/src/lay/lay/doc/manual/lvs_tweaks.xml @@ -41,7 +41,7 @@

KLayout offers a function to create top-level pins using - a simple heuristics: for every named (i.e. labelled) net in the top level + a simple heuristics: for every named (i.e. labeled) net in the top level circuit a pin will be created ():

@@ -199,9 +199,16 @@ netlist.purge_nets

is a wrapper for "make_top_level_pins", - "combine_devices" and "purge" in the recommended order: + "purge", "combine_devices" and "purge_nets" in this recommended order: 

netlist.simplify
+

+ As a technical detail, "make_top_level_pins" is included in this sequence as with + pins, nets are not considered floating. So "purge_nets" will maintain pins for + labeled nets even if these nets are not connected to devices. This allows adding + optional pins while maintaining the top level circuit's interface. +

+ diff --git a/src/lay/lay/doc/manual/net_tracing.xml b/src/lay/lay/doc/manual/net_tracing.xml index 6c8b3a416..cdb8a1271 100644 --- a/src/lay/lay/doc/manual/net_tracing.xml +++ b/src/lay/lay/doc/manual/net_tracing.xml @@ -101,7 +101,7 @@
  • Export all or selected nets to layout, save the netlist (with shapes) to a file, load it back from a file and manage the netlist database. Use the "File" menu button in the right upper corner.
    • -
  • Search for net names (if labelled) and circuits using the search edit box. +
  • Search for net names (if labeled) and circuits using the search edit box.
  • Navigate through the history using the "back" and "forward" buttons at the top left.