diff --git a/src/db/db/dbNetlistCompare.cc b/src/db/db/dbNetlistCompare.cc
index c9103b7c7..5c63f95c7 100644
--- a/src/db/db/dbNetlistCompare.cc
+++ b/src/db/db/dbNetlistCompare.cc
@@ -4145,6 +4145,8 @@ NetlistComparer::do_subcircuit_assignment (const db::Circuit *c1, const db::NetG
           ++nscm;
           if (scc.equals (scm->second, std::make_pair (sc.operator-> (), sc_cat))) {
             found = true;
+          } else {
+            ++scm;
           }
         }
 
diff --git a/src/lvs/unit_tests/lvsSimpleTests.cc b/src/lvs/unit_tests/lvsSimpleTests.cc
index 44ee2133e..f82345c11 100644
--- a/src/lvs/unit_tests/lvsSimpleTests.cc
+++ b/src/lvs/unit_tests/lvsSimpleTests.cc
@@ -187,3 +187,9 @@ TEST(21_split_gate)
   run_test (_this, "nand2_split_gate", "nand2_split_gate.oas");
 }
 
+//  empty gds
+TEST(23_issue709)
+{
+  run_test (_this, "empty_subcells", "empty_subcells.gds");
+}
+
diff --git a/testdata/lvs/empty_subcells.cir b/testdata/lvs/empty_subcells.cir
new file mode 100644
index 000000000..8c16d33c2
--- /dev/null
+++ b/testdata/lvs/empty_subcells.cir
@@ -0,0 +1,25 @@
+* Extracted by KLayout
+
+* cell empty_subcells
+.SUBCKT empty_subcells
+* cell instance $1 r0 *1 0,0
+X$1 1 2 blockB
+* cell instance $2 r0 *1 310,0
+X$2 1 2 blockA
+.ENDS empty_subcells
+
+* cell blockB
+* pin V
+* pin W
+.SUBCKT blockB 1 2
+* net 1 V
+* net 2 W
+.ENDS blockB
+
+* cell blockA
+* pin A
+* pin B
+.SUBCKT blockA 1 2
+* net 1 A
+* net 2 B
+.ENDS blockA
diff --git a/testdata/lvs/empty_subcells.gds b/testdata/lvs/empty_subcells.gds
new file mode 100644
index 000000000..1db25bd36
Binary files /dev/null and b/testdata/lvs/empty_subcells.gds differ
diff --git a/testdata/lvs/empty_subcells.lvs b/testdata/lvs/empty_subcells.lvs
new file mode 100644
index 000000000..949f73f30
--- /dev/null
+++ b/testdata/lvs/empty_subcells.lvs
@@ -0,0 +1,21 @@
+
+source($lvs_test_source)
+report_lvs($lvs_test_target_lvsdb, true)
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("empty_subcells_sch.cir")
+
+deep
+
+m1  = input(1, 0)
+via  = input(2, 0)
+m2  = input(3, 0)
+lab  = labels(254,0)
+
+connect(m1,  via)
+connect(via, m2)
+connect(m2, lab)
+
+netlist.make_top_level_pins
+compare
+
diff --git a/testdata/lvs/empty_subcells.lvsdb b/testdata/lvs/empty_subcells.lvsdb
new file mode 100644
index 000000000..81138e85d
--- /dev/null
+++ b/testdata/lvs/empty_subcells.lvsdb
@@ -0,0 +1,167 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(empty_subcells)
+ unit(1)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1 '1/0')
+ layer(l2 '2/0')
+ layer(l3 '3/0')
+ layer(l4 '254/0')
+
+ # Mask layer connectivity
+ connect(l1 l1 l2)
+ connect(l2 l1 l2 l3)
+ connect(l3 l2 l3 l4)
+ connect(l4 l3)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(blockA
+
+  # Circuit boundary
+  rect((100 10) (30 80))
+
+  # Nets with their geometries
+  net(1 name(A)
+   rect(l3 (100 60) (30 30))
+   text(l4 A (-10 -10))
+  )
+  net(2 name(B)
+   rect(l3 (100 10) (30 30))
+   text(l4 B (-10 -10))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(blockB
+
+  # Circuit boundary
+  rect((100 10) (30 80))
+
+  # Nets with their geometries
+  net(1 name(V)
+   rect(l3 (100 60) (30 30))
+   text(l4 V (-10 -10))
+  )
+  net(2 name(W)
+   rect(l3 (100 10) (30 30))
+   text(l4 W (-10 -10))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(V))
+  pin(2 name(W))
+
+ )
+ circuit(empty_subcells
+
+  # Circuit boundary
+  rect((100 10) (340 80))
+
+  # Nets with their geometries
+  net(1
+   rect(l1 (180 60) (90 30))
+   rect(l2 (-160 -20) (90 10))
+   rect(l2 (40 -10) (180 10))
+  )
+  net(2
+   rect(l1 (180 10) (90 30))
+   rect(l2 (-160 -20) (90 10))
+   rect(l2 (40 -10) (180 10))
+  )
+
+  # Subcircuits and their connections
+  circuit(1 blockB location(0 0)
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 blockA location(310 0)
+   pin(0 1)
+   pin(1 2)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(BLOCKA
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+
+ )
+ circuit(BLOCKB
+
+  # Nets
+  net(1 name(V))
+  net(2 name(W))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(V))
+  pin(2 name(W))
+
+ )
+ circuit(EMPTY_SUBCELLS
+
+  # Nets
+  net(1 name(E))
+  net(2 name(F))
+
+  # Subcircuits and their connections
+  circuit(1 BLOCKA name('1')
+   pin(0 1)
+   pin(1 2)
+  )
+  circuit(2 BLOCKB name('2')
+   pin(0 1)
+   pin(1 2)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(blockA BLOCKA match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(blockB BLOCKB match
+  xref(
+   net(1 1 match)
+   net(2 2 match)
+   pin(0 0 match)
+   pin(1 1 match)
+  )
+ )
+ circuit(empty_subcells EMPTY_SUBCELLS match
+  xref(
+   net(1 1 warning)
+   net(2 2 warning)
+   circuit(2 1 match)
+   circuit(1 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/empty_subcells_sch.cir b/testdata/lvs/empty_subcells_sch.cir
new file mode 100644
index 000000000..6e6cbceee
--- /dev/null
+++ b/testdata/lvs/empty_subcells_sch.cir
@@ -0,0 +1,12 @@
+
+
+.subckt blockA a b
+.ends
+
+.subckt blockB v w
+.ends
+
+.subckt empty_subcells
+X1 e f blockA
+X2 e f blockB
+.ends