From e0be042e675a0306c5080f45f653b0a56613a087 Mon Sep 17 00:00:00 2001
From: Matthias Koefferlein <matthias@koefferlein.de>
Date: Sun, 15 Dec 2019 20:48:56 +0100
Subject: [PATCH] Test data update for CentOS 6

---
 .../lvs/ringo_simple_dummy_device.lvsdb.3     |  965 +++++++++++++++
 .../lvs/ringo_simple_simplification.lvsdb.3   | 1095 +++++++++++++++++
 ...o_simple_simplification_with_align.lvsdb.3 | 1095 +++++++++++++++++
 3 files changed, 3155 insertions(+)
 create mode 100644 testdata/lvs/ringo_simple_dummy_device.lvsdb.3
 create mode 100644 testdata/lvs/ringo_simple_simplification.lvsdb.3
 create mode 100644 testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3

diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.3
new file mode 100644
index 000000000..8fc3eac47
--- /dev/null
+++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.3
@@ -0,0 +1,965 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1151 -401) (2 2))
+   rect(l2 (-276 -2151) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-141 -501) (2 2))
+   rect(l11 (-1751 1099) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-1750 -1450) (425 1500))
+   rect(l2 (950 -1500) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1151 -401) (2 2))
+   rect(l6 (-951 859) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-71 -91) (2 2))
+   rect(l11 (-171 -151) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS$1
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$2
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (299 399) (2 2))
+   rect(l2 (-651 -2151) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-151 -2501) (2 2))
+   rect(l2 (-226 1049) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-851 -401) (2 2))
+   rect(l6 (-651 859) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (27600 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l4 (26050 2800) (525 550))
+   rect(l4 (-525 -300) (300 300))
+   rect(l4 (-25 -2000) (250 1450))
+   rect(l8 (-465 310) (180 180))
+   rect(l11 (-240 -240) (300 300))
+  )
+  net(2
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(3
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(4
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(5
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(6
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(7
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(8
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(9
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(10
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(11
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(12 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17921 -201) (2 2))
+   rect(l13 (-221 -201) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(13 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l3 (0 -3500) (600 3500))
+   rect(l3 (0 -3500) (600 3500))
+   rect(l3 (0 -3500) (600 3500))
+   rect(l8 (-26490 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21741 859) (2 2))
+   rect(l11 (-2351 -451) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-101 -351) (2 2))
+   rect(l11 (-1251 -401) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-101 -351) (2 2))
+   rect(l11 (549 -401) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l9 (-26650 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(14 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-101 -101) (2 2))
+   rect(l13 (-201 -201) (400 400))
+  )
+  net(15 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-101 -101) (2 2))
+   rect(l13 (-201 -201) (400 400))
+  )
+  net(16 name(VSS)
+   rect(l8 (26010 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (520 -730) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-25780 -890) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (1260 -40) (300 1360))
+   rect(l11 (400 -1360) (300 1360))
+   rect(l11 (-24001 -1711) (2 2))
+   rect(l11 (-1901 -401) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-551 -401) (2 2))
+   rect(l11 (-1251 -401) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-551 -401) (2 2))
+   rect(l11 (549 -401) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l6 (-1025 400) (425 950))
+   rect(l6 (-1100 -950) (425 950))
+   rect(l10 (-25375 -2150) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(12 name(FB))
+  pin(13 name(VDD))
+  pin(14 name(OUT))
+  pin(15 name(ENABLE))
+  pin(16 name(VSS))
+
+  # Devices and their connections
+  device(1 D$NMOS
+   location(26450 2075)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 16)
+   terminal(G 1)
+   terminal(D 16)
+   terminal(B 16)
+  )
+
+  # Subcircuits and their connections
+  circuit(3 ND2X1 location(1800 0)
+   pin(0 13)
+   pin(1 2)
+   pin(2 16)
+   pin(3 13)
+   pin(4 12)
+   pin(5 15)
+   pin(6 16)
+  )
+  circuit(4 INVX1 location(4200 0)
+   pin(0 13)
+   pin(1 3)
+   pin(2 16)
+   pin(3 13)
+   pin(4 2)
+   pin(5 16)
+  )
+  circuit(5 INVX1 location(6000 0)
+   pin(0 13)
+   pin(1 4)
+   pin(2 16)
+   pin(3 13)
+   pin(4 3)
+   pin(5 16)
+  )
+  circuit(6 INVX1 location(7800 0)
+   pin(0 13)
+   pin(1 5)
+   pin(2 16)
+   pin(3 13)
+   pin(4 4)
+   pin(5 16)
+  )
+  circuit(7 INVX1 location(9600 0)
+   pin(0 13)
+   pin(1 6)
+   pin(2 16)
+   pin(3 13)
+   pin(4 5)
+   pin(5 16)
+  )
+  circuit(8 INVX1 location(11400 0)
+   pin(0 13)
+   pin(1 7)
+   pin(2 16)
+   pin(3 13)
+   pin(4 6)
+   pin(5 16)
+  )
+  circuit(9 INVX1 location(13200 0)
+   pin(0 13)
+   pin(1 8)
+   pin(2 16)
+   pin(3 13)
+   pin(4 7)
+   pin(5 16)
+  )
+  circuit(10 INVX1 location(15000 0)
+   pin(0 13)
+   pin(1 9)
+   pin(2 16)
+   pin(3 13)
+   pin(4 8)
+   pin(5 16)
+  )
+  circuit(11 INVX1 location(16800 0)
+   pin(0 13)
+   pin(1 10)
+   pin(2 16)
+   pin(3 13)
+   pin(4 9)
+   pin(5 16)
+  )
+  circuit(12 INVX1 location(18600 0)
+   pin(0 13)
+   pin(1 11)
+   pin(2 16)
+   pin(3 13)
+   pin(4 10)
+   pin(5 16)
+  )
+  circuit(13 INVX1 location(20400 0)
+   pin(0 13)
+   pin(1 12)
+   pin(2 16)
+   pin(3 13)
+   pin(4 11)
+   pin(5 16)
+  )
+  circuit(14 INVX1 location(22200 0)
+   pin(0 13)
+   pin(1 14)
+   pin(2 16)
+   pin(3 13)
+   pin(4 12)
+   pin(5 16)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(NMOS MOS4)
+ class(PMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+  net(16 name(DUMMY))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Devices and their connections
+  device(1 NMOS
+   name($1)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 16)
+   terminal(D 1)
+   terminal(B 1)
+  )
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(2 6 match)
+   net(11 15 match)
+   net(3 7 match)
+   net(4 8 match)
+   net(5 9 match)
+   net(6 10 match)
+   net(7 11 match)
+   net(8 12 match)
+   net(9 13 match)
+   net(10 14 match)
+   net(1 16 match)
+   net(15 4 match)
+   net(12 3 match)
+   net(14 5 match)
+   net(13 2 match)
+   net(16 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   device(1 1 match)
+   circuit(4 2 match)
+   circuit(5 3 match)
+   circuit(6 4 match)
+   circuit(7 5 match)
+   circuit(8 6 match)
+   circuit(9 7 match)
+   circuit(10 8 match)
+   circuit(11 9 match)
+   circuit(12 10 match)
+   circuit(13 11 match)
+   circuit(14 12 match)
+   circuit(3 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.3 b/testdata/lvs/ringo_simple_simplification.lvsdb.3
new file mode 100644
index 000000000..53ac9099a
--- /dev/null
+++ b/testdata/lvs/ringo_simple_simplification.lvsdb.3
@@ -0,0 +1,1095 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1151 -401) (2 2))
+   rect(l2 (-276 -2151) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-141 -501) (2 2))
+   rect(l11 (-1751 1099) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-1750 -1450) (425 1500))
+   rect(l2 (950 -1500) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1151 -401) (2 2))
+   rect(l6 (-951 859) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-71 -91) (2 2))
+   rect(l11 (-171 -151) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (299 399) (2 2))
+   rect(l2 (-651 -2151) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-151 -2501) (2 2))
+   rect(l2 (-226 1049) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-851 -401) (2 2))
+   rect(l6 (-651 859) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-225 -1300) (675 450))
+   rect(l4 (0 -1100) (250 1950))
+   rect(l4 (-1225 -1850) (300 300))
+   rect(l4 (675 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-950 -2000) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (450 -5390) (250 1450))
+   rect(l4 (-950 -1450) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(2 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-1640 -240) (300 1400))
+   rect(l11 (-650 300) (2400 800))
+   rect(l11 (-2050 -1100) (300 300))
+   rect(l11 (1100 -300) (300 300))
+   rect(l11 (-1101 399) (2 2))
+   rect(l11 (799 -2101) (300 1400))
+   rect(l2 (-1750 -1450) (425 1500))
+   rect(l2 (950 -1500) (425 1500))
+  )
+  net(3 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-151 -2501) (2 2))
+   rect(l2 (-226 1049) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+   rect(l6 (-450 -4890) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+  net(4 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (1220 -730) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-1640 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-650 0) (300 1360))
+   rect(l11 (-1101 -1761) (2 2))
+   rect(l6 (724 859) (425 950))
+   rect(l6 (-1800 -950) (425 950))
+  )
+  net(5
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(IN))
+  pin(2 name(VDD))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5)
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 5800)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0.975)
+   param(AD 0.975)
+   param(PS 5.8)
+   param(PD 5.8)
+   terminal(S 2)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 2135)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0.6175)
+   param(AD 0.6175)
+   param(PS 4.15)
+   param(PD 4.15)
+   terminal(S 4)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((600 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(4
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(5 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17921 -201) (2 2))
+   rect(l13 (-221 -201) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(6 name(VDD)
+   rect(l3 (1100 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-22341 859) (2 2))
+   rect(l11 (-1751 -451) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-101 -351) (2 2))
+   rect(l11 (-1251 -401) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-101 -351) (2 2))
+   rect(l11 (549 -401) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(7 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-101 -101) (2 2))
+   rect(l13 (-201 -201) (400 400))
+  )
+  net(8 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-101 -101) (2 2))
+   rect(l13 (-201 -201) (400 400))
+  )
+  net(9 name(VSS)
+   rect(l8 (1710 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-22341 -391) (2 2))
+   rect(l11 (-1301 -401) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-551 -401) (2 2))
+   rect(l11 (-1251 -401) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-551 -401) (2 2))
+   rect(l11 (549 -401) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+  net(10
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(11
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(12
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(13
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(14
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(15
+   rect(l11 (14550 2950) (900 300))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(FB))
+  pin(6 name(VDD))
+  pin(7 name(OUT))
+  pin(8 name(ENABLE))
+  pin(9 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 6)
+   pin(1 1)
+   pin(2 9)
+   pin(3 6)
+   pin(4 5)
+   pin(5 8)
+   pin(6 9)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 6)
+   pin(1 2)
+   pin(2 9)
+   pin(3 6)
+   pin(4 1)
+   pin(5 9)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 6)
+   pin(1 10)
+   pin(2 9)
+   pin(3 6)
+   pin(4 2)
+   pin(5 9)
+  )
+  circuit(4 INVX1 location(16800 0)
+   pin(0 6)
+   pin(1 3)
+   pin(2 9)
+   pin(3 6)
+   pin(4 11)
+   pin(5 9)
+  )
+  circuit(5 INVX1 location(18600 0)
+   pin(0 6)
+   pin(1 4)
+   pin(2 9)
+   pin(3 6)
+   pin(4 3)
+   pin(5 9)
+  )
+  circuit(6 INVX1 location(20400 0)
+   pin(0 6)
+   pin(1 5)
+   pin(2 9)
+   pin(3 6)
+   pin(4 4)
+   pin(5 9)
+  )
+  circuit(7 INVX2 location(22200 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 9)
+   pin(4 6)
+   pin(5 9)
+  )
+  circuit(17 INVX1 location(7800 0)
+   pin(0 6)
+   pin(1 12)
+   pin(2 9)
+   pin(3 6)
+   pin(4 10)
+   pin(5 9)
+  )
+  circuit(18 INVX1 location(9600 0)
+   pin(0 6)
+   pin(1 13)
+   pin(2 9)
+   pin(3 6)
+   pin(4 12)
+   pin(5 9)
+  )
+  circuit(19 INVX1 location(11400 0)
+   pin(0 6)
+   pin(1 14)
+   pin(2 9)
+   pin(3 6)
+   pin(4 13)
+   pin(5 9)
+  )
+  circuit(20 INVX1 location(13200 0)
+   pin(0 6)
+   pin(1 15)
+   pin(2 9)
+   pin(3 6)
+   pin(4 14)
+   pin(5 9)
+  )
+  circuit(21 INVX1 location(15000 0)
+   pin(0 6)
+   pin(1 11)
+   pin(2 9)
+   pin(3 6)
+   pin(4 15)
+   pin(5 9)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX2 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INVX2 INVX2 match
+  xref(
+   net(5 4 match)
+   net(1 5 match)
+   net(3 2 match)
+   net(6 6 match)
+   net(2 1 match)
+   net(4 3 match)
+   pin(4 3 match)
+   pin(0 4 match)
+   pin(2 1 match)
+   pin(5 5 match)
+   pin(1 0 match)
+   pin(3 2 match)
+   device(3 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(4 15 match)
+   net(2 7 match)
+   net(10 8 match)
+   net(12 9 match)
+   net(13 10 match)
+   net(14 11 match)
+   net(15 12 match)
+   net(11 13 match)
+   net(3 14 match)
+   net(8 4 match)
+   net(5 3 match)
+   net(7 5 match)
+   net(6 2 match)
+   net(9 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(17 4 match)
+   circuit(18 5 match)
+   circuit(19 6 match)
+   circuit(20 7 match)
+   circuit(21 8 match)
+   circuit(4 9 match)
+   circuit(5 10 match)
+   circuit(6 11 match)
+   circuit(7 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3
new file mode 100644
index 000000000..be1456dd3
--- /dev/null
+++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3
@@ -0,0 +1,1095 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1151 -401) (2 2))
+   rect(l2 (-276 -2151) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-141 -501) (2 2))
+   rect(l11 (-1751 1099) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-1750 -1450) (425 1500))
+   rect(l2 (950 -1500) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1151 -401) (2 2))
+   rect(l6 (-951 859) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-71 -91) (2 2))
+   rect(l11 (-171 -151) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (299 399) (2 2))
+   rect(l2 (-651 -2151) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-151 -2501) (2 2))
+   rect(l2 (-226 1049) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-851 -401) (2 2))
+   rect(l6 (-651 859) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-225 -1300) (675 450))
+   rect(l4 (0 -1100) (250 1950))
+   rect(l4 (-1225 -1850) (300 300))
+   rect(l4 (675 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-950 -2000) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (450 -5390) (250 1450))
+   rect(l4 (-950 -1450) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-91 -91) (2 2))
+   rect(l11 (-151 -151) (300 300))
+  )
+  net(2 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-1640 -240) (300 1400))
+   rect(l11 (-650 300) (2400 800))
+   rect(l11 (-2050 -1100) (300 300))
+   rect(l11 (1100 -300) (300 300))
+   rect(l11 (-1101 399) (2 2))
+   rect(l11 (799 -2101) (300 1400))
+   rect(l2 (-1750 -1450) (425 1500))
+   rect(l2 (950 -1500) (425 1500))
+  )
+  net(3 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-151 -2501) (2 2))
+   rect(l2 (-226 1049) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+   rect(l6 (-450 -4890) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+  net(4 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (1220 -730) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-1640 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-650 0) (300 1360))
+   rect(l11 (-1101 -1761) (2 2))
+   rect(l6 (724 859) (425 950))
+   rect(l6 (-1800 -950) (425 950))
+  )
+  net(5
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(IN))
+  pin(2 name(VDD))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5)
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 5800)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0.975)
+   param(AD 0.975)
+   param(PS 5.8)
+   param(PD 5.8)
+   terminal(S 2)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 2135)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0.6175)
+   param(AD 0.6175)
+   param(PS 4.15)
+   param(PD 4.15)
+   terminal(S 4)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((600 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(4
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(5 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17921 -201) (2 2))
+   rect(l13 (-221 -201) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(6 name(VDD)
+   rect(l3 (1100 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-22341 859) (2 2))
+   rect(l11 (-1751 -451) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-101 -351) (2 2))
+   rect(l11 (-1251 -401) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-101 -351) (2 2))
+   rect(l11 (549 -401) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(7 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-101 -101) (2 2))
+   rect(l13 (-201 -201) (400 400))
+  )
+  net(8 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-101 -101) (2 2))
+   rect(l13 (-201 -201) (400 400))
+  )
+  net(9 name(VSS)
+   rect(l8 (1710 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-22341 -391) (2 2))
+   rect(l11 (-1301 -401) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-551 -401) (2 2))
+   rect(l11 (-1251 -401) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-551 -401) (2 2))
+   rect(l11 (549 -401) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+  net(10
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(11
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(12
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(13
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(14
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(15
+   rect(l11 (14550 2950) (900 300))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(FB))
+  pin(6 name(VDD))
+  pin(7 name(OUT))
+  pin(8 name(ENABLE))
+  pin(9 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 6)
+   pin(1 1)
+   pin(2 9)
+   pin(3 6)
+   pin(4 5)
+   pin(5 8)
+   pin(6 9)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 6)
+   pin(1 2)
+   pin(2 9)
+   pin(3 6)
+   pin(4 1)
+   pin(5 9)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 6)
+   pin(1 10)
+   pin(2 9)
+   pin(3 6)
+   pin(4 2)
+   pin(5 9)
+  )
+  circuit(4 INVX1 location(16800 0)
+   pin(0 6)
+   pin(1 3)
+   pin(2 9)
+   pin(3 6)
+   pin(4 11)
+   pin(5 9)
+  )
+  circuit(5 INVX1 location(18600 0)
+   pin(0 6)
+   pin(1 4)
+   pin(2 9)
+   pin(3 6)
+   pin(4 3)
+   pin(5 9)
+  )
+  circuit(6 INVX1 location(20400 0)
+   pin(0 6)
+   pin(1 5)
+   pin(2 9)
+   pin(3 6)
+   pin(4 4)
+   pin(5 9)
+  )
+  circuit(7 INVX2 location(22200 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 9)
+   pin(4 6)
+   pin(5 9)
+  )
+  circuit(13 INVX1 location(7800 0)
+   pin(0 6)
+   pin(1 12)
+   pin(2 9)
+   pin(3 6)
+   pin(4 10)
+   pin(5 9)
+  )
+  circuit(14 INVX1 location(9600 0)
+   pin(0 6)
+   pin(1 13)
+   pin(2 9)
+   pin(3 6)
+   pin(4 12)
+   pin(5 9)
+  )
+  circuit(15 INVX1 location(11400 0)
+   pin(0 6)
+   pin(1 14)
+   pin(2 9)
+   pin(3 6)
+   pin(4 13)
+   pin(5 9)
+  )
+  circuit(16 INVX1 location(13200 0)
+   pin(0 6)
+   pin(1 15)
+   pin(2 9)
+   pin(3 6)
+   pin(4 14)
+   pin(5 9)
+  )
+  circuit(17 INVX1 location(15000 0)
+   pin(0 6)
+   pin(1 11)
+   pin(2 9)
+   pin(3 6)
+   pin(4 15)
+   pin(5 9)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX2 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INVX2 INVX2 match
+  xref(
+   net(5 4 match)
+   net(1 5 match)
+   net(3 2 match)
+   net(6 6 match)
+   net(2 1 match)
+   net(4 3 match)
+   pin(4 3 match)
+   pin(0 4 match)
+   pin(2 1 match)
+   pin(5 5 match)
+   pin(1 0 match)
+   pin(3 2 match)
+   device(3 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(4 15 match)
+   net(2 7 match)
+   net(10 8 match)
+   net(12 9 match)
+   net(13 10 match)
+   net(14 11 match)
+   net(15 12 match)
+   net(11 13 match)
+   net(3 14 match)
+   net(8 4 match)
+   net(5 3 match)
+   net(7 5 match)
+   net(6 2 match)
+   net(9 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(13 4 match)
+   circuit(14 5 match)
+   circuit(15 6 match)
+   circuit(16 7 match)
+   circuit(17 8 match)
+   circuit(4 9 match)
+   circuit(5 10 match)
+   circuit(6 11 match)
+   circuit(7 12 match)
+   circuit(1 1 match)
+  )
+ )
+)