From af30695ab34a7cecb6c7425af487a575b825a9c0 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sat, 7 Jan 2023 21:56:25 +0100 Subject: [PATCH] WIP: experimental - introducing net DRC, first steps --- src/db/db/dbLayoutToNetlist.cc | 34 +++-- src/db/db/dbLayoutToNetlist.h | 49 +++++- src/db/db/gsiDeclDbLayoutToNetlist.cc | 6 +- src/db/unit_tests/dbHierNetsProcessorTests.cc | 138 +++++++++++++++++ .../dbLayoutToNetlistReaderTests.cc | 20 +-- src/db/unit_tests/dbLayoutToNetlistTests.cc | 14 +- .../dbLayoutToNetlistWriterTests.cc | 4 +- src/db/unit_tests/unit_tests.pro | 141 +++++++++--------- src/layui/layui/layNetlistBrowserPage.cc | 1 + 9 files changed, 298 insertions(+), 109 deletions(-) create mode 100644 src/db/unit_tests/dbHierNetsProcessorTests.cc diff --git a/src/db/db/dbLayoutToNetlist.cc b/src/db/db/dbLayoutToNetlist.cc index fce467f85..8fd048aa0 100644 --- a/src/db/db/dbLayoutToNetlist.cc +++ b/src/db/db/dbLayoutToNetlist.cc @@ -984,9 +984,17 @@ LayoutToNetlist::build_net_rec (db::cell_index_type ci, size_t cid, db::Layout & } db::properties_id_type -LayoutToNetlist::make_netname_propid (db::Layout &ly, const tl::Variant &netname_prop, const db::Net &net) const +LayoutToNetlist::make_netname_propid (db::Layout &ly, NetPropertyMode net_prop_mode, const tl::Variant &netname_prop, const db::Net &net) const { - if (! netname_prop.is_nil () || net.begin_properties () != net.end_properties ()) { + if (net_prop_mode == FakePropId) { + + return reinterpret_cast (&net); + + } else if (net_prop_mode == NoProperties) { + + return 0; + + } else if (! netname_prop.is_nil () || (net_prop_mode == AllProperties && net.begin_properties () != net.end_properties ())) { db::PropertiesRepository::properties_set propset; @@ -998,18 +1006,24 @@ LayoutToNetlist::make_netname_propid (db::Layout &ly, const tl::Variant &netname if (! netname_prop.is_nil ()) { db::property_names_id_type name_propnameid = ly.properties_repository ().prop_name_id (netname_prop); - propset.insert (std::make_pair (name_propnameid, tl::Variant (net.expanded_name ()))); + if (net_prop_mode == NetIDOnly) { + propset.insert (std::make_pair (name_propnameid, tl::Variant (reinterpret_cast (&net)))); + } else { + propset.insert (std::make_pair (name_propnameid, tl::Variant (net.expanded_name ()))); + } } return ly.properties_repository ().properties_id (propset); } else { + return 0; + } } void -LayoutToNetlist::build_net (const db::Net &net, db::Layout &target, db::Cell &target_cell, const std::map &lmap, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *cell_name_prefix, const char *device_cell_name_prefix) const +LayoutToNetlist::build_net (const db::Net &net, db::Layout &target, db::Cell &target_cell, const std::map &lmap, NetPropertyMode net_prop_mode, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *cell_name_prefix, const char *device_cell_name_prefix) const { if (! m_netlist_extracted) { throw tl::Exception (tl::to_string (tr ("The netlist has not been extracted yet"))); @@ -1019,14 +1033,14 @@ LayoutToNetlist::build_net (const db::Net &net, db::Layout &target, db::Cell &ta double mag = internal_layout ()->dbu () / target.dbu (); - db::properties_id_type netname_propid = make_netname_propid (target, netname_prop, net); + db::properties_id_type netname_propid = make_netname_propid (target, net_prop_mode, netname_prop, net); build_net_rec (net, target, target_cell, lmap, 0, netname_propid, hier_mode, cell_name_prefix, device_cell_name_prefix, cell_reuse_table, db::ICplxTrans (mag)); } void -LayoutToNetlist::build_all_nets (const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const +LayoutToNetlist::build_all_nets (const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, NetPropertyMode net_prop_mode, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const { - build_nets (0, cmap, target, lmap, net_cell_name_prefix, netname_prop, hier_mode, circuit_cell_name_prefix, device_cell_name_prefix); + build_nets (0, cmap, target, lmap, net_cell_name_prefix, net_prop_mode, netname_prop, hier_mode, circuit_cell_name_prefix, device_cell_name_prefix); } void @@ -1059,7 +1073,7 @@ LayoutToNetlist::build_net_rec (const db::Net &net, db::Layout &target, db::cell } void -LayoutToNetlist::build_nets (const std::vector *nets, const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const +LayoutToNetlist::build_nets (const std::vector *nets, const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, NetPropertyMode net_prop_mode, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const { if (! m_netlist_extracted) { throw tl::Exception (tl::to_string (tr ("The netlist has not been extracted yet"))); @@ -1085,7 +1099,7 @@ LayoutToNetlist::build_nets (const std::vector *nets, const db: } if (! nets || net_set.find (n.operator-> ()) != net_set.end ()) { - db::properties_id_type netname_propid = make_netname_propid (target, netname_prop, *n); + db::properties_id_type netname_propid = make_netname_propid (target, net_prop_mode, netname_prop, *n); build_net_rec (*n, target, c->cell_index (), cmap, lmap, net_cell_name_prefix, netname_propid, hier_mode, circuit_cell_name_prefix, device_cell_name_prefix, cell_reuse_table, db::ICplxTrans ()); } @@ -1114,7 +1128,7 @@ LayoutToNetlist::build_nets (const std::vector *nets, const db: double dbu = target.dbu (); db::ICplxTrans tr = db::CplxTrans (dbu).inverted () * subcircuit.trans () * db::CplxTrans (dbu); - db::properties_id_type netname_propid = make_netname_propid (target, netname_prop, *n); + db::properties_id_type netname_propid = make_netname_propid (target, net_prop_mode, netname_prop, *n); if (net_cell_name_prefix) { std::string ncn = std::string (net_cell_name_prefix) + subcircuit.expanded_name () + ":"; diff --git a/src/db/db/dbLayoutToNetlist.h b/src/db/db/dbLayoutToNetlist.h index a032b38d5..613f0edf6 100644 --- a/src/db/db/dbLayoutToNetlist.h +++ b/src/db/db/dbLayoutToNetlist.h @@ -703,6 +703,38 @@ public: */ void shapes_of_net (const db::Net &net, const db::Region &of_layer, bool recursive, db::Shapes &to, properties_id_type propid = 0) const; + /** + * @brief An enum describing the way how net information is attached to shapes as properties in "build_nets" + */ + enum NetPropertyMode + { + /** + * @brief Do no generate properties + */ + NoProperties, + + /** + * @brief Attach all net properties plus the net name (if a "netname_prop" is specified to "build_nets") + */ + AllProperties, + + /** + * @brief Attach net name only (if a "netname_prop" is specified to "build_nets") + */ + NetNameOnly, + + /** + * @brief Like NetNameOnly, but use a unique net ID (db::Net address actually) instead of name + */ + NetIDOnly, + + /** + * @brief Use the net ID (db::Net address) directly as property ID + * Caution: you need to know what you're doing if you use that mode. + */ + FakePropId + }; + /** * @brief An enum describing the way the net hierarchy is mapped */ @@ -747,15 +779,17 @@ public: * using a name like device_cell_name_prefix + device name. Otherwise the device shapes are * treated as part of the net. * + * @param net The net to build * @param target The target layout * @param target_cell The target cell * @param lmap Target layer indexes (keys) and net regions (values) * @param hier_mode See description of this method + * @param net_prop_mode How to attach properties to shapes * @param netname_prop An (optional) property name to which to attach the net name * @param cell_name_prefix Chooses recursive mode if non-null * @param device_cell_name_prefix See above */ - void build_net (const db::Net &net, db::Layout &target, db::Cell &target_cell, const std::map &lmap, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *cell_name_prefix, const char *device_cell_name_prefix) const; + void build_net (const db::Net &net, db::Layout &target, db::Cell &target_cell, const std::map &lmap, NetPropertyMode prop_mode, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *cell_name_prefix, const char *device_cell_name_prefix) const; /** * @brief Builds a full hierarchical representation of the nets @@ -788,18 +822,19 @@ public: * @param cmap The mapping of internal layout to target layout for the circuit mapping * @param target The target layout * @param lmap Target layer indexes (keys) and net regions (values) - * @param hier_mode See description of this method - * @param netname_prop An (optional) property name to which to attach the net name - * @param circuit_cell_name_prefix See method description * @param net_cell_name_prefix See method description + * @param net_prop_mode How to attach properties to shapes + * @param netname_prop The property key to use for the net name or "nil" for no netname properties + * @param hier_mode See description of this method + * @param circuit_cell_name_prefix See method description * @param device_cell_name_prefix See above */ - void build_all_nets (const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const; + void build_all_nets (const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, NetPropertyMode prop_mode, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const; /** * @brief Like build_all_nets, but with the ability to select some nets */ - void build_nets (const std::vector *nets, const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const; + void build_nets (const std::vector *nets, const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const char *net_cell_name_prefix, NetPropertyMode prop_mode, const tl::Variant &netname_prop, BuildNetHierarchyMode hier_mode, const char *circuit_cell_name_prefix, const char *device_cell_name_prefix) const; /** * @brief Finds the net by probing a specific location on the given layer @@ -984,7 +1019,7 @@ private: db::DeepLayer deep_layer_of (const ShapeCollection &coll) const; void ensure_layout () const; std::string make_new_name (const std::string &stem = std::string ()); - db::properties_id_type make_netname_propid (db::Layout &ly, const tl::Variant &netname_prop, const db::Net &net) const; + db::properties_id_type make_netname_propid (db::Layout &ly, NetPropertyMode net_prop_mode, const tl::Variant &netname_prop, const db::Net &net) const; db::CellMapping make_cell_mapping_into (db::Layout &layout, db::Cell &cell, const std::vector *nets, bool with_device_cells); void connect_impl (const db::ShapeCollection &a, const db::ShapeCollection &b); size_t connect_global_impl (const db::ShapeCollection &l, const std::string &gn); diff --git a/src/db/db/gsiDeclDbLayoutToNetlist.cc b/src/db/db/gsiDeclDbLayoutToNetlist.cc index d0f8fe202..37e26fd98 100644 --- a/src/db/db/gsiDeclDbLayoutToNetlist.cc +++ b/src/db/db/gsiDeclDbLayoutToNetlist.cc @@ -70,7 +70,7 @@ static void build_net (const db::LayoutToNetlist *l2n, const db::Net &net, db::L { std::string p = circuit_cell_name_prefix.to_string (); std::string dp = device_cell_name_prefix.to_string (); - l2n->build_net (net, target, target_cell, lmap, netname_prop, hier_mode, circuit_cell_name_prefix.is_nil () ? 0 : p.c_str (), device_cell_name_prefix.is_nil () ? 0 : dp.c_str ()); + l2n->build_net (net, target, target_cell, lmap, db::LayoutToNetlist::AllProperties, netname_prop, hier_mode, circuit_cell_name_prefix.is_nil () ? 0 : p.c_str (), device_cell_name_prefix.is_nil () ? 0 : dp.c_str ()); } static void build_all_nets (const db::LayoutToNetlist *l2n, const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const tl::Variant &net_cell_name_prefix, const tl::Variant &netname_prop, db::LayoutToNetlist::BuildNetHierarchyMode hier_mode, const tl::Variant &circuit_cell_name_prefix, const tl::Variant &device_cell_name_prefix) @@ -78,7 +78,7 @@ static void build_all_nets (const db::LayoutToNetlist *l2n, const db::CellMappin std::string cp = circuit_cell_name_prefix.to_string (); std::string np = net_cell_name_prefix.to_string (); std::string dp = device_cell_name_prefix.to_string (); - l2n->build_all_nets (cmap, target, lmap, net_cell_name_prefix.is_nil () ? 0 : np.c_str (), netname_prop, hier_mode, circuit_cell_name_prefix.is_nil () ? 0 : cp.c_str (), device_cell_name_prefix.is_nil () ? 0 : dp.c_str ()); + l2n->build_all_nets (cmap, target, lmap, net_cell_name_prefix.is_nil () ? 0 : np.c_str (), db::LayoutToNetlist::AllProperties, netname_prop, hier_mode, circuit_cell_name_prefix.is_nil () ? 0 : cp.c_str (), device_cell_name_prefix.is_nil () ? 0 : dp.c_str ()); } static void build_nets (const db::LayoutToNetlist *l2n, const std::vector &nets, const db::CellMapping &cmap, db::Layout &target, const std::map &lmap, const tl::Variant &net_cell_name_prefix, const tl::Variant &netname_prop, db::LayoutToNetlist::BuildNetHierarchyMode hier_mode, const tl::Variant &circuit_cell_name_prefix, const tl::Variant &device_cell_name_prefix) @@ -86,7 +86,7 @@ static void build_nets (const db::LayoutToNetlist *l2n, const std::vectorbuild_nets (&nets, cmap, target, lmap, net_cell_name_prefix.is_nil () ? 0 : np.c_str (), netname_prop, hier_mode, circuit_cell_name_prefix.is_nil () ? 0 : cp.c_str (), device_cell_name_prefix.is_nil () ? 0 : dp.c_str ()); + l2n->build_nets (&nets, cmap, target, lmap, net_cell_name_prefix.is_nil () ? 0 : np.c_str (), db::LayoutToNetlist::AllProperties, netname_prop, hier_mode, circuit_cell_name_prefix.is_nil () ? 0 : cp.c_str (), device_cell_name_prefix.is_nil () ? 0 : dp.c_str ()); } static std::vector l2n_layer_names (const db::LayoutToNetlist *l2n) diff --git a/src/db/unit_tests/dbHierNetsProcessorTests.cc b/src/db/unit_tests/dbHierNetsProcessorTests.cc new file mode 100644 index 000000000..2ac47f8df --- /dev/null +++ b/src/db/unit_tests/dbHierNetsProcessorTests.cc @@ -0,0 +1,138 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2023 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + + +#include "tlUnitTest.h" +#include "tlStream.h" +#include "dbLayoutToNetlist.h" +#include "dbTestSupport.h" +#include "dbReader.h" +#include "dbWriter.h" +#include "dbCommonReader.h" + + +static unsigned int define_layer (db::Layout &ly, db::LayerMap &lmap, int gds_layer, int gds_datatype = 0) +{ + unsigned int lid = ly.insert_layer (db::LayerProperties (gds_layer, gds_datatype)); + lmap.map (ly.get_properties (lid), lid); + return lid; +} + + +TEST(0_Develop) +{ + db::Layout ly; + db::LayerMap lmap; + + unsigned int poly = define_layer (ly, lmap, 7); + unsigned int cont = define_layer (ly, lmap, 14); + unsigned int metal1 = define_layer (ly, lmap, 15); + unsigned int via1 = define_layer (ly, lmap, 16); + unsigned int metal2 = define_layer (ly, lmap, 17); + unsigned int via2 = define_layer (ly, lmap, 18); + unsigned int metal3 = define_layer (ly, lmap, 19); + unsigned int via3 = define_layer (ly, lmap, 20); + unsigned int metal4 = define_layer (ly, lmap, 21); + + { + db::LoadLayoutOptions options; + options.get_options ().layer_map = lmap; + options.get_options ().create_other_layers = false; + + // @@@ std::string fn (tl::testdata ()); + // @@@ fn = tl::combine_path (fn, "algo"); + // @@@ fn = tl::combine_path (fn, "device_extract_l1.gds"); + + std::string fn ("/home/matthias/klayout/testdata/laurent_ANA_DRIVE7/ANA_DRIVE7.gds"); // @@@ + + tl::InputStream stream (fn); + db::Reader reader (stream); + reader.read (ly, options); + } + + db::Cell &tc = ly.cell (*ly.begin_top_down ()); + db::LayoutToNetlist l2n (db::RecursiveShapeIterator (ly, tc, std::set ())); + + std::unique_ptr rpoly (l2n.make_polygon_layer (poly, "poly")); + std::unique_ptr rcont (l2n.make_polygon_layer (cont, "cont")); + std::unique_ptr rmetal1 (l2n.make_polygon_layer (metal1, "metal1")); + std::unique_ptr rvia1 (l2n.make_polygon_layer (via1, "via1")); + std::unique_ptr rmetal2 (l2n.make_polygon_layer (metal2, "metal2")); + std::unique_ptr rvia2 (l2n.make_polygon_layer (via1, "via2")); + std::unique_ptr rmetal3 (l2n.make_polygon_layer (metal2, "metal3")); + std::unique_ptr rvia3 (l2n.make_polygon_layer (via1, "via3")); + std::unique_ptr rmetal4 (l2n.make_polygon_layer (metal2, "metal4")); + + // net extraction + + // Intra-layer + l2n.connect (*rpoly); + l2n.connect (*rcont); + l2n.connect (*rmetal1); + l2n.connect (*rvia1); + l2n.connect (*rmetal2); + l2n.connect (*rvia2); + l2n.connect (*rmetal3); + l2n.connect (*rvia3); + l2n.connect (*rmetal4); + // Inter-layer + l2n.connect (*rpoly, *rcont); + l2n.connect (*rcont, *rmetal1); + l2n.connect (*rmetal1, *rvia1); + l2n.connect (*rvia1, *rmetal2); + l2n.connect (*rmetal2, *rvia2); + l2n.connect (*rvia2, *rmetal3); + l2n.connect (*rmetal3, *rvia3); + l2n.connect (*rvia3, *rmetal4); + + l2n.extract_netlist (); + + // .... + + db::Layout ly2; + ly2.dbu (l2n.internal_layout ()->dbu ()); + db::Cell &top2 = ly2.cell (ly2.add_cell (ly.cell_name (tc.cell_index ()))); + + db::CellMapping cm = l2n.cell_mapping_into (ly2, top2, false /*without device cells*/); + + std::map lmap_write; + unsigned int wpoly, wcont, wmetal1, wvia1, wmetal2; + lmap_write [wpoly = ly2.insert_layer (db::LayerProperties (7, 0))] = l2n.layer_by_name ("poly"); + lmap_write [wcont = ly2.insert_layer (db::LayerProperties (14, 0))] = l2n.layer_by_name ("cont"); + lmap_write [wmetal1 = ly2.insert_layer (db::LayerProperties (15, 0))] = l2n.layer_by_name ("metal1"); + lmap_write [wvia1 = ly2.insert_layer (db::LayerProperties (16, 0))] = l2n.layer_by_name ("via1"); + lmap_write [wmetal2 = ly2.insert_layer (db::LayerProperties (17, 0))] = l2n.layer_by_name ("metal2"); + + l2n.build_all_nets (cm, ly2, lmap_write, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "SC_", 0 /*don't produce devices*/); + + { + db::SaveLayoutOptions options; + + std::string fn ("net.gds"); // @@@ + + tl::OutputStream stream (fn); + db::Writer writer (options); + writer.write (ly2, stream); + } + + +} diff --git a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc index 4e7ab190e..65484c965 100644 --- a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc @@ -74,7 +74,7 @@ TEST(1_ReaderBasic) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = l2n.layer_by_name ("via1"); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = l2n.layer_by_name ("metal2"); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -104,7 +104,7 @@ TEST(1_ReaderBasic) db::CellMapping cm = l2n.cell_mapping_into (ly2, top2, nets); - l2n.build_nets (&nets, cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); + l2n.build_nets (&nets, cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -134,7 +134,7 @@ TEST(1_ReaderBasic) db::CellMapping cm = l2n.cell_mapping_into (ly2, top2, nets); - l2n.build_nets (&nets, cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_Flatten, 0, "DEVICE_"); + l2n.build_nets (&nets, cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Flatten, 0, "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -164,7 +164,7 @@ TEST(1_ReaderBasic) db::CellMapping cm = l2n.cell_mapping_into (ly2, top2, nets); - l2n.build_nets (&nets, cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_nets (&nets, cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -195,7 +195,7 @@ TEST(1_ReaderBasic) db::CellMapping cm = l2n.cell_mapping_into (ly2, top2, nets); - l2n.build_nets (&nets, cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", 0); + l2n.build_nets (&nets, cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", 0); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -226,7 +226,7 @@ TEST(1_ReaderBasic) db::CellMapping cm = l2n.const_cell_mapping_into (ly2, top2); - l2n.build_nets (&nets, cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_nets (&nets, cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -305,7 +305,7 @@ TEST(1c_ReaderBasicShortWithProps) db::CellMapping cm = l2n.cell_mapping_into (ly2, top2); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -361,7 +361,7 @@ TEST(2_ReaderWithGlobalNets) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = l2n.layer_by_name ("via1"); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = l2n.layer_by_name ("metal2"); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -417,7 +417,7 @@ TEST(3_ReaderAbsoluteCoordinates) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = l2n.layer_by_name ("via1"); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = l2n.layer_by_name ("metal2"); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -463,7 +463,7 @@ TEST(4_ReaderCombinedDevices) std::map lmap = l2n.create_layermap (ly2, 1000); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); diff --git a/src/db/unit_tests/dbLayoutToNetlistTests.cc b/src/db/unit_tests/dbLayoutToNetlistTests.cc index d82a42e7d..1a8d0dc62 100644 --- a/src/db/unit_tests/dbLayoutToNetlistTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistTests.cc @@ -395,7 +395,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, 0, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, 0); + l2n.build_all_nets (cm, ly2, lmap, 0, db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, 0); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -421,7 +421,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, 0); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, 0); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -447,7 +447,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, 0, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", 0); + l2n.build_all_nets (cm, ly2, lmap, 0, db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", 0); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -473,7 +473,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, 0, tl::Variant (42), db::LayoutToNetlist::BNH_Flatten, 0, 0); + l2n.build_all_nets (cm, ly2, lmap, 0, db::LayoutToNetlist::AllProperties, tl::Variant (42), db::LayoutToNetlist::BNH_Flatten, 0, 0); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -499,7 +499,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, 0, tl::Variant (42), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", 0); + l2n.build_all_nets (cm, ly2, lmap, 0, db::LayoutToNetlist::AllProperties, tl::Variant (42), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", 0); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -525,7 +525,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -636,7 +636,7 @@ TEST(1_BasicExtraction) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); diff --git a/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc b/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc index 423ae0824..1fa588897 100644 --- a/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistWriterTests.cc @@ -207,7 +207,7 @@ TEST(1_WriterBasic) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_Disconnected, 0, "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); @@ -440,7 +440,7 @@ TEST(2_WriterWithGlobalNets) lmap [ly2.insert_layer (db::LayerProperties (7, 0)) ] = rvia1.get (); lmap [ly2.insert_layer (db::LayerProperties (8, 0)) ] = rmetal2.get (); - l2n.build_all_nets (cm, ly2, lmap, "NET_", tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); + l2n.build_all_nets (cm, ly2, lmap, "NET_", db::LayoutToNetlist::NoProperties, tl::Variant (), db::LayoutToNetlist::BNH_SubcircuitCells, "CIRCUIT_", "DEVICE_"); std::string au = tl::testdata (); au = tl::combine_path (au, "algo"); diff --git a/src/db/unit_tests/unit_tests.pro b/src/db/unit_tests/unit_tests.pro index 50d493b51..bc0b60cad 100644 --- a/src/db/unit_tests/unit_tests.pro +++ b/src/db/unit_tests/unit_tests.pro @@ -13,76 +13,77 @@ SOURCES = \ dbRegionCheckUtilsTests.cc \ dbUtilsTests.cc \ dbWriterTools.cc \ - dbLoadLayoutOptionsTests.cc \ - dbSaveLayoutOptionsTests.cc \ - dbHierarchyBuilderTests.cc \ - dbRecursiveShapeIteratorTests.cc \ - dbHierProcessorTests.cc \ - dbDeepRegionTests.cc \ - dbDeepShapeStoreTests.cc \ - dbHierNetworkProcessorTests.cc \ - dbNetlistTests.cc \ - dbNetlistExtractorTests.cc \ - dbNetlistDeviceExtractorTests.cc \ - dbNetlistDeviceClassesTests.cc \ - dbLayoutToNetlistTests.cc \ - dbLayoutToNetlistWriterTests.cc \ - dbLayoutToNetlistReaderTests.cc \ - dbNetlistWriterTests.cc \ - dbCellVariantsTests.cc \ - dbDeepEdgesTests.cc \ - dbDeepEdgePairsTests.cc \ - dbNetlistCompareTests.cc \ - dbNetlistReaderTests.cc \ - dbLayoutVsSchematicTests.cc \ - dbLayoutQueryTests.cc \ - dbPolygonToolsTests.cc \ - dbTechnologyTests.cc \ - dbStreamLayerTests.cc \ - dbVectorTests.cc \ - dbVariableWidthPathTests.cc \ - dbTransTests.cc \ - dbTilingProcessorTests.cc \ - dbTextsTests.cc \ - dbTextTests.cc \ - dbShapesTests.cc \ - dbShapeRepositoryTests.cc \ - dbShapeArrayTests.cc \ - dbShapeTests.cc \ - dbRegionTests.cc \ - dbPropertiesRepositoryTests.cc \ - dbPolygonTests.cc \ - dbPointTests.cc \ - dbPCellsTests.cc \ - dbPathTests.cc \ - dbObjectTests.cc \ - dbMatrixTests.cc \ - dbLibrariesTests.cc \ - dbLayoutUtilsTests.cc \ - dbLayoutDiffTests.cc \ - dbLayoutTests.cc \ - dbLayerMappingTests.cc \ - dbLayerTests.cc \ - dbExpressionTests.cc \ - dbEdgesToContoursTests.cc \ - dbEdgesTests.cc \ - dbEdgeProcessorTests.cc \ - dbEdgePairsTests.cc \ - dbEdgePairRelationsTests.cc \ - dbEdgePairTests.cc \ - dbEdgeTests.cc \ - dbEdgesUtilsTests.cc \ - dbClipTests.cc \ - dbCellMappingTests.cc \ - dbCellHullGeneratorTests.cc \ - dbCellGraphUtilsTests.cc \ - dbCellTests.cc \ - dbBoxTreeTests.cc \ - dbBoxScannerTests.cc \ - dbBoxTests.cc \ - dbArrayTests.cc \ - dbDeepTextsTests.cc \ - dbNetShapeTests.cc + dbLoadLayoutOptionsTests.cc \ + dbSaveLayoutOptionsTests.cc \ + dbHierarchyBuilderTests.cc \ + dbRecursiveShapeIteratorTests.cc \ + dbHierProcessorTests.cc \ + dbDeepRegionTests.cc \ + dbDeepShapeStoreTests.cc \ + dbHierNetworkProcessorTests.cc \ + dbNetlistTests.cc \ + dbNetlistExtractorTests.cc \ + dbNetlistDeviceExtractorTests.cc \ + dbNetlistDeviceClassesTests.cc \ + dbLayoutToNetlistTests.cc \ + dbLayoutToNetlistWriterTests.cc \ + dbLayoutToNetlistReaderTests.cc \ + dbNetlistWriterTests.cc \ + dbCellVariantsTests.cc \ + dbDeepEdgesTests.cc \ + dbDeepEdgePairsTests.cc \ + dbNetlistCompareTests.cc \ + dbNetlistReaderTests.cc \ + dbLayoutVsSchematicTests.cc \ + dbLayoutQueryTests.cc \ + dbPolygonToolsTests.cc \ + dbTechnologyTests.cc \ + dbStreamLayerTests.cc \ + dbVectorTests.cc \ + dbVariableWidthPathTests.cc \ + dbTransTests.cc \ + dbTilingProcessorTests.cc \ + dbTextsTests.cc \ + dbTextTests.cc \ + dbShapesTests.cc \ + dbShapeRepositoryTests.cc \ + dbShapeArrayTests.cc \ + dbShapeTests.cc \ + dbRegionTests.cc \ + dbPropertiesRepositoryTests.cc \ + dbPolygonTests.cc \ + dbPointTests.cc \ + dbPCellsTests.cc \ + dbPathTests.cc \ + dbObjectTests.cc \ + dbMatrixTests.cc \ + dbLibrariesTests.cc \ + dbLayoutUtilsTests.cc \ + dbLayoutDiffTests.cc \ + dbLayoutTests.cc \ + dbLayerMappingTests.cc \ + dbLayerTests.cc \ + dbExpressionTests.cc \ + dbEdgesToContoursTests.cc \ + dbEdgesTests.cc \ + dbEdgeProcessorTests.cc \ + dbEdgePairsTests.cc \ + dbEdgePairRelationsTests.cc \ + dbEdgePairTests.cc \ + dbEdgeTests.cc \ + dbEdgesUtilsTests.cc \ + dbClipTests.cc \ + dbCellMappingTests.cc \ + dbCellHullGeneratorTests.cc \ + dbCellGraphUtilsTests.cc \ + dbCellTests.cc \ + dbBoxTreeTests.cc \ + dbBoxScannerTests.cc \ + dbBoxTests.cc \ + dbArrayTests.cc \ + dbDeepTextsTests.cc \ + dbNetShapeTests.cc \ + dbHierNetsProcessorTests.cc INCLUDEPATH += $$TL_INC $$DB_INC $$GSI_INC DEPENDPATH += $$TL_INC $$DB_INC $$GSI_INC diff --git a/src/layui/layui/layNetlistBrowserPage.cc b/src/layui/layui/layNetlistBrowserPage.cc index 247dd8034..55659a919 100644 --- a/src/layui/layui/layNetlistBrowserPage.cc +++ b/src/layui/layui/layNetlistBrowserPage.cc @@ -1781,6 +1781,7 @@ NetlistBrowserPage::export_nets (const std::vector *nets) database->build_nets (nets, cm, target_layout, lm, dialog->net_prefix ().empty () ? 0 : dialog->net_prefix ().c_str (), + db::LayoutToNetlist::AllProperties, dialog->net_propname (), dialog->produce_circuit_cells () ? db::LayoutToNetlist::BNH_SubcircuitCells : db::LayoutToNetlist::BNH_Flatten, dialog->produce_circuit_cells () ? dialog->circuit_cell_prefix ().c_str () : 0,