From a4c9be553649fe77e73726083ab045699d575f38 Mon Sep 17 00:00:00 2001
From: Matthias Koefferlein <matthias@klayout.de>
Date: Mon, 27 Feb 2023 22:34:45 +0100
Subject: [PATCH] Updated test data

---
 testdata/lvs/nand2_split_gate.cir.2       |  23 +
 testdata/lvs/nand2_split_gate_early.cir.2 |  23 +
 testdata/lvs/test_22c.lvsdb.3             | 952 ++++++++++++++++++++++
 testdata/lvs/test_22d.lvsdb.3             | 952 ++++++++++++++++++++++
 4 files changed, 1950 insertions(+)
 create mode 100644 testdata/lvs/nand2_split_gate.cir.2
 create mode 100644 testdata/lvs/nand2_split_gate_early.cir.2
 create mode 100644 testdata/lvs/test_22c.lvsdb.3
 create mode 100644 testdata/lvs/test_22d.lvsdb.3

diff --git a/testdata/lvs/nand2_split_gate.cir.2 b/testdata/lvs/nand2_split_gate.cir.2
new file mode 100644
index 000000000..3d5aa4d5f
--- /dev/null
+++ b/testdata/lvs/nand2_split_gate.cir.2
@@ -0,0 +1,23 @@
+* Extracted by KLayout
+
+* cell NAND2_WITH_DIODES
+* pin B
+* pin A
+* pin OUT
+* pin VDD
+* pin VSS
+.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
+* net 1 B
+* net 2 A
+* net 4 OUT
+* net 5 VDD
+* net 6 VSS
+* device instance $1 r0 *1 1.025,4.95 PMOS
+M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
+* device instance $2 r0 *1 1.775,4.95 PMOS
+M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
+* device instance $3 r0 *1 1.025,0.65 NMOS
+M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
+* device instance $4 r0 *1 1.775,0.65 NMOS
+M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
+.ENDS NAND2_WITH_DIODES
diff --git a/testdata/lvs/nand2_split_gate_early.cir.2 b/testdata/lvs/nand2_split_gate_early.cir.2
new file mode 100644
index 000000000..3d5aa4d5f
--- /dev/null
+++ b/testdata/lvs/nand2_split_gate_early.cir.2
@@ -0,0 +1,23 @@
+* Extracted by KLayout
+
+* cell NAND2_WITH_DIODES
+* pin B
+* pin A
+* pin OUT
+* pin VDD
+* pin VSS
+.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
+* net 1 B
+* net 2 A
+* net 4 OUT
+* net 5 VDD
+* net 6 VSS
+* device instance $1 r0 *1 1.025,4.95 PMOS
+M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
+* device instance $2 r0 *1 1.775,4.95 PMOS
+M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
+* device instance $3 r0 *1 1.025,0.65 NMOS
+M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
+* device instance $4 r0 *1 1.775,0.65 NMOS
+M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
+.ENDS NAND2_WITH_DIODES
diff --git a/testdata/lvs/test_22c.lvsdb.3 b/testdata/lvs/test_22c.lvsdb.3
new file mode 100644
index 000000000..66213ecfc
--- /dev/null
+++ b/testdata/lvs/test_22c.lvsdb.3
@@ -0,0 +1,952 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(SP6TArray_2X4)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l5 '64/20')
+ layer(l3)
+ layer(l8)
+ layer(l7 '66/20')
+ layer(l10)
+ layer(l9 '67/20')
+ layer(l12 '68/16')
+ layer(l11 '68/20')
+ layer(l14 '69/16')
+ layer(l13 '69/20')
+ layer(l16)
+ layer(l15)
+ layer(l18)
+ layer(l17)
+ layer(l20)
+ layer(l19)
+ layer(l21 '66/44')
+ layer(l23 '67/44')
+ layer(l24 '68/44')
+ layer(l25)
+ layer(l26)
+ layer(l27)
+ layer(l22)
+ layer(l2)
+ layer(l4)
+ layer(l6)
+ layer(l1)
+
+ # Mask layer connectivity
+ connect(l5 l5 l4)
+ connect(l3 l3 l2)
+ connect(l8 l8 l7)
+ connect(l7 l8 l7)
+ connect(l10 l10 l9)
+ connect(l9 l10 l9 l21 l23)
+ connect(l12 l12 l11)
+ connect(l11 l12 l11 l23 l24)
+ connect(l14 l14 l13)
+ connect(l13 l14 l13 l24 l25)
+ connect(l16 l16 l15)
+ connect(l15 l16 l15 l25 l26)
+ connect(l18 l18 l17)
+ connect(l17 l18 l17 l26 l27)
+ connect(l20 l20 l19)
+ connect(l19 l20 l19 l27)
+ connect(l21 l9 l21 l22 l2)
+ connect(l23 l9 l11 l23)
+ connect(l24 l11 l13 l24)
+ connect(l25 l13 l15 l25)
+ connect(l26 l15 l17 l26)
+ connect(l27 l17 l19 l27)
+ connect(l22 l21 l22)
+ connect(l2 l3 l21 l2 l4 l6)
+ connect(l4 l5 l2 l4)
+ connect(l6 l2 l6)
+ connect(l1 l1)
+
+ # Global nets and connectivity
+ global(l6 vss)
+ global(l1 vss)
+
+ # Device class section
+ class(active_res RES)
+ class(poly_res RES)
+ class(sky130_fd_pr__diode_pw2nd_05v5 DIODE)
+ class(sky130_fd_pr__diode_pd2nw_05v5 DIODE)
+ class(sky130_fd_pr__nfet_01v8__model MOS4)
+ class(sky130_fd_pr__nfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__nfet_g5v0d10v5__model MOS4)
+ class(sky130_fd_pr__pfet_01v8__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_hvt__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__pfet_g5v0d10v5__model MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$sky130_fd_pr__nfet_01v8__model sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$2 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$1 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCell
+
+  # Circuit boundary
+  rect((-385 -485) (2950 3565))
+
+  # Nets with their geometries
+  net(1
+   rect(l7 (1890 500) (150 2010))
+   rect(l7 (-1100 -1320) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+  )
+  net(2
+   rect(l7 (1240 1550) (330 270))
+   rect(l7 (-1280 -150) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+  )
+  net(3
+   polygon(l9 (525 760) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-5 -1010) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (950 -960) (150 2010))
+   rect(l22 (-1100 -1320) (950 150))
+   polygon(l2 (-1495 -1050) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+  )
+  net(4
+   polygon(l9 (1485 760) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-335 -650) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (-1280 -150) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   polygon(l2 (1075 -2220) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+  )
+  net(5 name(vdd)
+   rect(l5 (-385 1780) (2950 1300))
+   rect(l9 (-2650 -1075) (170 685))
+   rect(l9 (-250 0) (2510 170))
+   rect(l9 (-250 -855) (170 685))
+   rect(l11 (-2395 -75) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l23 (-2350 435) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-2460 -200) (2590 250))
+   rect(l2 (-2510 -940) (265 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l4 (-2510 270) (2590 250))
+  )
+  net(6 name(wl)
+   rect(l9 (1005 140) (170 500))
+   polygon(l11 (-200 -230) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   rect(l14 (-1205 320) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+   rect(l21 (-1175 -770) (170 170))
+   rect(l23 (-170 80) (170 170))
+   rect(l24 (-160 145) (150 150))
+   polygon(l22 (-900 -795) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(7 name(bl)
+   polygon(l9 (520 -165) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l12 (-260 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-140 -2860) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l2 (-235 -210) (420 265))
+  )
+  net(8 name(bl_n)
+   polygon(l9 (1490 -165) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l12 (-140 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-260 -2860) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l2 (-355 -210) (420 265))
+  )
+  net(9
+   polygon(l7 (265 140) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(10 name(vss)
+   rect(l9 (-85 -165) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l11 (-2395 -1165) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -1010) (170 170))
+   rect(l23 (-2350 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-215 555) (265 420))
+   rect(l2 (-2430 -1410) (250 720))
+   rect(l2 (-250 270) (265 420))
+   rect(l2 (1915 -1410) (250 720))
+   rect(l6 (-250 -720) (250 720))
+   rect(l6 (-2430 -720) (250 720))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(vdd))
+  pin(6 name(wl))
+  pin(7 name(bl))
+  pin(8 name(bl_n))
+  pin(10 name(vss))
+
+  # Devices and their connections
+  device(1 D$sky130_fd_pr__nfet_01v8__model
+   location(1575 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 4)
+   terminal(B 10)
+  )
+  device(2 D$sky130_fd_pr__nfet_01v8__model$1
+   location(1965 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(3 D$sky130_fd_pr__nfet_01v8__model$2
+   location(605 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 10)
+  )
+  device(4 D$sky130_fd_pr__nfet_01v8__model$3
+   location(215 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 3)
+   terminal(G 4)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(5 D$sky130_fd_pr__pfet_01v8__model
+   location(1965 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(6 D$sky130_fd_pr__pfet_01v8__model$1
+   location(215 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 5)
+   terminal(G 4)
+   terminal(D 3)
+   terminal(B 5)
+  )
+
+ )
+ circuit(SP6TArray_2X1
+
+  # Circuit boundary
+  rect((-385 -305) (2950 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name(vdd)
+   rect(l14 (-160 -130) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l14 (-1250 5420) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -5680) (2500 260))
+   rect(l13 (-2500 5290) (2500 260))
+  )
+  net(4 name('wl[0]')
+   rect(l14 (0 1785) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(5 name('wl[1]')
+   rect(l14 (0 3505) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(6 name(vss)
+   rect(l14 (-160 2645) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name(vdd))
+  pin(4 name('wl[0]'))
+  pin(5 name('wl[1]'))
+  pin(6 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCell location(0 2775)
+   pin(0 3)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+  circuit(2 SP6TCell mirror location(0 2775)
+   pin(0 3)
+   pin(1 4)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TArray_2X2
+
+  # Circuit boundary
+  rect((-385 -305) (5130 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name(vdd)
+   rect(l14 (-160 5420) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l14 (-2340 -5680) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 5420) (4680 260))
+   rect(l13 (-4680 -5810) (4680 260))
+  )
+  net(6 name('wl[0]')
+   rect(l14 (0 1785) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(7 name('wl[1]')
+   rect(l14 (0 3505) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(8 name(vss)
+   rect(l14 (-160 2645) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 -130) (4680 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name('bl[1]'))
+  pin(4 name('bl_n[1]'))
+  pin(5 name(vdd))
+  pin(6 name('wl[0]'))
+  pin(7 name('wl[1]'))
+  pin(8 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X1 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+  circuit(2 SP6TArray_2X1 location(2180 0)
+   pin(0 3)
+   pin(1 4)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TArray_2X4
+
+  # Circuit boundary
+  rect((-385 -305) (9490 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name('bl[2]')
+   rect(l12 (4790 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(6 name('bl_n[2]')
+   rect(l12 (5880 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(7 name('bl[3]')
+   rect(l12 (6970 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(8 name('bl_n[3]')
+   rect(l12 (8060 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(9 name(vdd)
+   rect(l14 (-160 -130) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l14 (-4520 5420) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -5680) (9040 260))
+   rect(l13 (-9040 5290) (9040 260))
+  )
+  net(10 name('wl[0]')
+   rect(l14 (0 1785) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(11 name('wl[1]')
+   rect(l14 (0 3505) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(12 name(vss)
+   rect(l14 (-160 2645) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -130) (9040 260))
+  )
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X2 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+  circuit(2 SP6TArray_2X2 location(4360 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 8)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(SKY130_FD_PR__PFET_01V8__MODEL MOS4)
+ class(SKY130_FD_PR__NFET_01V8__MODEL MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCELL
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(VSS))
+  net(3 name(WL))
+  net(4 name(BL))
+  net(5 name(BL_N))
+  net(6 name(BIT_N))
+  net(7 name(BIT))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(VSS))
+  pin(3 name(WL))
+  pin(4 name(BL))
+  pin(5 name(BL_N))
+
+  # Devices and their connections
+  device(1 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(2 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(3 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(4 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 2)
+  )
+  device(5 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 3)
+   terminal(D 4)
+   terminal(B 2)
+  )
+  device(6 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 2)
+  )
+
+ )
+ circuit(SP6TARRAY_2X1
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCELL name(INST0X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 3)
+   pin(3 5)
+   pin(4 6)
+  )
+  circuit(2 SP6TCELL name(INST1X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 4)
+   pin(3 5)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TARRAY_2X2
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X1 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+  )
+  circuit(2 SP6TARRAY_2X1 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TARRAY_2X4
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+  net(9 name('BL[2]'))
+  net(10 name('BL_N[2]'))
+  net(11 name('BL[3]'))
+  net(12 name('BL_N[3]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+  pin(9 name('BL[2]'))
+  pin(10 name('BL_N[2]'))
+  pin(11 name('BL[3]'))
+  pin(12 name('BL_N[3]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X2 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+   pin(6 7)
+   pin(7 8)
+  )
+  circuit(2 SP6TARRAY_2X2 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(SP6TArray_2X1 SP6TARRAY_2X1 match
+  xref(
+   net(1 5 match)
+   net(2 6 match)
+   net(3 2 match)
+   net(6 1 match)
+   net(4 3 warning)
+   net(5 4 warning)
+   pin(0 4 match)
+   pin(1 5 match)
+   pin(2 1 match)
+   pin(5 0 match)
+   pin(3 2 match)
+   pin(4 3 match)
+   circuit(2 1 match)
+   circuit(1 2 match)
+  )
+ )
+ circuit(SP6TArray_2X2 SP6TARRAY_2X2 match
+  xref(
+   net(1 5 match)
+   net(3 7 match)
+   net(2 6 warning)
+   net(4 8 warning)
+   net(5 2 match)
+   net(8 1 match)
+   net(6 3 match)
+   net(7 4 match)
+   pin(0 4 match)
+   pin(2 6 match)
+   pin(1 5 match)
+   pin(3 7 match)
+   pin(4 1 match)
+   pin(7 0 match)
+   pin(5 2 match)
+   pin(6 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TArray_2X4 SP6TARRAY_2X4 match
+  xref(
+   net(1 5 match)
+   net(3 7 warning)
+   net(5 9 match)
+   net(7 11 warning)
+   net(2 6 match)
+   net(4 8 match)
+   net(6 10 match)
+   net(8 12 match)
+   net(9 2 match)
+   net(12 1 match)
+   net(10 3 match)
+   net(11 4 match)
+   pin(() 4 match)
+   pin(() 6 match)
+   pin(() 8 match)
+   pin(() 10 match)
+   pin(() 5 match)
+   pin(() 7 match)
+   pin(() 9 match)
+   pin(() 11 match)
+   pin(() 1 match)
+   pin(() 0 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TCell SP6TCELL match
+  xref(
+   net(3 7 warning)
+   net(4 6 warning)
+   net(7 4 match)
+   net(8 5 match)
+   net(5 1 match)
+   net(10 2 match)
+   net(6 3 match)
+   pin(2 3 match)
+   pin(3 4 match)
+   pin(0 0 match)
+   pin(4 1 match)
+   pin(1 2 match)
+   device(4 3 match)
+   device(2 4 match)
+   device(3 5 match)
+   device(1 6 match)
+   device(6 1 match)
+   device(5 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/test_22d.lvsdb.3 b/testdata/lvs/test_22d.lvsdb.3
new file mode 100644
index 000000000..a0c293345
--- /dev/null
+++ b/testdata/lvs/test_22d.lvsdb.3
@@ -0,0 +1,952 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(SP6TArray_2X4)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l5 '64/20')
+ layer(l3)
+ layer(l8)
+ layer(l7 '66/20')
+ layer(l10)
+ layer(l9 '67/20')
+ layer(l12 '68/16')
+ layer(l11 '68/20')
+ layer(l14 '69/16')
+ layer(l13 '69/20')
+ layer(l16)
+ layer(l15)
+ layer(l18)
+ layer(l17)
+ layer(l20)
+ layer(l19)
+ layer(l21 '66/44')
+ layer(l23 '67/44')
+ layer(l24 '68/44')
+ layer(l25)
+ layer(l26)
+ layer(l27)
+ layer(l22)
+ layer(l2)
+ layer(l4)
+ layer(l6)
+ layer(l1)
+
+ # Mask layer connectivity
+ connect(l5 l5 l4)
+ connect(l3 l3 l2)
+ connect(l8 l8 l7)
+ connect(l7 l8 l7)
+ connect(l10 l10 l9)
+ connect(l9 l10 l9 l21 l23)
+ connect(l12 l12 l11)
+ connect(l11 l12 l11 l23 l24)
+ connect(l14 l14 l13)
+ connect(l13 l14 l13 l24 l25)
+ connect(l16 l16 l15)
+ connect(l15 l16 l15 l25 l26)
+ connect(l18 l18 l17)
+ connect(l17 l18 l17 l26 l27)
+ connect(l20 l20 l19)
+ connect(l19 l20 l19 l27)
+ connect(l21 l9 l21 l22 l2)
+ connect(l23 l9 l11 l23)
+ connect(l24 l11 l13 l24)
+ connect(l25 l13 l15 l25)
+ connect(l26 l15 l17 l26)
+ connect(l27 l17 l19 l27)
+ connect(l22 l21 l22)
+ connect(l2 l3 l21 l2 l4 l6)
+ connect(l4 l5 l2 l4)
+ connect(l6 l2 l6)
+ connect(l1 l1)
+
+ # Global nets and connectivity
+ global(l6 vss)
+ global(l1 vss)
+
+ # Device class section
+ class(active_res RES)
+ class(poly_res RES)
+ class(sky130_fd_pr__diode_pw2nd_05v5 DIODE)
+ class(sky130_fd_pr__diode_pd2nw_05v5 DIODE)
+ class(sky130_fd_pr__nfet_01v8__model MOS4)
+ class(sky130_fd_pr__nfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__nfet_g5v0d10v5__model MOS4)
+ class(sky130_fd_pr__pfet_01v8__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_hvt__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__pfet_g5v0d10v5__model MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$sky130_fd_pr__nfet_01v8__model sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$2 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$1 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCell
+
+  # Circuit boundary
+  rect((-385 -485) (2950 3565))
+
+  # Nets with their geometries
+  net(1
+   rect(l7 (1890 500) (150 2010))
+   rect(l7 (-1100 -1320) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+  )
+  net(2
+   rect(l7 (1240 1550) (330 270))
+   rect(l7 (-1280 -150) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+  )
+  net(3
+   polygon(l9 (525 760) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-5 -1010) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (950 -960) (150 2010))
+   rect(l22 (-1100 -1320) (950 150))
+   polygon(l2 (-1495 -1050) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+  )
+  net(4
+   polygon(l9 (1485 760) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-335 -650) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (-1280 -150) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   polygon(l2 (1075 -2220) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+  )
+  net(5 name(vdd)
+   rect(l5 (-385 1780) (2950 1300))
+   rect(l9 (-2650 -1075) (170 685))
+   rect(l9 (-250 0) (2510 170))
+   rect(l9 (-250 -855) (170 685))
+   rect(l11 (-2395 -75) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l23 (-2350 435) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-2460 -200) (2590 250))
+   rect(l2 (-2510 -940) (265 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l4 (-2510 270) (2590 250))
+  )
+  net(6 name(wl)
+   rect(l9 (1005 140) (170 500))
+   polygon(l11 (-200 -230) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   rect(l14 (-1205 320) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+   rect(l21 (-1175 -770) (170 170))
+   rect(l23 (-170 80) (170 170))
+   rect(l24 (-160 145) (150 150))
+   polygon(l22 (-900 -795) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(7 name(bl)
+   polygon(l9 (520 -165) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l12 (-260 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-140 -2860) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l2 (-235 -210) (420 265))
+  )
+  net(8 name(bl_n)
+   polygon(l9 (1490 -165) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l12 (-140 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-260 -2860) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l2 (-355 -210) (420 265))
+  )
+  net(9
+   polygon(l7 (265 140) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(10 name(vss)
+   rect(l9 (-85 -165) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l11 (-2395 -1165) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -1010) (170 170))
+   rect(l23 (-2350 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-215 555) (265 420))
+   rect(l2 (-2430 -1410) (250 720))
+   rect(l2 (-250 270) (265 420))
+   rect(l2 (1915 -1410) (250 720))
+   rect(l6 (-250 -720) (250 720))
+   rect(l6 (-2430 -720) (250 720))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(vdd))
+  pin(6 name(wl))
+  pin(7 name(bl))
+  pin(8 name(bl_n))
+  pin(10 name(vss))
+
+  # Devices and their connections
+  device(1 D$sky130_fd_pr__nfet_01v8__model
+   location(1575 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 4)
+   terminal(B 10)
+  )
+  device(2 D$sky130_fd_pr__nfet_01v8__model$1
+   location(1965 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(3 D$sky130_fd_pr__nfet_01v8__model$2
+   location(605 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 10)
+  )
+  device(4 D$sky130_fd_pr__nfet_01v8__model$3
+   location(215 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 3)
+   terminal(G 4)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(5 D$sky130_fd_pr__pfet_01v8__model
+   location(1965 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(6 D$sky130_fd_pr__pfet_01v8__model$1
+   location(215 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 5)
+   terminal(G 4)
+   terminal(D 3)
+   terminal(B 5)
+  )
+
+ )
+ circuit(SP6TArray_2X1
+
+  # Circuit boundary
+  rect((-385 -305) (2950 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name(vdd)
+   rect(l14 (-160 -130) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l14 (-1250 5420) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -5680) (2500 260))
+   rect(l13 (-2500 5290) (2500 260))
+  )
+  net(4 name('wl[0]')
+   rect(l14 (0 1785) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(5 name('wl[1]')
+   rect(l14 (0 3505) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(6 name(vss)
+   rect(l14 (-160 2645) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name(vdd))
+  pin(4 name('wl[0]'))
+  pin(5 name('wl[1]'))
+  pin(6 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCell location(0 2775)
+   pin(0 3)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+  circuit(2 SP6TCell mirror location(0 2775)
+   pin(0 3)
+   pin(1 4)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TArray_2X2
+
+  # Circuit boundary
+  rect((-385 -305) (5130 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name(vdd)
+   rect(l14 (-160 5420) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l14 (-2340 -5680) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 5420) (4680 260))
+   rect(l13 (-4680 -5810) (4680 260))
+  )
+  net(6 name('wl[0]')
+   rect(l14 (0 1785) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(7 name('wl[1]')
+   rect(l14 (0 3505) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(8 name(vss)
+   rect(l14 (-160 2645) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 -130) (4680 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name('bl[1]'))
+  pin(4 name('bl_n[1]'))
+  pin(5 name(vdd))
+  pin(6 name('wl[0]'))
+  pin(7 name('wl[1]'))
+  pin(8 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X1 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+  circuit(2 SP6TArray_2X1 location(2180 0)
+   pin(0 3)
+   pin(1 4)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TArray_2X4
+
+  # Circuit boundary
+  rect((-385 -305) (9490 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name('bl[2]')
+   rect(l12 (4790 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(6 name('bl_n[2]')
+   rect(l12 (5880 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(7 name('bl[3]')
+   rect(l12 (6970 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(8 name('bl_n[3]')
+   rect(l12 (8060 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(9 name(vdd)
+   rect(l14 (-160 -130) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l14 (-4520 5420) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -5680) (9040 260))
+   rect(l13 (-9040 5290) (9040 260))
+  )
+  net(10 name('wl[0]')
+   rect(l14 (0 1785) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(11 name('wl[1]')
+   rect(l14 (0 3505) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(12 name(vss)
+   rect(l14 (-160 2645) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -130) (9040 260))
+  )
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X2 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+  circuit(2 SP6TArray_2X2 location(4360 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 8)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(SKY130_FD_PR__PFET_01V8__MODEL MOS4)
+ class(SKY130_FD_PR__NFET_01V8__MODEL MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCELL
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(VSS))
+  net(3 name(WL))
+  net(4 name(BL))
+  net(5 name(BL_N))
+  net(6 name(BIT_N))
+  net(7 name(BIT))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(VSS))
+  pin(3 name(WL))
+  pin(4 name(BL))
+  pin(5 name(BL_N))
+
+  # Devices and their connections
+  device(1 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(2 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(3 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(4 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 2)
+  )
+  device(5 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 3)
+   terminal(D 4)
+   terminal(B 2)
+  )
+  device(6 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 2)
+  )
+
+ )
+ circuit(SP6TARRAY_2X1
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCELL name(INST0X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 3)
+   pin(3 5)
+   pin(4 6)
+  )
+  circuit(2 SP6TCELL name(INST1X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 4)
+   pin(3 5)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TARRAY_2X2
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X1 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+  )
+  circuit(2 SP6TARRAY_2X1 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TARRAY_2X4
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+  net(9 name('BL[2]'))
+  net(10 name('BL_N[2]'))
+  net(11 name('BL[3]'))
+  net(12 name('BL_N[3]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+  pin(9 name('BL[2]'))
+  pin(10 name('BL_N[2]'))
+  pin(11 name('BL[3]'))
+  pin(12 name('BL_N[3]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X2 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+   pin(6 7)
+   pin(7 8)
+  )
+  circuit(2 SP6TARRAY_2X2 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(SP6TArray_2X1 SP6TARRAY_2X1 match
+  xref(
+   net(1 5 match)
+   net(2 6 match)
+   net(3 2 match)
+   net(6 1 match)
+   net(4 3 match)
+   net(5 4 match)
+   pin(0 4 match)
+   pin(1 5 match)
+   pin(2 1 match)
+   pin(5 0 match)
+   pin(3 2 match)
+   pin(4 3 match)
+   circuit(2 1 match)
+   circuit(1 2 match)
+  )
+ )
+ circuit(SP6TArray_2X2 SP6TARRAY_2X2 match
+  xref(
+   net(1 5 match)
+   net(3 7 match)
+   net(2 6 match)
+   net(4 8 match)
+   net(5 2 match)
+   net(8 1 match)
+   net(6 3 match)
+   net(7 4 match)
+   pin(0 4 match)
+   pin(2 6 match)
+   pin(1 5 match)
+   pin(3 7 match)
+   pin(4 1 match)
+   pin(7 0 match)
+   pin(5 2 match)
+   pin(6 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TArray_2X4 SP6TARRAY_2X4 match
+  xref(
+   net(1 5 match)
+   net(3 7 match)
+   net(5 9 match)
+   net(7 11 match)
+   net(2 6 match)
+   net(4 8 match)
+   net(6 10 match)
+   net(8 12 match)
+   net(9 2 match)
+   net(12 1 match)
+   net(10 3 match)
+   net(11 4 match)
+   pin(() 4 match)
+   pin(() 6 match)
+   pin(() 8 match)
+   pin(() 10 match)
+   pin(() 5 match)
+   pin(() 7 match)
+   pin(() 9 match)
+   pin(() 11 match)
+   pin(() 1 match)
+   pin(() 0 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TCell SP6TCELL match
+  xref(
+   net(3 7 match)
+   net(4 6 match)
+   net(7 4 match)
+   net(8 5 match)
+   net(5 1 match)
+   net(10 2 match)
+   net(6 3 match)
+   pin(2 3 match)
+   pin(3 4 match)
+   pin(0 0 match)
+   pin(4 1 match)
+   pin(1 2 match)
+   device(4 3 match)
+   device(2 4 match)
+   device(3 5 match)
+   device(1 6 match)
+   device(6 1 match)
+   device(5 2 match)
+  )
+ )
+)