diff --git a/scripts/extract_doc.rb b/scripts/extract_doc.rb index 9e01f759c..54e51bfb1 100755 --- a/scripts/extract_doc.rb +++ b/scripts/extract_doc.rb @@ -2,9 +2,10 @@ $script_call = $0 + " " + ARGV.join(" ") -$indir="src/drc/drc/built-in-macros" +$indirs = [ "src/drc/drc/built-in-macros", "src/lvs/lvs/built-in-macros" ] + $loc = "about" -$outfiles="src/lay/lay/doc" +$outfiles = "src/lay/lay/doc" def create_ref(mod, s) if s =~ /(.*)::(.*)#(.*)/ @@ -262,53 +263,57 @@ collectors = { "LVS" => Collector::new("lvs", "LVS Reference") } -Dir.entries($indir).each do |p| +$indirs.each do |indir| - if p !~ /\.rb$/ - next - end + Dir.entries(indir).each do |p| - infile = File.join($indir, p) - puts "Extracting doc from #{infile} .." + if p !~ /\.rb$/ + next + end - File.open(infile, "r") do |file| + infile = File.join(indir, p) + puts "Extracting doc from #{infile} .." - block = [] - collector = nil - line = 0 + File.open(infile, "r") do |file| - file.each_line do |l| + block = [] + collector = nil + line = 0 - line += 1 + file.each_line do |l| - begin + line += 1 - l = unescape(l) + begin - if ! collector - collectors.each do |k,c| - if l =~ /^\s*#\s*%#{k}%/ - collector = c - l = nil - block = [] - break + l = unescape(l) + + if ! collector + collectors.each do |k,c| + if l =~ /^\s*#\s*%#{k}%/ + collector = c + l = nil + block = [] + break + end end end - end - if l - if l =~ /^\s*#\s*(.*)\s*$/ - collector && block.push($1) - elsif l =~ /^\s*$/ - collector && collector.add_block(block) - collector = nil + if l + if l =~ /^\s*#\s*(.*)\s*$/ + collector && block.push($1) + elsif l =~ /^\s*$/ + collector && collector.add_block(block) + collector = nil + end end + + rescue => ex + puts "ERROR in line #{line}:\n" + ex.to_s + puts ex.backtrace # @@@ + exit 1 end - rescue => ex - puts "ERROR in line #{line}:\n" + ex.to_s - puts ex.backtrace # @@@ - exit 1 end end diff --git a/scripts/make_drc_doc.sh b/scripts/make_drc_lvs_doc.sh similarity index 100% rename from scripts/make_drc_doc.sh rename to scripts/make_drc_lvs_doc.sh diff --git a/src/db/db/dbCircuit.cc b/src/db/db/dbCircuit.cc index dd3c6dc03..f608a9f77 100644 --- a/src/db/db/dbCircuit.cc +++ b/src/db/db/dbCircuit.cc @@ -88,9 +88,7 @@ Circuit::~Circuit () // the default destructor will make the nets access "this" to unregister the // objects - hence we have to do this explicitly. - m_nets.clear (); - m_subcircuits.clear (); - m_devices.clear (); + clear (); } Circuit &Circuit::operator= (const Circuit &other) @@ -376,14 +374,22 @@ void Circuit::flatten_subcircuit (SubCircuit *subcircuit) db::Net *outside_net = 0; if (n->pin_count () > 0) { + size_t pin_id = n->begin_pins ()->pin_id (); outside_net = subcircuit->net_for_pin (pin_id); + } else { + outside_net = new db::Net (); if (! n->name ().empty ()) { outside_net->set_name (subcircuit->expanded_name () + "." + n->name ()); } add_net (outside_net); + + if (netlist ()->callbacks ()) { + outside_net->set_cluster_id (netlist ()->callbacks ()->link_net_to_parent_circuit (n.operator-> (), this, subcircuit->trans ())); + } + } net2net.insert (std::make_pair (n.operator-> (), outside_net)); diff --git a/src/db/db/dbDeviceClass.cc b/src/db/db/dbDeviceClass.cc index 322885071..7ff6619f3 100644 --- a/src/db/db/dbDeviceClass.cc +++ b/src/db/db/dbDeviceClass.cc @@ -97,6 +97,41 @@ EqualDeviceParameters &EqualDeviceParameters::operator+= (const EqualDeviceParam return *this; } +// -------------------------------------------------------------------------------- +// AllDeviceParametersAreEqual class implementation + +AllDeviceParametersAreEqual::AllDeviceParametersAreEqual (double relative) + : m_relative (relative) +{ + // .. nothing yet .. +} + +bool AllDeviceParametersAreEqual::less (const db::Device &a, const db::Device &b) const +{ + const std::vector ¶meters = a.device_class ()->parameter_definitions (); + for (std::vector::const_iterator c = parameters.begin (); c != parameters.end (); ++c) { + int cmp = compare_parameters (a.parameter_value (c->id ()), b.parameter_value (c->id ()), 0.0, m_relative); + if (cmp != 0) { + return cmp < 0; + } + } + + return false; +} + +bool AllDeviceParametersAreEqual::equal (const db::Device &a, const db::Device &b) const +{ + const std::vector ¶meters = a.device_class ()->parameter_definitions (); + for (std::vector::const_iterator c = parameters.begin (); c != parameters.end (); ++c) { + int cmp = compare_parameters (a.parameter_value (c->id ()), b.parameter_value (c->id ()), 0.0, m_relative); + if (cmp != 0) { + return false; + } + } + + return true; +} + // -------------------------------------------------------------------------------- // DeviceClass class implementation diff --git a/src/db/db/dbDeviceClass.h b/src/db/db/dbDeviceClass.h index bb433ea92..62530e712 100644 --- a/src/db/db/dbDeviceClass.h +++ b/src/db/db/dbDeviceClass.h @@ -286,6 +286,22 @@ private: std::vector > > m_compare_set; }; +/** + * @brief A parameter compare delegate that compares all parameters in a relative fashion + */ +class DB_PUBLIC AllDeviceParametersAreEqual + : public DeviceParameterCompareDelegate +{ +public: + AllDeviceParametersAreEqual (double relative); + + virtual bool less (const db::Device &a, const db::Device &b) const; + virtual bool equal (const db::Device &a, const db::Device &b) const; + +private: + double m_relative; +}; + /** * @brief A device class * diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 2005b010c..f2e88a520 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -41,6 +41,25 @@ namespace db { +// ------------------------------------------------------------------------------ + +template void insert_transformed (db::Layout &layout, Container &shapes, const Shape &s, const Trans &t); + +template void insert_transformed (db::Layout &layout, Container &shapes, const db::PolygonRef &s, const Trans &t) +{ + db::Polygon poly = s.obj (); + poly.transform (s.trans ()); + if (! t.is_unity ()) { + poly.transform (t); + } + shapes.insert (db::PolygonRef (poly, layout.shape_repository ())); +} + +template void insert_transformed (db::Layout & /*layout*/, Container &shapes, const db::Edge &s, const Trans &t) +{ + shapes.insert (s.transformed (t)); +} + // ------------------------------------------------------------------------------ // Connectivity implementation @@ -993,7 +1012,6 @@ connected_clusters::join_cluster_with (typename local_cluster::id_type id, return; } - // join the shape clusters local_clusters::join_cluster_with (id, with_id); // handle the connections by translating @@ -2115,23 +2133,6 @@ hier_clusters::clusters_per_cell (db::cell_index_type cell_index) return c->second; } -template void insert_transformed (db::Layout &layout, db::Shapes &shapes, const Shape &s, const Trans &t); - -template void insert_transformed (db::Layout &layout, db::Shapes &shapes, const db::PolygonRef &s, const Trans &t) -{ - db::Polygon poly = s.obj (); - poly.transform (s.trans ()); - if (! t.is_unity ()) { - poly.transform (t); - } - shapes.insert (db::PolygonRef (poly, layout.shape_repository ())); -} - -template void insert_transformed (db::Layout & /*layout*/, db::Shapes &shapes, const db::Edge &s, const Trans &t) -{ - shapes.insert (s.transformed (t)); -} - template void hier_clusters::return_to_hierarchy (db::Layout &layout, const std::map &lm) const diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 112648e9c..03d2df07c 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -522,6 +522,14 @@ public: return --m_next_dummy_id; } + /** + * @brief Gets a value indicating whether the given ID is a dummy ID + */ + bool is_dummy (typename local_cluster::id_type id) const + { + return id > m_clusters.size (); + } + private: void ensure_sorted (); @@ -600,12 +608,20 @@ public: return m_inst_prop_id; } + /** + * @brief Transform with the given transformation + */ + void transform (const db::ICplxTrans &tr) + { + m_inst_trans = tr * m_inst_trans; + } + /** * @brief Equality */ bool operator== (const ClusterInstElement &other) const { - return m_inst_cell_index == other.m_inst_cell_index && m_inst_trans == other.m_inst_trans && m_inst_prop_id == other.m_inst_prop_id; + return m_inst_cell_index == other.m_inst_cell_index && m_inst_trans.equal (other.m_inst_trans) && m_inst_prop_id == other.m_inst_prop_id; } /** @@ -624,8 +640,8 @@ public: if (m_inst_cell_index != other.m_inst_cell_index) { return m_inst_cell_index < other.m_inst_cell_index; } - if (m_inst_trans != other.m_inst_trans) { - return m_inst_trans < other.m_inst_trans; + if (! m_inst_trans.equal (other.m_inst_trans)) { + return m_inst_trans.less (other.m_inst_trans); } return m_inst_prop_id < other.m_inst_prop_id; } @@ -803,7 +819,7 @@ public: * The "with_id" cluster is removed. All connections of "with_id" are transferred to the * first one. All shapes of "with_id" are transferred to "id". */ - void join_cluster_with (typename local_cluster::id_type id, typename local_cluster::id_type with_id); + void join_cluster_with(typename local_cluster::id_type id, typename local_cluster::id_type with_id); /** * @brief An iterator delivering all clusters (even the connectors) diff --git a/src/db/db/dbLayoutToNetlist.cc b/src/db/db/dbLayoutToNetlist.cc index 4e339c96e..9138a3e4f 100644 --- a/src/db/db/dbLayoutToNetlist.cc +++ b/src/db/db/dbLayoutToNetlist.cc @@ -38,7 +38,7 @@ namespace db // the iterator provides the hierarchical selection (enabling/disabling cells etc.) LayoutToNetlist::LayoutToNetlist (const db::RecursiveShapeIterator &iter) - : m_iter (iter), m_layout_index (0), m_netlist_extracted (false), m_is_flat (false) + : m_iter (iter), m_layout_index (0), m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0) { // check the iterator if (iter.has_complex_region () || iter.region () != db::Box::world ()) { @@ -58,7 +58,7 @@ LayoutToNetlist::LayoutToNetlist (const db::RecursiveShapeIterator &iter) } LayoutToNetlist::LayoutToNetlist (db::DeepShapeStore *dss, unsigned int layout_index) - : mp_dss (dss), m_layout_index (layout_index), m_netlist_extracted (false), m_is_flat (false) + : mp_dss (dss), m_layout_index (layout_index), m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0) { if (dss->is_valid_layout_index (m_layout_index)) { m_iter = db::RecursiveShapeIterator (dss->layout (m_layout_index), dss->initial_cell (m_layout_index), std::set ()); @@ -66,7 +66,7 @@ LayoutToNetlist::LayoutToNetlist (db::DeepShapeStore *dss, unsigned int layout_i } LayoutToNetlist::LayoutToNetlist (const std::string &topcell_name, double dbu) - : m_iter (), m_netlist_extracted (false), m_is_flat (true) + : m_iter (), m_netlist_extracted (false), m_is_flat (true), m_device_scaling (1.0) { mp_internal_dss.reset (new db::DeepShapeStore (topcell_name, dbu)); mp_dss.reset (mp_internal_dss.get ()); @@ -77,7 +77,7 @@ LayoutToNetlist::LayoutToNetlist (const std::string &topcell_name, double dbu) LayoutToNetlist::LayoutToNetlist () : m_iter (), mp_internal_dss (new db::DeepShapeStore ()), mp_dss (mp_internal_dss.get ()), m_layout_index (0), - m_netlist_extracted (false), m_is_flat (false) + m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0) { init (); } @@ -136,6 +136,16 @@ size_t LayoutToNetlist::max_vertex_count () const return dss ().max_vertex_count (); } +void LayoutToNetlist::set_device_scaling (double s) +{ + m_device_scaling = s; +} + +double LayoutToNetlist::device_scaling () const +{ + return m_device_scaling; +} + db::Region *LayoutToNetlist::make_layer (const std::string &n) { db::RecursiveShapeIterator si (m_iter); @@ -187,15 +197,37 @@ db::Region *LayoutToNetlist::make_polygon_layer (unsigned int layer_index, const return region.release (); } +size_t LayoutToNetlist::link_net_to_parent_circuit (const Net *subcircuit_net, Circuit *parent_circuit, const DCplxTrans &dtrans) +{ + if (! subcircuit_net->circuit () || ! has_internal_layout () || ! internal_layout ()->is_valid_cell_index (parent_circuit->cell_index ())) { + return 0; + } + + db::CplxTrans dbu_trans (internal_layout ()->dbu ()); + db::ICplxTrans trans = dbu_trans.inverted () * dtrans * dbu_trans; + + connected_clusters &parent_net_clusters = m_net_clusters.clusters_per_cell (parent_circuit->cell_index ()); + + size_t id = parent_net_clusters.insert_dummy (); // @@@ + + parent_net_clusters.add_connection (id, db::ClusterInstance (subcircuit_net->cluster_id (), subcircuit_net->circuit ()->cell_index (), trans, 0)); + return id; +} + +void LayoutToNetlist::ensure_netlist () +{ + if (! mp_netlist.get ()) { + mp_netlist.reset (new db::Netlist (this)); + } +} + void LayoutToNetlist::extract_devices (db::NetlistDeviceExtractor &extractor, const std::map &layers) { if (m_netlist_extracted) { throw tl::Exception (tl::to_string (tr ("The netlist has already been extracted"))); } - if (! mp_netlist.get ()) { - mp_netlist.reset (new db::Netlist ()); - } - extractor.extract (dss (), m_layout_index, layers, *mp_netlist, m_net_clusters); + ensure_netlist (); + extractor.extract (dss (), m_layout_index, layers, *mp_netlist, m_net_clusters, m_device_scaling); } void LayoutToNetlist::connect (const db::Region &l) @@ -267,9 +299,7 @@ void LayoutToNetlist::extract_netlist (const std::string &joined_net_names) if (m_netlist_extracted) { throw tl::Exception (tl::to_string (tr ("The netlist has already been extracted"))); } - if (! mp_netlist.get ()) { - mp_netlist.reset (new db::Netlist ()); - } + ensure_netlist (); db::NetlistExtractor netex; netex.extract_nets (dss (), m_layout_index, m_conn, *mp_netlist, m_net_clusters, joined_net_names); @@ -282,6 +312,11 @@ void LayoutToNetlist::set_netlist_extracted () m_netlist_extracted = true; } +bool LayoutToNetlist::has_internal_layout () const +{ + return mp_dss.get () && mp_dss->is_valid_layout_index (m_layout_index); +} + const db::Layout *LayoutToNetlist::internal_layout () const { ensure_layout (); @@ -530,9 +565,7 @@ db::Netlist *LayoutToNetlist::netlist () const db::Netlist *LayoutToNetlist::make_netlist () { - if (! mp_netlist.get ()) { - mp_netlist.reset (new db::Netlist ()); - } + ensure_netlist (); return mp_netlist.get (); } diff --git a/src/db/db/dbLayoutToNetlist.h b/src/db/db/dbLayoutToNetlist.h index cb5485a8b..e2287a301 100644 --- a/src/db/db/dbLayoutToNetlist.h +++ b/src/db/db/dbLayoutToNetlist.h @@ -70,7 +70,7 @@ namespace db * @li */ class DB_PUBLIC LayoutToNetlist - : public gsi::ObjectBase, public tl::Object + : public gsi::ObjectBase, public db::NetlistManipulationCallbacks { public: typedef std::map::const_iterator layer_iterator; @@ -220,6 +220,18 @@ public: */ size_t max_vertex_count () const; + /** + * @brief Sets the device scaling factor + * This factor will scale the physical properties of the extracted devices + * accordingly. The scale factor applies an isotropic shrink (<1) or expansion (>1). + */ + void set_device_scaling (double s); + + /** + * @brief Gets the device scaling factor + */ + double device_scaling () const; + /** * @brief Register a layer under the given name * This is a formal name for the layer. Using a name or layer properties @@ -397,6 +409,11 @@ public: return *mp_dss; } + /** + * @brief Returns true, if there a layout is set + */ + bool has_internal_layout () const; + /** * @brief Gets the internal layout */ @@ -711,6 +728,7 @@ private: std::map m_name_of_layer; bool m_netlist_extracted; bool m_is_flat; + double m_device_scaling; db::DeepLayer m_dummy_layer; struct CellReuseTableKey @@ -743,6 +761,7 @@ private: typedef std::map cell_reuse_table_type; void init (); + void ensure_netlist (); size_t search_net (const db::ICplxTrans &trans, const db::Cell *cell, const db::local_cluster &test_cluster, std::vector &rev_inst_path); void build_net_rec (const db::Net &net, db::Layout &target, cell_index_type circuit_cell, const db::CellMapping &cmap, const std::map &lmap, const char *net_cell_name_prefix, db::properties_id_type netname_propid, BuildNetHierarchyMode hier_mode, const char *cell_name_prefix, const char *device_cell_name_prefix, cell_reuse_table_type &reuse_table, const ICplxTrans &tr) const; void build_net_rec (const db::Net &net, db::Layout &target, db::Cell &target_cell, const std::map &lmap, const char *net_cell_name_prefix, db::properties_id_type netname_propid, BuildNetHierarchyMode hier_mode, const char *cell_name_prefix, const char *device_cell_name_prefix, cell_reuse_table_type &reuse_table, const ICplxTrans &tr) const; @@ -752,6 +771,9 @@ private: std::string make_new_name (const std::string &stem = std::string ()); db::properties_id_type make_netname_propid (db::Layout &ly, const tl::Variant &netname_prop, const db::Net &net) const; db::CellMapping make_cell_mapping_into (db::Layout &layout, db::Cell &cell, const std::vector *nets, bool with_device_cells); + + // implementation of NetlistManipulationCallbacks + virtual size_t link_net_to_parent_circuit (const Net *subcircuit_net, Circuit *parent_circuit, const DCplxTrans &trans); }; } diff --git a/src/db/db/dbNetlist.cc b/src/db/db/dbNetlist.cc index 9b245fbf1..6b536c817 100644 --- a/src/db/db/dbNetlist.cc +++ b/src/db/db/dbNetlist.cc @@ -30,8 +30,9 @@ namespace db // -------------------------------------------------------------------------------- // Netlist class implementation -Netlist::Netlist () - : m_valid_topology (false), m_lock_count (0), +Netlist::Netlist (NetlistManipulationCallbacks *callbacks) + : mp_callbacks (callbacks), + m_valid_topology (false), m_lock_count (0), m_circuit_by_name (this, &Netlist::begin_circuits, &Netlist::end_circuits), m_circuit_by_cell_index (this, &Netlist::begin_circuits, &Netlist::end_circuits), m_device_abstract_by_name (this, &Netlist::begin_device_abstracts, &Netlist::end_device_abstracts), diff --git a/src/db/db/dbNetlist.h b/src/db/db/dbNetlist.h index df443c2c0..da26bd399 100644 --- a/src/db/db/dbNetlist.h +++ b/src/db/db/dbNetlist.h @@ -35,6 +35,20 @@ namespace db { +/** + * @brief An interface which connects the netlist with a layout representation + * Specifically this interface allows manipulating the layout in sync with the netlist. + */ +class DB_PUBLIC NetlistManipulationCallbacks + : public tl::Object +{ +public: + NetlistManipulationCallbacks () { } + virtual ~NetlistManipulationCallbacks () { } + + virtual size_t link_net_to_parent_circuit (const db::Net *subcircuit_net, db::Circuit *parent_circuit, const db::DCplxTrans &trans) = 0; +}; + /** * @brief The netlist class * @@ -65,7 +79,7 @@ public: * * This constructor creates an empty hierarchical netlist */ - Netlist (); + Netlist (NetlistManipulationCallbacks *callbacks = 0); /** * @brief Copy constructor @@ -480,6 +494,7 @@ private: friend class Circuit; friend class DeviceAbstract; + tl::weak_ptr mp_callbacks; circuit_list m_circuits; device_class_list m_device_classes; device_abstract_list m_device_abstracts; @@ -494,6 +509,11 @@ private: object_by_attr > m_device_abstract_by_name; object_by_attr > m_device_abstract_by_cell_index; + db::NetlistManipulationCallbacks *callbacks () + { + return mp_callbacks.get (); + } + void invalidate_topology (); void validate_topology (); void circuits_changed (); diff --git a/src/db/db/dbNetlistCompare.cc b/src/db/db/dbNetlistCompare.cc index 11fb51ba2..c1ee28855 100644 --- a/src/db/db/dbNetlistCompare.cc +++ b/src/db/db/dbNetlistCompare.cc @@ -2083,6 +2083,49 @@ NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b, NetlistCom return res; } +void +NetlistComparer::unmatched_circuits (db::Netlist *a, db::Netlist *b, std::vector &in_a, std::vector &in_b) const +{ + // we need to create a copy because this method is supposed to be const. + db::CircuitCategorizer circuit_categorizer = *mp_circuit_categorizer; + + std::map > cat2circuits; + + for (db::Netlist::circuit_iterator i = a->begin_circuits (); i != a->end_circuits (); ++i) { + size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ()); + if (cat && i->begin_refs () != i->end_refs ()) { + cat2circuits[cat].first = i.operator-> (); + } + } + + for (db::Netlist::circuit_iterator i = b->begin_circuits (); i != b->end_circuits (); ++i) { + size_t cat = circuit_categorizer.cat_for_circuit (i.operator-> ()); + if (cat && i->begin_refs () != i->end_refs ()) { + cat2circuits[cat].second = i.operator-> (); + } + } + + size_t na = 0, nb = 0; + for (std::map >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) { + if (! i->second.first) { + ++nb; + } else if (! i->second.second) { + ++na; + } + } + + in_a.reserve (na); + in_b.reserve (nb); + + for (std::map >::const_iterator i = cat2circuits.begin (); i != cat2circuits.end (); ++i) { + if (! i->second.first) { + in_b.push_back (i->second.second); + } else if (! i->second.second) { + in_a.push_back (i->second.first); + } + } +} + bool NetlistComparer::compare (const db::Netlist *a, const db::Netlist *b) const { @@ -2368,6 +2411,42 @@ struct KeySize } }; +struct DeviceConnectionDistance +{ + typedef std::pair >, std::pair > value_type; + + double operator() (const value_type &a, const value_type &b) const + { + int d = 0.0; + for (std::vector >::const_iterator i = a.first.begin (), j = b.first.begin (); i != a.first.end () && j != b.first.end (); ++i, ++j) { + if (i->second != j->second || i->second == std::numeric_limits::max () || j->second == std::numeric_limits::max ()) { + ++d; + } + } + return double (d); + } +}; + +struct DeviceParametersCompare +{ + typedef std::pair >, std::pair > value_type; + + bool operator() (const value_type &a, const value_type &b) const + { + // category and parameters + return m_dc (a.second, b.second); + } + + bool equals (const value_type &a, const value_type &b) const + { + // category and parameters + return m_dc.equals (a.second, b.second); + } + +private: + db::DeviceCompare m_dc; +}; + template void align (Iter i1, Iter i2, Iter j1, Iter j2, Distance distance) { @@ -2403,12 +2482,12 @@ void align (Iter i1, Iter i2, Iter j1, Iter j2, Distance distance) any_swapped = false; - for (size_t m = n + 1; m < vj.size () - 1; ++m) { + for (size_t m = n + 1; m < vj.size (); ++m) { if (vi [n] == Iter () || vi [m] == Iter () || vj [n] == Iter () || vj [m] == Iter ()) { continue; } else if (distance (*vi [n], *vj [m]) + distance (*vi [m], *vj [n]) < distance (*vi [n], *vj [n]) + distance (*vi [m], *vj [m])) { // this will reduce the overall distance: - std::swap (vj [n], vj [m]); + std::swap (*vj [n], *vj [m]); any_swapped = true; } } @@ -2419,7 +2498,14 @@ void align (Iter i1, Iter i2, Iter j1, Iter j2, Distance distance) } bool -NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, db::DeviceCategorizer &device_categorizer, db::CircuitCategorizer &circuit_categorizer, db::CircuitPinMapper &circuit_pin_mapper, const std::vector > &net_identity, bool &pin_mismatch, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping) const +NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, + db::DeviceCategorizer &device_categorizer, + db::CircuitCategorizer &circuit_categorizer, + db::CircuitPinMapper &circuit_pin_mapper, + const std::vector > &net_identity, + bool &pin_mismatch, + std::map &c12_circuit_and_pin_mapping, + std::map &c22_circuit_and_pin_mapping) const { db::DeviceFilter device_filter (m_cap_threshold, m_res_threshold); @@ -2562,7 +2648,16 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, } } + do_pin_assignment (c1, g1, c2, g2, c12_circuit_and_pin_mapping, c22_circuit_and_pin_mapping, pin_mismatch, good); + do_device_assignment (c1, g1, c2, g2, device_filter, device_categorizer, good); + do_subcircuit_assignment (c1, g1, c2, g2, circuit_categorizer, circuit_pin_mapper, c12_circuit_and_pin_mapping, c22_circuit_and_pin_mapping, good); + return good; +} + +void +NetlistComparer::do_pin_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &pin_mismatch, bool &good) const +{ // Report pin assignment // This step also does the pin identity mapping. @@ -2742,10 +2837,18 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, } +} + +void +NetlistComparer::do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, db::DeviceCategorizer &device_categorizer, bool &good) const +{ // Report device assignment std::multimap >, std::pair > device_map; + typedef std::vector >, std::pair > > unmatched_list; + unmatched_list unmatched_a, unmatched_b; + for (db::Circuit::const_device_iterator d = c1->begin_devices (); d != c1->end_devices (); ++d) { if (! device_filter.filter (d.operator-> ())) { @@ -2761,15 +2864,16 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, std::vector > k = compute_device_key (*d, g1); bool mapped = true; - for (std::vector >::iterator i = k.begin (); i != k.end () && mapped; ++i) { + for (std::vector >::iterator i = k.begin (); i != k.end (); ++i) { if (! g1.begin () [i->second].has_other ()) { + i->second = std::numeric_limits::max (); // normalization mapped = false; } } if (! mapped) { if (mp_logger) { - mp_logger->device_mismatch (d.operator-> (), 0); + unmatched_a.push_back (std::make_pair (k, std::make_pair (d.operator-> (), device_cat))); } good = false; } else { @@ -2796,6 +2900,7 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, bool mapped = true; for (std::vector >::iterator i = k.begin (); i != k.end (); ++i) { if (! g2.begin () [i->second].has_other ()) { + i->second = std::numeric_limits::max (); // normalization mapped = false; } else { i->second = g2.begin () [i->second].other_net_index (); @@ -2809,7 +2914,7 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, if (! mapped || dm == device_map.end () || dm->first != k) { if (mp_logger) { - mp_logger->device_mismatch (0, d.operator-> ()); + unmatched_b.push_back (std::make_pair (k, std::make_pair (d.operator-> (), device_cat))); } good = false; @@ -2843,12 +2948,90 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, for (std::multimap >, std::pair >::const_iterator dm = device_map.begin (); dm != device_map.end (); ++dm) { if (mp_logger) { - mp_logger->device_mismatch (dm->second.first, 0); + unmatched_a.push_back (*dm); } good = false; } + // try to do some better mapping of unmatched devices - they will still be reported as mismatching, but their pairing gives some hint + // what to fix. + if (mp_logger) { + + size_t max_analysis_set = 1000; + if (unmatched_a.size () + unmatched_b.size () > max_analysis_set) { + + // don't try too much analysis - this may be a waste of time + for (unmatched_list::const_iterator i = unmatched_a.begin (); i != unmatched_a.end (); ++i) { + mp_logger->device_mismatch (i->second.first, 0); + } + for (unmatched_list::const_iterator i = unmatched_b.begin (); i != unmatched_b.end (); ++i) { + mp_logger->device_mismatch (0, i->second.first); + } + + } else { + + DeviceParametersCompare cmp; + + std::sort (unmatched_a.begin (), unmatched_a.end (), cmp); + std::sort (unmatched_b.begin (), unmatched_b.end (), cmp); + + for (unmatched_list::iterator i = unmatched_a.begin (), j = unmatched_b.begin (); i != unmatched_a.end () || j != unmatched_b.end (); ) { + + while (j != unmatched_b.end () && (i == unmatched_a.end () || !cmp.equals (*j, *i))) { + mp_logger->device_mismatch (0, j->second.first); + ++j; + } + + while (i != unmatched_a.end () && (j == unmatched_b.end () || !cmp.equals (*i, *j))) { + mp_logger->device_mismatch (i->second.first, 0); + ++i; + } + + if (i == unmatched_a.end () && j == unmatched_b.end ()) { + break; + } + + unmatched_list::iterator ii = i, jj = j; + ++i, ++j; + size_t n = ii->first.size (); + tl_assert (n == jj->first.size ()); + + while (i != unmatched_a.end () && cmp.equals (*i, *ii)) { + ++i; + } + + while (j != unmatched_b.end () && cmp.equals (*j, *jj)) { + ++j; + } + + if (i - ii == size_t(2)) { + printf("@@@1\n"); fflush(stdout); + } + align (ii, i, jj, j, DeviceConnectionDistance ()); + + for ( ; ii != i && jj != j; ++ii, ++jj) { + mp_logger->device_mismatch (ii->second.first, jj->second.first); + } + + for ( ; jj != j; ++jj) { + mp_logger->device_mismatch (0, jj->second.first); + } + + for ( ; ii != i; ++ii) { + mp_logger->device_mismatch (ii->second.first, 0); + } + + } + + } + + } +} + +void +NetlistComparer::do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const CircuitPinMapper &circuit_pin_mapper, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &good) const +{ // Report subcircuit assignment std::multimap >, std::pair > subcircuit_map; @@ -3012,8 +3195,6 @@ NetlistComparer::compare_circuits (const db::Circuit *c1, const db::Circuit *c2, } } - - return good; } } diff --git a/src/db/db/dbNetlistCompare.h b/src/db/db/dbNetlistCompare.h index 7fa46f99a..774936442 100644 --- a/src/db/db/dbNetlistCompare.h +++ b/src/db/db/dbNetlistCompare.h @@ -33,9 +33,11 @@ namespace db { class CircuitPinMapper; +class DeviceFilter; class DeviceCategorizer; class CircuitCategorizer; class CircuitMapper; +class NetGraph; /** * @brief A receiver for netlist compare events @@ -266,6 +268,13 @@ public: return m_max_n_branch; } + /** + * @brief Gets the list of circuits without matching circuit in the other netlist + * The result can be used to flatten these circuits prior to compare. + * Mismatching top level circuits are not reported because they cannot be flattened. + */ + void unmatched_circuits (db::Netlist *a, db::Netlist *b, std::vector &in_a, std::vector &in_b) const; + /** * @brief Actually compares the two netlists */ @@ -285,6 +294,9 @@ protected: bool compare_circuits (const db::Circuit *c1, const db::Circuit *c2, db::DeviceCategorizer &device_categorizer, db::CircuitCategorizer &circuit_categorizer, db::CircuitPinMapper &circuit_pin_mapper, const std::vector > &net_identity, bool &pin_mismatch, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping) const; bool all_subcircuits_verified (const db::Circuit *c, const std::set &verified_circuits) const; static void derive_pin_equivalence (const db::Circuit *ca, const db::Circuit *cb, CircuitPinMapper *circuit_pin_mapper); + void do_pin_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &pin_mismatch, bool &good) const; + void do_device_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, const db::DeviceFilter &device_filter, DeviceCategorizer &device_categorizer, bool &good) const; + void do_subcircuit_assignment (const db::Circuit *c1, const db::NetGraph &g1, const db::Circuit *c2, const db::NetGraph &g2, CircuitCategorizer &circuit_categorizer, const db::CircuitPinMapper &circuit_pin_mapper, std::map &c12_circuit_and_pin_mapping, std::map &c22_circuit_and_pin_mapping, bool &good) const; mutable NetlistCompareLogger *mp_logger; std::map, std::vector > > m_same_nets; diff --git a/src/db/db/dbNetlistCrossReference.cc b/src/db/db/dbNetlistCrossReference.cc index 5b6ad9ee7..344969908 100644 --- a/src/db/db/dbNetlistCrossReference.cc +++ b/src/db/db/dbNetlistCrossReference.cc @@ -141,6 +141,36 @@ struct by_expanded_name_value_compare } }; +struct ByDeviceClassNameCompare +{ + int operator() (const db::Device &a, const db::Device &b) const + { + if ((a.device_class () == 0) != (b.device_class () == 0)) { + return a.device_class () == 0 ? -1 : 1; + } + if (a.device_class () == 0) { + return 0; + } else { + return string_value_compare (a.device_class ()->name (), b.device_class ()->name ()); + } + } +}; + +struct ByRefCircuitNameCompare +{ + int operator() (const db::SubCircuit &a, const db::SubCircuit &b) const + { + if ((a.circuit_ref () == 0) != (b.circuit_ref () == 0)) { + return a.circuit_ref () == 0 ? -1 : 1; + } + if (a.circuit_ref () == 0) { + return 0; + } else { + return string_value_compare (a.circuit_ref ()->name (), b.circuit_ref ()->name ()); + } + } +}; + template struct net_object_compare; @@ -246,11 +276,17 @@ struct SortNetSubCircuitPins } void -NetlistCrossReference::gen_end_netlist (const db::Netlist *, const db::Netlist *) +NetlistCrossReference::sort_netlist () { std::sort (m_circuits.begin (), m_circuits.end (), CircuitsCompareByName ()); } +void +NetlistCrossReference::gen_end_netlist (const db::Netlist *, const db::Netlist *) +{ + // .. nothing yet .. +} + void NetlistCrossReference::establish_pair (const db::Circuit *a, const db::Circuit *b) { @@ -323,16 +359,21 @@ NetlistCrossReference::gen_begin_circuit (const db::Circuit *a, const db::Circui establish_pair (a, b); } +void +NetlistCrossReference::sort_circuit () +{ + std::stable_sort (mp_per_circuit_data->devices.begin (), mp_per_circuit_data->devices.end (), pair_data_compare ()); + std::stable_sort (mp_per_circuit_data->subcircuits.begin (), mp_per_circuit_data->subcircuits.end (), pair_data_compare ()); + + std::stable_sort (mp_per_circuit_data->pins.begin (), mp_per_circuit_data->pins.end (), pair_data_compare > ()); + std::stable_sort (mp_per_circuit_data->nets.begin (), mp_per_circuit_data->nets.end (), pair_data_compare > ()); +} + void NetlistCrossReference::gen_end_circuit (const db::Circuit *, const db::Circuit *, Status status) { mp_per_circuit_data->status = status; - std::stable_sort (mp_per_circuit_data->devices.begin (), mp_per_circuit_data->devices.end (), pair_data_compare > ()); - std::stable_sort (mp_per_circuit_data->pins.begin (), mp_per_circuit_data->pins.end (), pair_data_compare > ()); - std::stable_sort (mp_per_circuit_data->subcircuits.begin (), mp_per_circuit_data->subcircuits.end (), pair_data_compare > ()); - std::stable_sort (mp_per_circuit_data->nets.begin (), mp_per_circuit_data->nets.end (), pair_data_compare > ()); - m_current_circuits = std::make_pair((const db::Circuit *)0, (const db::Circuit *)0); mp_per_circuit_data = 0; } diff --git a/src/db/db/dbNetlistCrossReference.h b/src/db/db/dbNetlistCrossReference.h index 176750208..3b1b8ae85 100644 --- a/src/db/db/dbNetlistCrossReference.h +++ b/src/db/db/dbNetlistCrossReference.h @@ -153,6 +153,7 @@ public: virtual void end_netlist (const db::Netlist *a, const db::Netlist *b) { + sort_netlist (); gen_end_netlist (a, b); } @@ -163,6 +164,7 @@ public: virtual void end_circuit (const db::Circuit *a, const db::Circuit *b, bool matching) { + sort_circuit (); gen_end_circuit (a, b, matching ? Match : NoMatch); } @@ -291,6 +293,8 @@ private: void establish_pair (const db::Device *a, const db::Device *b, Status status); void establish_pair (const db::Pin *a, const db::Pin *b, Status status); void establish_pair (const db::SubCircuit *a, const db::SubCircuit *b, Status status); + void sort_circuit (); + void sort_netlist (); void build_per_net_info (const std::pair &nets, PerNetData &data) const; void build_subcircuit_pin_refs (const std::pair &nets, PerNetData &data) const; diff --git a/src/db/db/dbNetlistDeviceExtractor.cc b/src/db/db/dbNetlistDeviceExtractor.cc index 77df10bd1..5f1bc66c0 100644 --- a/src/db/db/dbNetlistDeviceExtractor.cc +++ b/src/db/db/dbNetlistDeviceExtractor.cc @@ -75,7 +75,7 @@ std::string NetlistDeviceExtractorError::to_string () const // NetlistDeviceExtractor implementation NetlistDeviceExtractor::NetlistDeviceExtractor (const std::string &name) - : mp_layout (0), m_cell_index (0), mp_circuit (0) + : mp_layout (0), m_cell_index (0), m_device_scaling (1.0), mp_circuit (0) { m_name = name; m_terminal_id_propname_id = 0; @@ -110,6 +110,7 @@ void NetlistDeviceExtractor::initialize (db::Netlist *nl) { m_layer_definitions.clear (); mp_device_class = 0; + m_device_scaling = 1.0; m_terminal_id_propname_id = 0; m_device_id_propname_id = 0; m_device_class_propname_id = 0; @@ -123,7 +124,7 @@ static void insert_into_region (const db::PolygonRef &s, const db::ICplxTrans &t region.insert (s.obj ().transformed (tr * db::ICplxTrans (s.trans ()))); } -void NetlistDeviceExtractor::extract (db::DeepShapeStore &dss, unsigned int layout_index, const NetlistDeviceExtractor::input_layers &layer_map, db::Netlist &nl, hier_clusters_type &clusters) +void NetlistDeviceExtractor::extract (db::DeepShapeStore &dss, unsigned int layout_index, const NetlistDeviceExtractor::input_layers &layer_map, db::Netlist &nl, hier_clusters_type &clusters, double device_scaling) { initialize (&nl); @@ -183,13 +184,13 @@ void NetlistDeviceExtractor::extract (db::DeepShapeStore &dss, unsigned int layo } - extract_without_initialize (dss.layout (layout_index), dss.initial_cell (layout_index), clusters, layers); + extract_without_initialize (dss.layout (layout_index), dss.initial_cell (layout_index), clusters, layers, device_scaling); } -void NetlistDeviceExtractor::extract (db::Layout &layout, db::Cell &cell, const std::vector &layers, db::Netlist *nl, hier_clusters_type &clusters) +void NetlistDeviceExtractor::extract (db::Layout &layout, db::Cell &cell, const std::vector &layers, db::Netlist *nl, hier_clusters_type &clusters, double device_scaling) { initialize (nl); - extract_without_initialize (layout, cell, clusters, layers); + extract_without_initialize (layout, cell, clusters, layers, device_scaling); } namespace { @@ -202,7 +203,7 @@ struct ExtractorCacheValueType { } -void NetlistDeviceExtractor::extract_without_initialize (db::Layout &layout, db::Cell &cell, hier_clusters_type &clusters, const std::vector &layers) +void NetlistDeviceExtractor::extract_without_initialize (db::Layout &layout, db::Cell &cell, hier_clusters_type &clusters, const std::vector &layers, double device_scaling) { tl_assert (layers.size () == m_layer_definitions.size ()); @@ -212,6 +213,7 @@ void NetlistDeviceExtractor::extract_without_initialize (db::Layout &layout, db: mp_layout = &layout; m_layers = layers; mp_clusters = &clusters; + m_device_scaling = device_scaling; // terminal properties are kept in a property with the terminal_property_name name m_terminal_id_propname_id = mp_layout->properties_repository ().prop_name_id (terminal_id_property_name ()); diff --git a/src/db/db/dbNetlistDeviceExtractor.h b/src/db/db/dbNetlistDeviceExtractor.h index 1cec36080..5143b9c7f 100644 --- a/src/db/db/dbNetlistDeviceExtractor.h +++ b/src/db/db/dbNetlistDeviceExtractor.h @@ -263,7 +263,7 @@ public: * * NOTE: The extractor expects "PolygonRef" type layers. */ - void extract (Layout &layout, Cell &cell, const std::vector &layers, Netlist *netlist, hier_clusters_type &clusters); + void extract (Layout &layout, Cell &cell, const std::vector &layers, Netlist *netlist, hier_clusters_type &clusters, double device_scaling = 1.0); /** * @brief Extracts the devices from a list of regions @@ -272,7 +272,7 @@ public: * named regions for input. These regions need to be of deep region type and * originate from the same layout than the DeepShapeStore. */ - void extract (DeepShapeStore &dss, unsigned int layout_index, const input_layers &layers, Netlist &netlist, hier_clusters_type &clusters); + void extract (DeepShapeStore &dss, unsigned int layout_index, const input_layers &layers, Netlist &netlist, hier_clusters_type &clusters, double device_scaling = 1.0); /** * @brief Gets the error iterator, begin @@ -416,6 +416,16 @@ public: return mp_layout->dbu (); } + /** + * @brief Gets the scaled database unit + * Use this unit to compute device properties. It is the database unit multiplied with the + * device scaling factor. + */ + double sdbu () const + { + return m_device_scaling * mp_layout->dbu (); + } + /** * @brief Gets the layout the shapes are taken from * NOTE: this method is provided for testing purposes mainly. @@ -523,6 +533,7 @@ private: db::properties_id_type m_terminal_id_propname_id, m_device_id_propname_id, m_device_class_propname_id; hier_clusters_type *mp_clusters; db::cell_index_type m_cell_index; + double m_device_scaling; db::Circuit *mp_circuit; db::DeviceClass *mp_device_class; std::string m_name; @@ -542,7 +553,7 @@ private: */ void initialize (db::Netlist *nl); - void extract_without_initialize (db::Layout &layout, db::Cell &cell, hier_clusters_type &clusters, const std::vector &layers); + void extract_without_initialize (db::Layout &layout, db::Cell &cell, hier_clusters_type &clusters, const std::vector &layers, double device_scaling); void push_new_devices (const Vector &disp_cache); void push_cached_devices (const tl::vector &cached_devices, const db::Vector &disp_cache, const db::Vector &new_disp); }; diff --git a/src/db/db/dbNetlistDeviceExtractorClasses.cc b/src/db/db/dbNetlistDeviceExtractorClasses.cc index 75dc62542..394c74bad 100644 --- a/src/db/db/dbNetlistDeviceExtractorClasses.cc +++ b/src/db/db/dbNetlistDeviceExtractorClasses.cc @@ -112,8 +112,8 @@ void NetlistDeviceExtractorMOS3Transistor::extract_devices (const std::vectorset_trans (db::DCplxTrans ((p->box ().center () - db::Point ()) * dbu ())); - device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_W, dbu () * edges.length () * 0.5); - device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_L, dbu () * (p->perimeter () - edges.length ()) * 0.5); + device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_W, sdbu () * edges.length () * 0.5); + device->set_parameter_value (db::DeviceClassMOS3Transistor::param_id_L, sdbu () * (p->perimeter () - edges.length ()) * 0.5); int diff_index = 0; for (db::Region::const_iterator d = rdiff2gate.begin (); !d.at_end () && diff_index < 2; ++d, ++diff_index) { @@ -123,8 +123,8 @@ void NetlistDeviceExtractorMOS3Transistor::extract_devices (const std::vector 0); - device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_AS : db::DeviceClassMOS3Transistor::param_id_AD, dbu () * dbu () * d->area () / double (n)); - device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_PS : db::DeviceClassMOS3Transistor::param_id_PD, dbu () * d->perimeter () / double (n)); + device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_AS : db::DeviceClassMOS3Transistor::param_id_AD, sdbu () * sdbu () * d->area () / double (n)); + device->set_parameter_value (diff_index == 0 ? db::DeviceClassMOS3Transistor::param_id_PS : db::DeviceClassMOS3Transistor::param_id_PD, sdbu () * d->perimeter () / double (n)); unsigned int sd_index = diff_index == 0 ? source_terminal_geometry_index : drain_terminal_geometry_index; define_terminal (device, diff_index == 0 ? db::DeviceClassMOS3Transistor::terminal_id_S : db::DeviceClassMOS3Transistor::terminal_id_D, sd_index, *d); @@ -262,10 +262,10 @@ void NetlistDeviceExtractorResistor::extract_devices (const std::vectorset_parameter_value (db::DeviceClassResistor::param_id_R, m_sheet_rho * double (length) / double (width)); - device->set_parameter_value (db::DeviceClassResistor::param_id_L, dbu () * length); - device->set_parameter_value (db::DeviceClassResistor::param_id_W, dbu () * width); - device->set_parameter_value (db::DeviceClassResistor::param_id_A, dbu () * dbu () * p->area ()); - device->set_parameter_value (db::DeviceClassResistor::param_id_P, dbu () * p->perimeter ()); + device->set_parameter_value (db::DeviceClassResistor::param_id_L, sdbu () * length); + device->set_parameter_value (db::DeviceClassResistor::param_id_W, sdbu () * width); + device->set_parameter_value (db::DeviceClassResistor::param_id_A, sdbu () * sdbu () * p->area ()); + device->set_parameter_value (db::DeviceClassResistor::param_id_P, sdbu () * p->perimeter ()); int cont_index = 0; for (db::Region::const_iterator d = contacts_per_res.begin (); !d.at_end () && cont_index < 2; ++d, ++cont_index) { @@ -366,11 +366,11 @@ void NetlistDeviceExtractorCapacitor::extract_devices (const std::vectorset_trans (db::DCplxTrans ((p->box ().center () - db::Point ()) * dbu ())); - double area = p->area () * dbu () * dbu (); + double area = p->area () * sdbu () * sdbu (); device->set_parameter_value (db::DeviceClassCapacitor::param_id_C, m_area_cap * area); device->set_parameter_value (db::DeviceClassCapacitor::param_id_A, area); - device->set_parameter_value (db::DeviceClassCapacitor::param_id_P, dbu () * p->perimeter ()); + device->set_parameter_value (db::DeviceClassCapacitor::param_id_P, sdbu () * p->perimeter ()); define_terminal (device, db::DeviceClassCapacitor::terminal_id_A, a_terminal_geometry_index, *p); define_terminal (device, db::DeviceClassCapacitor::terminal_id_B, b_terminal_geometry_index, *p); @@ -498,11 +498,11 @@ void NetlistDeviceExtractorBJT3Transistor::extract_devices (const std::vectorarea (); - double pb = dbu () * p->perimeter (); + double ab = sdbu () * sdbu () * p->area (); + double pb = sdbu () * p->perimeter (); - double ac = dbu () * dbu () * rcollector2base.area (); - double pc = dbu () * rcollector2base.perimeter (); + double ac = sdbu () * sdbu () * rcollector2base.area (); + double pc = sdbu () * rcollector2base.perimeter (); for (db::Region::const_iterator pe = remitter2base.begin_merged (); !pe.at_end (); ++pe) { @@ -512,8 +512,8 @@ void NetlistDeviceExtractorBJT3Transistor::extract_devices (const std::vectorset_parameter_value (db::DeviceClassBJT3Transistor::param_id_NE, 1.0); - device->set_parameter_value (db::DeviceClassBJT3Transistor::param_id_AE, dbu () * dbu () * pe->area ()); - device->set_parameter_value (db::DeviceClassBJT3Transistor::param_id_PE, dbu () * pe->perimeter ()); + device->set_parameter_value (db::DeviceClassBJT3Transistor::param_id_AE, sdbu () * sdbu () * pe->area ()); + device->set_parameter_value (db::DeviceClassBJT3Transistor::param_id_PE, sdbu () * pe->perimeter ()); device->set_parameter_value (db::DeviceClassBJT3Transistor::param_id_AB, ab); device->set_parameter_value (db::DeviceClassBJT3Transistor::param_id_PB, pb); @@ -629,10 +629,10 @@ void NetlistDeviceExtractorDiode::extract_devices (const std::vector device->set_trans (db::DCplxTrans ((p->box ().center () - db::Point ()) * dbu ())); - double area = p->area () * dbu () * dbu (); + double area = p->area () * sdbu () * sdbu (); device->set_parameter_value (db::DeviceClassDiode::param_id_A, area); - device->set_parameter_value (db::DeviceClassDiode::param_id_P, dbu () * p->perimeter ()); + device->set_parameter_value (db::DeviceClassDiode::param_id_P, sdbu () * p->perimeter ()); define_terminal (device, db::DeviceClassDiode::terminal_id_A, a_terminal_geometry_index, *p); define_terminal (device, db::DeviceClassDiode::terminal_id_C, c_terminal_geometry_index, *p); diff --git a/src/db/db/dbNetlistSpiceReader.cc b/src/db/db/dbNetlistSpiceReader.cc index 7f7c4235c..50218d7d2 100644 --- a/src/db/db/dbNetlistSpiceReader.cc +++ b/src/db/db/dbNetlistSpiceReader.cc @@ -195,6 +195,7 @@ void NetlistSpiceReader::read (tl::InputStream &stream, db::Netlist &netlist) mp_netlist = &netlist; mp_circuit = 0; mp_nets_by_name.reset (0); + m_global_nets.clear (); try { @@ -343,6 +344,11 @@ bool NetlistSpiceReader::read_card () // ignore model statements + } else if (ex.test_without_case ("global")) { + + std::string n = read_name (ex); + m_global_nets.push_back (n); + } else if (ex.test_without_case ("subckt")) { std::string nc = read_name (ex); @@ -497,6 +503,10 @@ void NetlistSpiceReader::ensure_circuit () mp_circuit->set_name (".TOP"); mp_netlist->add_circuit (mp_circuit); + for (std::vector::const_iterator gn = m_global_nets.begin (); gn != m_global_nets.end (); ++gn) { + make_net (*gn); + } + } } @@ -737,16 +747,25 @@ void NetlistSpiceReader::read_subcircuit (const std::string &sc_name, const std: db::Circuit *cc = mp_netlist->circuit_by_name (nc_name); if (! cc) { + cc = new db::Circuit (); mp_netlist->add_circuit (cc); cc->set_name (nc_name); + + // we'll make the names later ... for (std::vector::const_iterator i = nets.begin (); i != nets.end (); ++i) { cc->add_pin (std::string ()); } + for (std::vector::const_iterator gn = m_global_nets.begin (); gn != m_global_nets.end (); ++gn) { + cc->add_pin (std::string ()); + } + } else { - if (cc->pin_count () != nets.size ()) { + + if (cc->pin_count () != nets.size () + m_global_nets.size ()) { error (tl::sprintf (tl::to_string (tr ("Pin count mismatch between circuit definition and circuit call: %d expected, got %d")), int (cc->pin_count ()), int (nets.size ()))); } + } db::SubCircuit *sc = new db::SubCircuit (cc, sc_name); @@ -755,6 +774,11 @@ void NetlistSpiceReader::read_subcircuit (const std::string &sc_name, const std: for (std::vector::const_iterator i = nets.begin (); i != nets.end (); ++i) { sc->connect_pin (i - nets.begin (), *i); } + + for (std::vector::const_iterator gn = m_global_nets.begin (); gn != m_global_nets.end (); ++gn) { + db::Net *net = make_net (*gn); + sc->connect_pin (gn - m_global_nets.begin () + nets.size (), net); + } } void NetlistSpiceReader::skip_circuit (tl::Extractor & /*ex*/) @@ -789,16 +813,23 @@ void NetlistSpiceReader::read_circuit (tl::Extractor &ex, const std::string &nc) db::Circuit *cc = mp_netlist->circuit_by_name (nc); if (! cc) { + cc = new db::Circuit (); mp_netlist->add_circuit (cc); cc->set_name (nc); for (std::vector::const_iterator i = nn.begin (); i != nn.end (); ++i) { cc->add_pin (std::string ()); } + for (std::vector::const_iterator gn = m_global_nets.begin (); gn != m_global_nets.end (); ++gn) { + cc->add_pin (std::string ()); + } + } else { - if (cc->pin_count () != nn.size ()) { + + if (cc->pin_count () != nn.size () + m_global_nets.size ()) { error (tl::sprintf (tl::to_string (tr ("Pin count mismatch between implicit (through call) and explicit circuit definition: %d expected, got %d")), int (cc->pin_count ()), int (nn.size ()))); } + } std::auto_ptr > n2n (mp_nets_by_name.release ()); @@ -806,13 +837,23 @@ void NetlistSpiceReader::read_circuit (tl::Extractor &ex, const std::string &nc) std::swap (cc, mp_circuit); + // produce the explicit pins for (std::vector::const_iterator i = nn.begin (); i != nn.end (); ++i) { db::Net *net = make_net (*i); // use the net name to name the pin (otherwise SPICE pins are always unnamed) + size_t pin_id = i - nn.begin (); if (! i->empty ()) { - mp_circuit->rename_pin (i - nn.begin (), net->name ()); + mp_circuit->rename_pin (pin_id, net->name ()); } - mp_circuit->connect_pin (i - nn.begin (), net); + mp_circuit->connect_pin (pin_id, net); + } + + // produce pins for the global nets + for (std::vector::const_iterator gn = m_global_nets.begin (); gn != m_global_nets.end (); ++gn) { + db::Net *net = make_net (*gn); + size_t pin_id = gn - m_global_nets.begin () + nn.size (); + mp_circuit->rename_pin (pin_id, net->name ()); + mp_circuit->connect_pin (pin_id, net); } while (! at_end ()) { diff --git a/src/db/db/dbNetlistSpiceReader.h b/src/db/db/dbNetlistSpiceReader.h index 056b2b2d4..95eca62e2 100644 --- a/src/db/db/dbNetlistSpiceReader.h +++ b/src/db/db/dbNetlistSpiceReader.h @@ -128,6 +128,7 @@ private: std::auto_ptr > mp_nets_by_name; std::string m_stored_line; std::map m_captured; + std::vector m_global_nets; void push_stream (const std::string &path); void pop_stream (); diff --git a/src/db/db/dbTestSupport.cc b/src/db/db/dbTestSupport.cc index 1d71cacca..86707a236 100644 --- a/src/db/db/dbTestSupport.cc +++ b/src/db/db/dbTestSupport.cc @@ -291,7 +291,7 @@ private: } }; -void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const std::string &au_nl_string) +void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const std::string &au_nl_string, bool exact_parameter_match) { db::Netlist au_nl; for (db::Netlist::const_device_class_iterator d = netlist.begin_device_classes (); d != netlist.end_device_classes (); ++d) { @@ -300,27 +300,29 @@ void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, au_nl.from_string (au_nl_string); - db::NetlistComparer comp (0); - - if (! comp.compare (&netlist, &au_nl)) { - _this->raise ("Compare failed - see log for details.\n\nActual:\n" + netlist.to_string () + "\nGolden:\n" + au_nl_string); - // Compare once again - this time with logger - CompareLogger logger; - db::NetlistComparer comp (&logger); - comp.compare (&netlist, &au_nl); - } + compare_netlist (_this, netlist, au_nl, exact_parameter_match); } -void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const db::Netlist &netlist_au) +void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const db::Netlist &netlist_au, bool exact_parameter_match) { db::NetlistComparer comp (0); - if (! comp.compare (&netlist, &netlist_au)) { - _this->raise ("Compare failed - see log for details.\n\nActual:\n" + netlist.to_string () + "\nGolden:\n" + netlist_au.to_string ()); + db::Netlist netlist_copy (netlist); + + if (exact_parameter_match) { + // install a "all parameters are equal" device parameter comparer so we make sure the devices are compared exactly + for (db::Netlist::device_class_iterator dc = netlist_copy.begin_device_classes (); dc != netlist_copy.end_device_classes (); ++dc) { + db::DeviceClass &cls = *dc; + cls.set_parameter_compare_delegate (new db::AllDeviceParametersAreEqual (0.01)); + } + } + + if (! comp.compare (&netlist_copy, &netlist_au)) { + _this->raise ("Compare failed - see log for details.\n\nActual:\n" + netlist_copy.to_string () + "\nGolden:\n" + netlist_au.to_string ()); // Compare once again - this time with logger CompareLogger logger; db::NetlistComparer comp (&logger); - comp.compare (&netlist, &netlist_au); + comp.compare (&netlist_copy, &netlist_au); } } diff --git a/src/db/db/dbTestSupport.h b/src/db/db/dbTestSupport.h index e079cf05b..6a9278040 100644 --- a/src/db/db/dbTestSupport.h +++ b/src/db/db/dbTestSupport.h @@ -77,12 +77,12 @@ void DB_PUBLIC compare_layouts (tl::TestBase *_this, const db::Layout &layout, c /** * @brief Compares a netlist against a string */ -void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const std::string &au_nl_string); +void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const std::string &au_nl_string, bool exact_parameter_match = false); /** * @brief Compares a netlist against another netlist */ -void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const db::Netlist &netlist_au); +void DB_PUBLIC compare_netlist (tl::TestBase *_this, const db::Netlist &netlist, const db::Netlist &netlist_au, bool exact_parameter_match = false); } diff --git a/src/db/db/gsiDeclDbLayoutToNetlist.cc b/src/db/db/gsiDeclDbLayoutToNetlist.cc index e1369989f..02ba6b3c9 100644 --- a/src/db/db/gsiDeclDbLayoutToNetlist.cc +++ b/src/db/db/gsiDeclDbLayoutToNetlist.cc @@ -198,6 +198,15 @@ Class decl_dbLayoutToNetlist ("db", "LayoutToNetlist", gsi::method ("max_vertex_count", &db::LayoutToNetlist::max_vertex_count, "See \\max_vertex_count= for details about this attribute." ) + + gsi::method ("device_scaling=", &db::LayoutToNetlist::set_device_scaling, gsi::arg ("f"), + "@brief Sets the device scaling factor\n" + "This factor will scale the physical properties of the extracted devices\n" + "accordingly. The scale factor applies an isotropic shrink (<1) or expansion (>1).\n" + ) + + gsi::method ("device_scaling", &db::LayoutToNetlist::device_scaling, + "@brief Gets the device scaling factor\n" + "See \\device_scaling= for details about this attribute." + ) + gsi::method ("name", (const std::string &(db::LayoutToNetlist::*) () const) &db::LayoutToNetlist::name, "@brief Gets the name of the database\n" ) + diff --git a/src/db/db/gsiDeclDbNetlist.cc b/src/db/db/gsiDeclDbNetlist.cc index 911262002..9523e7b7f 100644 --- a/src/db/db/gsiDeclDbNetlist.cc +++ b/src/db/db/gsiDeclDbNetlist.cc @@ -283,6 +283,15 @@ Class decl_dbDevice ("db", "Device", gsi::method ("name", &db::Device::name, "@brief Gets the name of the device.\n" ) + + gsi::method ("trans=", &db::Device::set_trans, gsi::arg ("t"), + "@brief Sets the location of the device.\n" + "The device location is essentially describing the position of the device. The position is typically the center of some " + "recognition shape. In this case the transformation is a plain displacement to the center of this shape." + ) + + gsi::method ("trans", &db::Device::trans, + "@brief Gets the location of the device.\n" + "See \\trans= for details about this method." + ) + gsi::method ("expanded_name", &db::Device::expanded_name, "@brief Gets the expanded name of the device.\n" "The expanded name takes the name of the device. If the name is empty, the numeric ID will be used to build a name. " diff --git a/src/db/db/gsiDeclDbNetlistCompare.cc b/src/db/db/gsiDeclDbNetlistCompare.cc index d9dd10c2c..0afaf06de 100644 --- a/src/db/db/gsiDeclDbNetlistCompare.cc +++ b/src/db/db/gsiDeclDbNetlistCompare.cc @@ -452,6 +452,20 @@ static db::NetlistComparer *make_comparer1 (GenericNetlistCompareLogger *logger) return new db::NetlistComparer (logger); } +static std::vector unmatched_circuits_a (const db::NetlistComparer *comparer, db::Netlist *a, db::Netlist *b) +{ + std::vector res_a, res_b; + comparer->unmatched_circuits (a, b, res_a, res_b); + return res_a; +} + +static std::vector unmatched_circuits_b (const db::NetlistComparer *comparer, db::Netlist *a, db::Netlist *b) +{ + std::vector res_a, res_b; + comparer->unmatched_circuits (a, b, res_a, res_b); + return res_b; +} + Class decl_dbNetlistComparer ("db", "NetlistComparer", gsi::constructor ("new", &make_comparer0, "@brief Creates a new comparer object.\n" @@ -524,6 +538,16 @@ Class decl_dbNetlistComparer ("db", "NetlistComparer", "@brief Gets the maximum branch complexity\n" "See \\max_branch_complexity= for details." ) + + gsi::method_ext ("unmatched_circuits_a", &unmatched_circuits_a, gsi::arg ("a"), gsi::arg ("b"), + "@brief Returns a list of circuits in A for which there is not corresponding circuit in B\n" + "This list can be used to flatten these circuits so they do not participate in the compare process.\n" + "Top level circuits are not included as they cannot be flattened.\n" + ) + + gsi::method_ext ("unmatched_circuits_b", &unmatched_circuits_b, gsi::arg ("a"), gsi::arg ("b"), + "@brief Returns a list of circuits in B for which there is not corresponding circuit in A\n" + "This list can be used to flatten these circuits so they do not participate in the compare process.\n" + "Top level circuits are not included as they cannot be flattened.\n" + ) + gsi::method ("compare", (bool (db::NetlistComparer::*) (const db::Netlist *, const db::Netlist *) const) &db::NetlistComparer::compare, gsi::arg ("netlist_a"), gsi::arg ("netlist_b"), "@brief Compares two netlists.\n" "This method will perform the actual netlist compare. It will return true if both netlists are identical. " diff --git a/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc b/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc index 2afd835f0..0851b5f4f 100644 --- a/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc +++ b/src/db/db/gsiDeclDbNetlistDeviceExtractor.cc @@ -331,6 +331,11 @@ Class decl_GenericDeviceExtractor (decl_dbNetlistDeviceE gsi::method ("dbu", &GenericDeviceExtractor::dbu, "@brief Gets the database unit\n" ) + + gsi::method ("sdbu", &GenericDeviceExtractor::sdbu, + "@brief Gets the scaled database unit\n" + "Use this unit to compute device properties. It is the database unit multiplied with the\n" + "device scaling factor." + ) + gsi::method ("error", (void (GenericDeviceExtractor::*) (const std::string &)) &GenericDeviceExtractor::error, gsi::arg ("message"), "@brief Issues an error with the given message\n" diff --git a/src/db/unit_tests/dbLayoutToNetlistTests.cc b/src/db/unit_tests/dbLayoutToNetlistTests.cc index 3fed04252..640552385 100644 --- a/src/db/unit_tests/dbLayoutToNetlistTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistTests.cc @@ -2755,3 +2755,258 @@ TEST(11_DuplicateInstances) "end;\n" ); } + +TEST(12_FlattenCircuitDoesFlattenLayout) +{ + db::Layout ly; + db::LayerMap lmap; + + unsigned int nwell = define_layer (ly, lmap, 1); + unsigned int active = define_layer (ly, lmap, 2); + unsigned int pplus = define_layer (ly, lmap, 10); + unsigned int nplus = define_layer (ly, lmap, 11); + unsigned int poly = define_layer (ly, lmap, 3); + unsigned int poly_lbl = define_layer (ly, lmap, 3, 1); + unsigned int diff_cont = define_layer (ly, lmap, 4); + unsigned int poly_cont = define_layer (ly, lmap, 5); + unsigned int metal1 = define_layer (ly, lmap, 6); + unsigned int metal1_lbl = define_layer (ly, lmap, 6, 1); + unsigned int via1 = define_layer (ly, lmap, 7); + unsigned int metal2 = define_layer (ly, lmap, 8); + unsigned int metal2_lbl = define_layer (ly, lmap, 8, 1); + + { + db::LoadLayoutOptions options; + options.get_options ().layer_map = lmap; + options.get_options ().create_other_layers = false; + + std::string fn (tl::testsrc ()); + fn = tl::combine_path (fn, "testdata"); + fn = tl::combine_path (fn, "algo"); + fn = tl::combine_path (fn, "device_extract_l5.gds"); + + tl::InputStream stream (fn); + db::Reader reader (stream); + reader.read (ly, options); + } + + db::Cell &tc = ly.cell (*ly.begin_top_down ()); + db::LayoutToNetlist l2n (db::RecursiveShapeIterator (ly, tc, std::set ())); + + std::auto_ptr rbulk (l2n.make_layer ("bulk")); + std::auto_ptr rnwell (l2n.make_layer (nwell, "nwell")); + std::auto_ptr ractive (l2n.make_layer (active, "active")); + std::auto_ptr rpplus (l2n.make_layer (pplus, "pplus")); + std::auto_ptr rnplus (l2n.make_layer (nplus, "nplus")); + std::auto_ptr rpoly (l2n.make_polygon_layer (poly, "poly")); + std::auto_ptr rpoly_lbl (l2n.make_text_layer (poly_lbl, "poly_lbl")); + std::auto_ptr rdiff_cont (l2n.make_polygon_layer (diff_cont, "diff_cont")); + std::auto_ptr rpoly_cont (l2n.make_polygon_layer (poly_cont, "poly_cont")); + std::auto_ptr rmetal1 (l2n.make_polygon_layer (metal1, "metal1")); + std::auto_ptr rmetal1_lbl (l2n.make_text_layer (metal1_lbl, "metal1_lbl")); + std::auto_ptr rvia1 (l2n.make_polygon_layer (via1, "via1")); + std::auto_ptr rmetal2 (l2n.make_polygon_layer (metal2, "metal2")); + std::auto_ptr rmetal2_lbl (l2n.make_text_layer (metal2_lbl, "metal2_lbl")); + + // derived regions + + db::Region ractive_in_nwell = *ractive & *rnwell; + db::Region rpactive = ractive_in_nwell & *rpplus; + db::Region rntie = ractive_in_nwell & *rnplus; + db::Region rpgate = rpactive & *rpoly; + db::Region rpsd = rpactive - rpgate; + + db::Region ractive_outside_nwell = *ractive - *rnwell; + db::Region rnactive = ractive_outside_nwell & *rnplus; + db::Region rptie = ractive_outside_nwell & *rpplus; + db::Region rngate = rnactive & *rpoly; + db::Region rnsd = rnactive - rngate; + + // return the computed layers into the original layout and write it for debugging purposes + + unsigned int lgate = ly.insert_layer (db::LayerProperties (20, 0)); // 20/0 -> Gate + unsigned int lsd = ly.insert_layer (db::LayerProperties (21, 0)); // 21/0 -> Source/Drain + unsigned int lpdiff = ly.insert_layer (db::LayerProperties (22, 0)); // 22/0 -> P Diffusion + unsigned int lndiff = ly.insert_layer (db::LayerProperties (23, 0)); // 23/0 -> N Diffusion + unsigned int lptie = ly.insert_layer (db::LayerProperties (24, 0)); // 24/0 -> P Tie + unsigned int lntie = ly.insert_layer (db::LayerProperties (25, 0)); // 25/0 -> N Tie + + rpgate.insert_into (&ly, tc.cell_index (), lgate); + rngate.insert_into (&ly, tc.cell_index (), lgate); + rpsd.insert_into (&ly, tc.cell_index (), lsd); + rnsd.insert_into (&ly, tc.cell_index (), lsd); + rpsd.insert_into (&ly, tc.cell_index (), lpdiff); + rnsd.insert_into (&ly, tc.cell_index (), lndiff); + rpsd.insert_into (&ly, tc.cell_index (), lptie); + rnsd.insert_into (&ly, tc.cell_index (), lntie); + + db::NetlistDeviceExtractorMOS4Transistor pmos_ex ("PMOS"); + db::NetlistDeviceExtractorMOS4Transistor nmos_ex ("NMOS"); + + // device extraction + + db::NetlistDeviceExtractor::input_layers dl; + + dl["SD"] = &rpsd; + dl["G"] = &rpgate; + dl["P"] = rpoly.get (); // not needed for extraction but to return terminal shapes + dl["W"] = rnwell.get (); + l2n.extract_devices (pmos_ex, dl); + + dl["SD"] = &rnsd; + dl["G"] = &rngate; + dl["P"] = rpoly.get (); // not needed for extraction but to return terminal shapes + dl["W"] = rbulk.get (); + l2n.extract_devices (nmos_ex, dl); + + // net extraction + + l2n.register_layer (rpsd, "psd"); + l2n.register_layer (rnsd, "nsd"); + l2n.register_layer (rptie, "ptie"); + l2n.register_layer (rntie, "ntie"); + + // Intra-layer + l2n.connect (rpsd); + l2n.connect (rnsd); + l2n.connect (*rnwell); + l2n.connect (*rpoly); + l2n.connect (*rdiff_cont); + l2n.connect (*rpoly_cont); + l2n.connect (*rmetal1); + l2n.connect (*rvia1); + l2n.connect (*rmetal2); + l2n.connect (rptie); + l2n.connect (rntie); + // Inter-layer + l2n.connect (rpsd, *rdiff_cont); + l2n.connect (rnsd, *rdiff_cont); + l2n.connect (*rpoly, *rpoly_cont); + l2n.connect (*rpoly_cont, *rmetal1); + l2n.connect (*rdiff_cont, *rmetal1); + l2n.connect (*rdiff_cont, rptie); + l2n.connect (*rdiff_cont, rntie); + l2n.connect (*rnwell, rntie); + l2n.connect (*rmetal1, *rvia1); + l2n.connect (*rvia1, *rmetal2); + l2n.connect (*rpoly, *rpoly_lbl); // attaches labels + l2n.connect (*rmetal1, *rmetal1_lbl); // attaches labels + l2n.connect (*rmetal2, *rmetal2_lbl); // attaches labels + // Global + l2n.connect_global (rptie, "BULK"); + l2n.connect_global (*rbulk, "BULK"); + + // create some mess - we have to keep references to the layers to make them not disappear + rmetal1_lbl.reset (0); + rmetal2_lbl.reset (0); + rpoly_lbl.reset (0); + + l2n.extract_netlist (); + + l2n.netlist ()->flatten_circuit (l2n.netlist ()->circuit_by_name ("INV2")); + l2n.netlist ()->flatten_circuit (l2n.netlist ()->circuit_by_name ("INV2PAIR")); + l2n.netlist ()->flatten_circuit (l2n.netlist ()->circuit_by_name ("TRANS")); + + // debug layers produced for nets + // 201/0 -> Well + // 203/0 -> Poly + // 204/0 -> Diffusion contacts + // 205/0 -> Poly contacts + // 206/0 -> Metal1 + // 207/0 -> Via1 + // 208/0 -> Metal2 + // 210/0 -> N source/drain + // 211/0 -> P source/drain + // 212/0 -> N tie + // 213/0 -> P tie + std::map dump_map; + dump_map [&rpsd ] = ly.insert_layer (db::LayerProperties (210, 0)); + dump_map [&rnsd ] = ly.insert_layer (db::LayerProperties (211, 0)); + dump_map [&rptie ] = ly.insert_layer (db::LayerProperties (212, 0)); + dump_map [&rntie ] = ly.insert_layer (db::LayerProperties (213, 0)); + dump_map [rbulk.get () ] = ly.insert_layer (db::LayerProperties (214, 0)); + dump_map [rnwell.get () ] = ly.insert_layer (db::LayerProperties (201, 0)); + dump_map [rpoly.get () ] = ly.insert_layer (db::LayerProperties (203, 0)); + dump_map [rdiff_cont.get ()] = ly.insert_layer (db::LayerProperties (204, 0)); + dump_map [rpoly_cont.get ()] = ly.insert_layer (db::LayerProperties (205, 0)); + dump_map [rmetal1.get () ] = ly.insert_layer (db::LayerProperties (206, 0)); + dump_map [rvia1.get () ] = ly.insert_layer (db::LayerProperties (207, 0)); + dump_map [rmetal2.get () ] = ly.insert_layer (db::LayerProperties (208, 0)); + + // write nets to layout + db::CellMapping cm = l2n.cell_mapping_into (ly, tc); + dump_nets_to_layout (l2n, ly, dump_map, cm); + + dump_map.clear (); + dump_map [&rpsd ] = ly.insert_layer (db::LayerProperties (310, 0)); + dump_map [&rnsd ] = ly.insert_layer (db::LayerProperties (311, 0)); + dump_map [&rptie ] = ly.insert_layer (db::LayerProperties (312, 0)); + dump_map [&rntie ] = ly.insert_layer (db::LayerProperties (313, 0)); + dump_map [rbulk.get () ] = ly.insert_layer (db::LayerProperties (314, 0)); + dump_map [rnwell.get () ] = ly.insert_layer (db::LayerProperties (301, 0)); + dump_map [rpoly.get () ] = ly.insert_layer (db::LayerProperties (303, 0)); + dump_map [rdiff_cont.get ()] = ly.insert_layer (db::LayerProperties (304, 0)); + dump_map [rpoly_cont.get ()] = ly.insert_layer (db::LayerProperties (305, 0)); + dump_map [rmetal1.get () ] = ly.insert_layer (db::LayerProperties (306, 0)); + dump_map [rvia1.get () ] = ly.insert_layer (db::LayerProperties (307, 0)); + dump_map [rmetal2.get () ] = ly.insert_layer (db::LayerProperties (308, 0)); + + dump_recursive_nets_to_layout (l2n, ly, dump_map, cm); + + // compare netlist as string + CHECKPOINT (); + db::compare_netlist (_this, *l2n.netlist (), + "circuit RINGO ();\n" + " device PMOS $1 (S=FB,G=$I7,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $2 (S=VDD,G=$I7,D=FB,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $3 (S=FB,G=$I7,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $4 (S=VSS,G=$I7,D=FB,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $5 (S=OSC,G=FB,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $6 (S=VDD,G=FB,D=OSC,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $7 (S=OSC,G=FB,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $8 (S=VSS,G=FB,D=OSC,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $9 (S=$I22,G=FB,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $10 (S=VDD,G=FB,D=$I22,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $11 (S=$I22,G=FB,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $12 (S=VSS,G=FB,D=$I22,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $13 (S=$I13,G=$I22,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $14 (S=VDD,G=$I22,D=$I13,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $15 (S=$I13,G=$I22,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $16 (S=VSS,G=$I22,D=$I13,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $17 (S=$I23,G=$I13,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $18 (S=VDD,G=$I13,D=$I23,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $19 (S=$I23,G=$I13,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $20 (S=VSS,G=$I13,D=$I23,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $21 (S=$I5,G=$I23,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $22 (S=VDD,G=$I23,D=$I5,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $23 (S=$I5,G=$I23,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $24 (S=VSS,G=$I23,D=$I5,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $25 (S=$I24,G=$I5,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $26 (S=VDD,G=$I5,D=$I24,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $27 (S=$I24,G=$I5,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $28 (S=VSS,G=$I5,D=$I24,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $29 (S=$I6,G=$I24,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $30 (S=VDD,G=$I24,D=$I6,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $31 (S=$I6,G=$I24,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $32 (S=VSS,G=$I24,D=$I6,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $33 (S=$I25,G=$I6,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $34 (S=VDD,G=$I6,D=$I25,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $35 (S=$I25,G=$I6,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $36 (S=VSS,G=$I6,D=$I25,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device PMOS $37 (S=$I7,G=$I25,D=VDD,B=VDD) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device PMOS $38 (S=VDD,G=$I25,D=$I7,B=VDD) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + " device NMOS $39 (S=$I7,G=$I25,D=VSS,B=VSS) (L=0.25,W=1.75,AS=0.91875,AD=0.48125,PS=4.55,PD=2.3);\n" + " device NMOS $40 (S=VSS,G=$I25,D=$I7,B=VSS) (L=0.25,W=1.75,AS=0.48125,AD=0.91875,PS=2.3,PD=4.55);\n" + "end;\n" + ); + + // compare the collected test data + + std::string au = tl::testsrc (); + au = tl::combine_path (au, "testdata"); + au = tl::combine_path (au, "algo"); + au = tl::combine_path (au, "device_extract_au5_flattened_circuits.gds"); + + db::compare_layouts (_this, ly, au); +} + diff --git a/src/db/unit_tests/dbNetlistCompareTests.cc b/src/db/unit_tests/dbNetlistCompareTests.cc index d01980573..60267320e 100644 --- a/src/db/unit_tests/dbNetlistCompareTests.cc +++ b/src/db/unit_tests/dbNetlistCompareTests.cc @@ -586,8 +586,8 @@ TEST(1_SimpleInverterSkippedDevices) "match_pins $3 $2\n" "match_devices $3 $1\n" "match_devices_with_different_parameters $2 $2\n" - "device_mismatch (null) $3\n" "match_devices $1 $4\n" + "device_mismatch (null) $3\n" "end_circuit INV INV NOMATCH" ); EXPECT_EQ (good, false); @@ -622,8 +622,8 @@ TEST(1_SimpleInverterSkippedDevices) " terminal $3[S]:$1[D]\n" " pin $3:$2\n" " device (null):$3 [Mismatch]\n" - " device $3:$1 [Match]\n" " device $2:$2 [MatchWithWarning]\n" + " device $3:$1 [Match]\n" " device $1:$4 [Match]\n" ); EXPECT_EQ (good, false); @@ -1283,13 +1283,13 @@ TEST(6_BufferTwoPathsAdditionalDevices) "match_pins $3 $2\n" "match_devices $5 $1\n" "match_devices $7 $2\n" - "device_mismatch (null) $3\n" "match_devices $1 $4\n" "match_devices $3 $5\n" "match_devices $6 $6\n" "match_devices $8 $7\n" "match_devices $2 $8\n" "match_devices $4 $9\n" + "device_mismatch (null) $3\n" "device_mismatch $9 (null)\n" "end_circuit BUF BUF NOMATCH" ); @@ -1414,8 +1414,8 @@ TEST(7_ResistorsPlusOneDevice) "match_pins $2 $2\n" "match_devices $1 $1\n" "match_devices $3 $2\n" - "device_mismatch (null) $3\n" "match_devices $2 $4\n" + "device_mismatch (null) $3\n" "end_circuit TRIANGLE TRIANGLE NOMATCH" ); EXPECT_EQ (good, false); @@ -1496,9 +1496,8 @@ TEST(8_DiodesDontMatchOnSwappedPins) "match_pins $1 $0\n" "match_pins $2 $1\n" "match_devices $1 $1\n" - "device_mismatch (null) $2\n" "match_devices $3 $3\n" - "device_mismatch $2 (null)\n" + "device_mismatch $2 $2\n" "end_circuit TRIANGLE TRIANGLE NOMATCH" ); EXPECT_EQ (good, false); @@ -1676,8 +1675,7 @@ TEST(11_MismatchingSubcircuits) "match_pins $2 $0\n" "match_pins $3 $2\n" "match_devices $2 $1\n" - "device_mismatch (null) $2\n" - "device_mismatch $1 (null)\n" + "device_mismatch $1 $2\n" "end_circuit INV INV NOMATCH\n" "begin_circuit TOP TOP\n" "match_nets OUT OUT\n" @@ -1709,13 +1707,11 @@ TEST(11_MismatchingSubcircuits) " pin $3:$2 [Match]\n" " net IN:IN [Mismatch]\n" " terminal (null):$2[S]\n" - " terminal (null):$2[G]\n" - " terminal $1[G]:(null)\n" + " terminal $1[G]:$2[G]\n" " terminal $2[G]:$1[G]\n" " pin $0:$1\n" " net OUT:OUT [Mismatch]\n" - " terminal (null):$2[D]\n" - " terminal $1[D]:(null)\n" + " terminal $1[D]:$2[D]\n" " terminal $2[D]:$1[S]\n" " pin $1:$3\n" " net VDD:VDD [Mismatch]\n" @@ -1724,9 +1720,8 @@ TEST(11_MismatchingSubcircuits) " net VSS:VSS [Match]\n" " terminal $2[S]:$1[D]\n" " pin $3:$2\n" - " device (null):$2 [Mismatch]\n" - " device $1:(null) [Mismatch]\n" " device $2:$1 [Match]\n" + " device $1:$2 [Mismatch]\n" "TOP:TOP [Match]:\n" " pin $0:$2 [Match]\n" " pin $1:$0 [Match]\n" @@ -2106,10 +2101,10 @@ TEST(14_Subcircuit2NandMismatchNoSwap) " net VSS:VSS [Match]\n" " terminal $3[S]:$3[S]\n" " pin $4:$4\n" - " device $1:$1 [Match]\n" - " device $2:$2 [Match]\n" " device $3:$3 [Match]\n" " device $4:$4 [Match]\n" + " device $1:$1 [Match]\n" + " device $2:$2 [Match]\n" "TOP:TOP [NoMatch]:\n" " pin (null):$0 [Mismatch]\n" " pin $0:(null) [Mismatch]\n" diff --git a/src/db/unit_tests/dbNetlistExtractorTests.cc b/src/db/unit_tests/dbNetlistExtractorTests.cc index 7bc49b804..e841c2cb8 100644 --- a/src/db/unit_tests/dbNetlistExtractorTests.cc +++ b/src/db/unit_tests/dbNetlistExtractorTests.cc @@ -1066,10 +1066,11 @@ TEST(4_ResAndCapExtraction) " device PMOS $2 (S=VDD,G=IN,D=$3) (L=0.4,W=2.3,AS=1.38,AD=1.38,PS=5.8,PD=5.8);\n" " device NMOS $3 (S=VSS,G=$4,D=OUT) (L=0.4,W=4.6,AS=2.185,AD=2.185,PS=8.8,PD=8.8);\n" " device MIM_CAP $5 (A=$4,B=VSS) (C=2.622e-14,A=26.22,P=29.8);\n" - " device POLY_RES $7 (A=$3,B=$4) (R=750,A=2.4,P=13.6);\n" - " device POLY_RES $9 (A=$4,B=VSS) (R=1825,A=5.84,P=30);\n" + " device POLY_RES $7 (A=$3,B=$4) (R=750,L=12,W=0.8,A=2.4,P=13.6);\n" + " device POLY_RES $9 (A=$4,B=VSS) (R=1825,L=29.2,W=0.8,A=5.84,P=30);\n" " device NMOS $10 (S=VSS,G=IN,D=$3) (L=0.4,W=3.1,AS=1.86,AD=1.86,PS=7.4,PD=7.4);\n" - "end;\n" + "end;\n", + true /*exact parameter compare*/ ); // compare the collected test data @@ -1339,10 +1340,11 @@ TEST(5_ResAndCapWithBulkExtraction) " device NMOS $3 (S=VSS,G=$4,D=OUT,B=BULK) (L=0.4,W=4.6,AS=2.185,AD=2.185,PS=8.8,PD=8.8);\n" " device MIM_CAP_SUBSTRATE $5 (A=$4,B=VSS,W=BULK) (C=1.334e-14,A=13.34,P=15);\n" " device MIM_CAP_NWELL $6 (A=$4,B=VSS,W=NWELL) (C=1.288e-14,A=12.88,P=14.8);\n" - " device POLY_RES_NWELL $7 (A=$3,B=$4,W=NWELL) (R=750,A=2.4,P=13.6);\n" - " device POLY_RES_SUBSTRATE $9 (A=$4,B=VSS,W=BULK) (R=1825,A=5.84,P=30);\n" + " device POLY_RES_NWELL $7 (A=$3,B=$4,W=NWELL) (R=750,L=12,W=0.8,A=2.4,P=13.6);\n" + " device POLY_RES_SUBSTRATE $9 (A=$4,B=VSS,W=BULK) (R=1825,L=29.2,W=0.8,A=5.84,P=30);\n" " device NMOS $10 (S=VSS,G=IN,D=$3,B=BULK) (L=0.4,W=3.1,AS=1.86,AD=1.86,PS=7.4,PD=7.4);\n" - "end;\n" + "end;\n", + true /*exact parameter compare*/ ); // compare the collected test data @@ -1582,9 +1584,10 @@ TEST(6_BJT3TransistorExtraction) " device PMOS $3 (S=VDD,G=IN,D=$3,B=VDD) (L=0.4,W=2.3,AS=1.38,AD=1.38,PS=5.8,PD=5.8);\n" " device NMOS $4 (S=VSS,G=$4,D=OUT,B=BULK) (L=0.4,W=4.6,AS=2.185,AD=2.185,PS=8.8,PD=8.8);\n" " device PNP $6 (C=BULK,B=$3,E=$3) (AE=3.06,PE=7,AB=25.2,PB=21.2,AC=25.2,PC=21.2,NE=1);\n" - " device PNP $7 (C=BULK,B=$3,E=$4) (AE=6.12,PE=14,AB=50.4,PB=42.4,AC=50.4,PC=42.4,NE=2);\n" + " device PNP $7 (C=BULK,B=$3,E=$4) (AE=6.12,PE=14,AB=25.2,PB=21.2,AC=25.2,PC=21.2,NE=2);\n" " device NMOS $9 (S=VSS,G=IN,D=$3,B=BULK) (L=0.4,W=3.1,AS=1.86,AD=1.86,PS=7.4,PD=7.4);\n" - "end;\n" + "end;\n", + true /*exact parameter compare*/ ); // compare the collected test data @@ -1716,7 +1719,140 @@ TEST(7_DiodeExtraction) db::compare_netlist (_this, nl, "circuit TOP (A=A,C=C);\n" " device DIODE $1 (A=A,C=C) (A=9.18,P=21);\n" - "end;\n" + "end;\n", + true /*exact parameter compare*/ + ); + + // compare the collected test data + + std::string au = tl::testsrc (); + au = tl::combine_path (au, "testdata"); + au = tl::combine_path (au, "algo"); + au = tl::combine_path (au, "diode_devices_nets.gds"); + + db::compare_layouts (_this, ly, au); +} + +TEST(8_DiodeExtractionScaled) +{ + db::Layout ly; + db::LayerMap lmap; + + unsigned int nwell = define_layer (ly, lmap, 1); + unsigned int active = define_layer (ly, lmap, 2); + unsigned int diff_cont = define_layer (ly, lmap, 4); + unsigned int metal1 = define_layer (ly, lmap, 6); + unsigned int metal1_lbl = define_layer (ly, lmap, 6, 1); + unsigned int pplus = define_layer (ly, lmap, 9); + unsigned int nplus = define_layer (ly, lmap, 10); + + { + db::LoadLayoutOptions options; + options.get_options ().layer_map = lmap; + options.get_options ().create_other_layers = false; + + std::string fn (tl::testsrc ()); + fn = tl::combine_path (fn, "testdata"); + fn = tl::combine_path (fn, "algo"); + fn = tl::combine_path (fn, "diode_devices_test.oas"); + + tl::InputStream stream (fn); + db::Reader reader (stream); + reader.read (ly, options); + } + + db::Cell &tc = ly.cell (*ly.begin_top_down ()); + + db::DeepShapeStore dss; + dss.set_text_enlargement (1); + dss.set_text_property_name (tl::Variant ("LABEL")); + + // original layers + db::Region rnwell (db::RecursiveShapeIterator (ly, tc, nwell), dss); + db::Region ractive (db::RecursiveShapeIterator (ly, tc, active), dss); + db::Region rdiff_cont (db::RecursiveShapeIterator (ly, tc, diff_cont), dss); + db::Region rmetal1 (db::RecursiveShapeIterator (ly, tc, metal1), dss); + db::Region rmetal1_lbl (db::RecursiveShapeIterator (ly, tc, metal1_lbl), dss); + db::Region rpplus (db::RecursiveShapeIterator (ly, tc, pplus), dss); + db::Region rnplus (db::RecursiveShapeIterator (ly, tc, nplus), dss); + + // derived regions + + db::Region rn = ractive & rnwell; + db::Region rntie = rnwell & rnplus; + + // return the computed layers into the original layout and write it for debugging purposes + + unsigned int ln = ly.insert_layer (db::LayerProperties (10, 0)); // 10/0 -> N layer + unsigned int lntie = ly.insert_layer (db::LayerProperties (11, 0)); // 11/0 -> N contact + rn.insert_into (&ly, tc.cell_index (), ln); + rntie.insert_into (&ly, tc.cell_index (), lntie); + + // perform the extraction + + db::Netlist nl; + db::hier_clusters cl; + + db::NetlistDeviceExtractorDiode diode_ex ("DIODE"); + + db::NetlistDeviceExtractor::input_layers dl; + + dl["N"] = &rn; + dl["P"] = &rpplus; + dl["tC"] = &rnwell; + diode_ex.extract (dss, 0, dl, nl, cl, 2.0); + + // perform the net extraction + + db::NetlistExtractor net_ex; + + db::Connectivity conn; + // Intra-layer + conn.connect (rnwell); + conn.connect (rntie); + conn.connect (rpplus); + conn.connect (rdiff_cont); + conn.connect (rmetal1); + // Inter-layer + conn.connect (rntie, rnwell); + conn.connect (rntie, rdiff_cont); + conn.connect (rpplus, rdiff_cont); + conn.connect (rdiff_cont, rmetal1); + conn.connect (rmetal1, rmetal1_lbl); // attaches labels + + // extract the nets + + net_ex.extract_nets (dss, 0, conn, nl, cl, "*"); + + // cleanup + completion + nl.combine_devices (); + nl.make_top_level_pins (); + nl.purge (); + + EXPECT_EQ (all_net_names_unique (nl), true); + + // debug layers produced for nets + // 201/0 -> n well + // 204/0 -> Diffusion contacts + // 206/0 -> Metal1 + // 210/0 -> N tiedown + std::map dump_map; + dump_map [layer_of (rntie) ] = ly.insert_layer (db::LayerProperties (210, 0)); + dump_map [layer_of (rnwell) ] = ly.insert_layer (db::LayerProperties (201, 0)); + dump_map [layer_of (rdiff_cont)] = ly.insert_layer (db::LayerProperties (204, 0)); + dump_map [layer_of (rmetal1) ] = ly.insert_layer (db::LayerProperties (206, 0)); + + // write nets to layout + db::CellMapping cm = dss.cell_mapping_to_original (0, &ly, tc.cell_index ()); + dump_nets_to_layout (nl, cl, ly, dump_map, cm, true /*with device cells*/); + + // compare netlist as string + CHECKPOINT (); + db::compare_netlist (_this, nl, + "circuit TOP (A=A,C=C);\n" + " device DIODE $1 (A=A,C=C) (A=36.72,P=42);\n" + "end;\n", + true /*exact parameter compare*/ ); // compare the collected test data diff --git a/src/db/unit_tests/dbNetlistReaderTests.cc b/src/db/unit_tests/dbNetlistReaderTests.cc index 8683d27d6..c39e477a6 100644 --- a/src/db/unit_tests/dbNetlistReaderTests.cc +++ b/src/db/unit_tests/dbNetlistReaderTests.cc @@ -255,3 +255,42 @@ TEST(6_ReaderWithDelegate) "end;\n" ); } + +TEST(7_GlobalNets) +{ + db::Netlist nl; + + std::string path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nreader7.cir"); + + MyNetlistReaderDelegate delegate; + db::NetlistSpiceReader reader (&delegate); + tl::InputStream is (path); + reader.read (is, nl); + + EXPECT_EQ (nl.to_string (), + "circuit RINGO (FB=FB,OUT=OUT,ENABLE=ENABLE,VDD=VDD,VSS=VSS);\n" + " subcircuit ND2X1 $1 (OUT='1',B=FB,A=ENABLE,VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $2 (OUT='2',IN='1',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $3 (OUT='3',IN='2',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $4 (OUT='4',IN='3',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $5 (OUT='5',IN='4',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $6 (OUT='6',IN='5',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $7 (OUT='7',IN='6',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $8 (OUT='8',IN='7',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $9 (OUT='9',IN='8',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $10 (OUT='10',IN='9',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $11 (OUT=FB,IN='10',VDD=VDD,VSS=VSS);\n" + " subcircuit INVX1 $12 (OUT=OUT,IN=FB,VDD=VDD,VSS=VSS);\n" + "end;\n" + "circuit ND2X1 (OUT=OUT,B=B,A=A,VDD=VDD,VSS=VSS);\n" + " device MLVPMOS $1 (S=OUT,G=A,D=VDD,B=VDD) (L=0.25,W=1.5,AS=0.6375,AD=0.3375,PS=3.85,PD=1.95);\n" + " device MLVPMOS $2 (S=VDD,G=B,D=OUT,B=VDD) (L=0.25,W=1.5,AS=0.3375,AD=0.6375,PS=1.95,PD=3.85);\n" + " device MLVNMOS $3 (S=VSS,G=A,D=INT,B=VSS) (L=0.25,W=0.95,AS=0.40375,AD=0.21375,PS=2.75,PD=1.4);\n" + " device MLVNMOS $4 (S=INT,G=B,D=OUT,B=VSS) (L=0.25,W=0.95,AS=0.21375,AD=0.40375,PS=1.4,PD=2.75);\n" + "end;\n" + "circuit INVX1 (OUT=OUT,IN=IN,VDD=VDD,VSS=VSS);\n" + " device MLVPMOS $1 (S=VDD,G=IN,D=OUT,B=VDD) (L=0.25,W=1.5,AS=0.6375,AD=0.6375,PS=3.85,PD=3.85);\n" + " device MLVNMOS $2 (S=VSS,G=IN,D=OUT,B=VSS) (L=0.25,W=0.95,AS=0.40375,AD=0.40375,PS=2.75,PD=2.75);\n" + "end;\n" + ); +} diff --git a/src/drc/drc/built-in-macros/_drc_engine.rb b/src/drc/drc/built-in-macros/_drc_engine.rb index 81de7f124..9ffaf7d79 100644 --- a/src/drc/drc/built-in-macros/_drc_engine.rb +++ b/src/drc/drc/built-in-macros/_drc_engine.rb @@ -1159,6 +1159,12 @@ CODE # @synopsis l2n_data # See \Netter#l2n_data for a description of that function. + # %DRC% + # @name device_scaling + # @brief Specifies a dimension scale factor for the geometrical device properties + # @synopsis device_scaling(factor) + # See \Netter#device_scaling for a description of that function. + # %DRC% # @name extract_devices # @brief Extracts devices for a given device extractor and device layer selection @@ -1173,7 +1179,7 @@ CODE # yet, this method will trigger the extraction process. # See \Netter#netlist for a description of this function. - %w(connect connect_global clear_connections connect_implicit antenna_check l2n_data extract_devices netlist).each do |f| + %w(connect connect_global clear_connections connect_implicit antenna_check l2n_data device_scaling extract_devices netlist).each do |f| eval <<"CODE" def #{f}(*args) _netter.#{f}(*args) diff --git a/src/drc/drc/built-in-macros/_drc_netter.rb b/src/drc/drc/built-in-macros/_drc_netter.rb index 9d4712261..400acd91b 100644 --- a/src/drc/drc/built-in-macros/_drc_netter.rb +++ b/src/drc/drc/built-in-macros/_drc_netter.rb @@ -68,6 +68,7 @@ module DRC @connect_implicit = [] @l2n = nil @lnum = 0 + @device_scaling = 1.0 end # %DRC% @@ -169,7 +170,8 @@ module DRC layer_selection.is_a?(Hash) || raise("Second argument of Netter#extract_devices must be a hash") ls = {} - layer_selection.each do |n,l| + layer_selection.keys.sort.each do |n| + l = layer_selection[n] l.requires_region("Netter#extract_devices (#{n} layer)") register_layer(l.data) ls[n.to_s] = l.data @@ -178,6 +180,19 @@ module DRC @engine._cmd(@l2n, :extract_devices, devex, ls) end + + # %DRC% + # @name device_scaling + # @brief Specifies a dimension scale factor for the geometrical device properties + # @synopsis device_scaling(factor) + # Specifying a factor of 2 will make all devices being extracted as if the + # geometries were two times larger. This feature is useful when the drawn layout + # does not correspond to the physical dimensions. + + def device_scaling(factor) + @device_scaling = factor + @l2n && @l2n.device_scaling = factor + end # %DRC% # @name clear_connections @@ -378,6 +393,7 @@ module DRC if !@l2n @layers = {} _make_data + @l2n.device_scaling = @device_scaling end end diff --git a/src/lay/lay/doc/about/drc_ref_global.xml b/src/lay/lay/doc/about/drc_ref_global.xml index 2521e3296..0b3b3b2a6 100644 --- a/src/lay/lay/doc/about/drc_ref_global.xml +++ b/src/lay/lay/doc/about/drc_ref_global.xml @@ -29,7 +29,7 @@ See Netter#antenna_check f
  • bjt3(name)

    • -Use this class with device_extract to specify extraction of a +Use this class with extract_devices to specify extraction of a bipolar junction transistor

    "bjt4" - Supplies the BJT4 transistor extractor class

    @@ -39,7 +39,7 @@ bipolar junction transistor
  • bjt4(name)

    • -Use this class with device_extract to specify extraction of a +Use this class with extract_devices to specify extraction of a bipolar junction transistor with a substrate terminal

    "box" - Creates a box object

    @@ -59,17 +59,17 @@ This function creates a box object. The arguments are the same than for the
  • capacitor(name, area_cap)

    • -Use this class with device_extract to specify extraction of a capacitor. +Use this class with extract_devices to specify extraction of a capacitor. The area_cap argument is the capacitance in Farad per square micrometer.

    "capacitor_with_bulk" - Supplies the capacitor extractor class that includes a bulk terminal

    Usage:

      -
    • capacitor_with_bulk(name)
      • +
    • capacitor_with_bulk(name, area_cap)

    -Use this class with device_extract to specify extraction of a capacitor +Use this class with extract_devices to specify extraction of a capacitor with a bulk terminal. The area_cap argument is the capacitance in Farad per square micrometer.

    @@ -185,6 +185,15 @@ implied always. Sometimes cell variants will be created.

    Deep mode can be cancelled with tiles or flat.

    +

    "device_scaling" - Specifies a dimension scale factor for the geometrical device properties

    + +

    Usage:

    +
      +
    • device_scaling(factor)
      • +
    +

    +See Netter#device_scaling for a description of that function. +

    "diode" - Supplies the diode extractor class

    Usage:

    @@ -192,7 +201,7 @@ Deep mode can be cancelled with     tiles or fl
  • diode(name)

    • -Use this class with device_extract to specify extraction of a +Use this class with extract_devices to specify extraction of a planar diode

    "edge" - Creates an edge object

    @@ -396,7 +405,7 @@ filled with Layer#insert.
  • mos3(name)

    • -Use this class with device_extract to specify extraction of a +Use this class with extract_devices to specify extraction of a three-terminal MOS transistor

    "mos4" - Supplies the MOS4 transistor extractor class

    @@ -406,7 +415,7 @@ three-terminal MOS transistor
  • mos4(name)

    • -Use this class with device_extract to specify extraction of a +Use this class with extract_devices to specify extraction of a four-terminal MOS transistor

    "netlist" - Obtains the extracted netlist from the default Netter

    @@ -537,7 +546,7 @@ third parameter.

    Usage:

      -
    • report_netlist([ filename ])
      • +
    • report_netlist([ filename [, long ] ])

    This method applies to runsets creating a netlist through @@ -547,6 +556,8 @@ netlist plus the net and device shapes are turned into a layout-to-netlist report (L2N database) and shown in the netlist browser window. If a file name is given, the report will also be written to the given file. +If a file name is given and "long" is true, a verbose +version of the L2N DB format will be used.

    "resistor" - Supplies the resistor extractor class

    @@ -555,17 +566,17 @@ will also be written to the given file.
  • resistor(name, sheet_rho)

    • -Use this class with device_extract to specify extraction of a resistor. +Use this class with extract_devices to specify extraction of a resistor. The sheet_rho value is the sheet resistance in ohms/square.

    "resistor_with_bulk" - Supplies the resistor extractor class that includes a bulk terminal

    Usage:

      -
    • resistor_with_bulk(name)
      • +
    • resistor_with_bulk(name, sheet_rho)

    -Use this class with device_extract to specify extraction of a resistor +Use this class with extract_devices to specify extraction of a resistor with a bulk terminal. The sheet_rho value is the sheet resistance in ohms/square.

    diff --git a/src/lay/lay/doc/about/drc_ref_netter.xml b/src/lay/lay/doc/about/drc_ref_netter.xml index 1fa008d21..a131bad28 100644 --- a/src/lay/lay/doc/about/drc_ref_netter.xml +++ b/src/lay/lay/doc/about/drc_ref_netter.xml @@ -186,23 +186,29 @@ to shapes belonging to tie-down diodes.
  • connect_implicit(label_pattern)

    • -Use this method to supply a glob pattern for labels which create implicit net connections +Use this method to supply label strings which create implicit net connections on the top level circuit. This feature is useful to connect identically labelled nets -while a component isn't integrated yet. If the component is integrated, net may be connected +while a component isn't integrated yet. If the component is integrated, nets may be connected on a higher hierarchy level - e.g. by a power mesh. Inside the component this net consists of individual islands. To properly perform netlist extraction and comparison, these islands need to be connected even though there isn't a physical connection. "connect_implicit" can achive this if these islands are labelled with the same text on the top level of the component.

    -Glob pattern are used which resemble shell file pattern: "*" is for all labels, "VDD" -for all "VDD" labels (pattern act case sensitive). "VDD*" is for all labels beginning -with "VDD" (still different labels will be connected to different nets!). "{VDD,VSS}" -is either "VDD" or "VSS". -

    -The search pattern is applied on the next net extraction. The search pattern is cleared +The implicit connections are applied on the next net extraction and cleared on "clear_connections".

    +

    "device_scaling" - Specifies a dimension scale factor for the geometrical device properties

    + +

    Usage:

    +
      +
    • device_scaling(factor)
      • +
    +

    +Specifying a factor of 2 will make all devices being extracted as if the +geometries were two times larger. This feature is useful when the drawn layout +does not correspond to the physical dimensions. +

    "extract_devices" - Extracts devices based on the given extractor class, name and device layer selection

    Usage:

    diff --git a/src/lay/lay/doc/about/lvs_ref_global.xml b/src/lay/lay/doc/about/lvs_ref_global.xml index d99c2fb74..4ea1fa4fb 100644 --- a/src/lay/lay/doc/about/lvs_ref_global.xml +++ b/src/lay/lay/doc/about/lvs_ref_global.xml @@ -19,6 +19,15 @@ layers or specification of the layout source. For more details about the DRC functions see     DRC::global.

    +

    "align" - Aligns the extracted netlist vs. the schematic by flattening circuits where required

    + +

    Usage:

    +
      +
    • align
      • +
    +

    +See Netter#align for a description of that function. +

    "compare" - Compares the extracted netlist vs. the schematic

    Usage:

    @@ -37,6 +46,24 @@ See     Netter#compare for a descrip

    See Netter#equivalent_pins for a description of that function.

    +

    "max_branch_complexity" - Configures the maximum branch complexity for ambiguous net matching

    + +

    Usage:

    +
      +
    • max_branch_complexity(n)
      • +
    +

    +See Netter#max_branch_complexity for a description of that function. +

    +

    "max_depth" - Configures the maximum search depth for net match deduction

    + +

    Usage:

    +
      +
    • max_depth(n)
      • +
    +

    +See Netter#max_depth for a description of that function. +

    "max_res" - Ignores resistors with a resistance above a certain value

    Usage:

    @@ -68,13 +95,14 @@ See     Netter for more details

    Usage:

      -
    • report_lvs([ filename ])
      • +
    • report_lvs([ filename [, long ] ])

    After the comparison step, the LVS database will be shown in the netlist database browser in a cross-reference view. If a filename is given, the LVS database is also written to -this file. +this file. If a file name is given and "long" is true, a +verbose version of the LVS DB format will be used.

    If this method is called together with report_netlist and two files each, two files can be generated - one for the extracted netlist (L2N database) and one for the diff --git a/src/lay/lay/doc/about/lvs_ref_netter.xml b/src/lay/lay/doc/about/lvs_ref_netter.xml index 98a3cd859..604805c0c 100644 --- a/src/lay/lay/doc/about/lvs_ref_netter.xml +++ b/src/lay/lay/doc/about/lvs_ref_netter.xml @@ -43,6 +43,31 @@ end

    +

    "align" - Aligns the extracted netlist vs. the schematic

    + +

    Usage:

    +
      +
    • align
      • +
    +

    +The align method will modify the netlists in case of missing +corresponding circuits. It will flatten these circuits, thus +improving the equivalence between the netlists. Top level circuits +are not flattened. +

    +This feature is in particular useful to remove structural cells +like device PCells, reuse blocks etc. +

    +This method will also remove schematic circuits for which there is +no corresponding layout cell. In the extreme case of flat layout this +will result in a flat vs. flat compare. +

    +"netlist.flatten_circuit(...)" or "schematic.flatten_circuit(...)" +are other (explicit) ways to flatten circuits. +

    +Please note that flattening circuits has some side effects such +as loss of details in the cross reference and net layout. +

    "compare" - Compares the extracted netlist vs. the schematic

    Usage:

    @@ -54,6 +79,9 @@ Before using this method, a schematic netlist has to be loaded with     same_nets, same_circuits, same_device_classes and equivalent_pins.

    +The compare method will also modify the netlists in case of missing +corresponding circuits: the unpaired circuit will be flattened then. +

    This method will return true, if the netlists are equivalent and false otherwise.

    @@ -61,7 +89,7 @@ otherwise.

    Usage:

      -
    • equivalent_pins(circuit, pins ...)
      • +
    • equivalent_pins(circuit, pin ...)

    This method will mark the given pins as equivalent. This gives the compare algorithm @@ -70,9 +98,15 @@ is used to declare inputs from gates are equivalent where are are logically, but physically (e.g. in a CMOS NAND gate): 

    -netter.equivalent_pins("NAND2", "A", "B")
+netter.equivalent_pins("NAND2", 0, 1)

    +The circuit argument is either a circuit name (a string) or a Circuit object +from the schematic netlist. +

    +The pin arguments are zero-based pin numbers, where 0 is the first number, 1 the second etc. +If the netlist provides named pins, names can be used instead of numbers. +

    Before this method can be used, a schematic netlist needs to be loaded with schematic.

    @@ -86,6 +120,23 @@ Before this method can be used, a schematic netlist needs to be loaded with The LayoutVsSchematic object provides access to the internal details of the netter object.

    +

    "max_depth" - Configures the maximum search depth for net match deduction

    + +

    Usage:

    +
      +
    • max_depth(n)
      • +
    +

    +The netlist compare algorithm works recursively: once a net +equivalence is established, additional matches are derived from +this equivalence. Such equivalences in turn are used to derive +new equivalences and so on. The maximum depth parameter configures +the number of recursions the algorithm performs before picking +the next net. With higher values for the depth, the algorithm +pursues this "deduction path" in greater depth while with +smaller values, the algorithm prefers picking nets in a random fashion +as the seeds for this deduction path. The default value is 8. +

    "max_res" - Ignores resistors with a resistance above a certain value

    Usage:

    @@ -117,6 +168,9 @@ This method will force an equivalence between the two circuits. By default, circuits are identified by name. If names are different, this method allows establishing an explicit correspondence.

    +One of the circuits may be nil. In this case, the corresponding +other circuit is mapped to "nothing", i.e. ignored. +

    Before this method can be used, a schematic netlist needs to be loaded with schematic.

    @@ -132,6 +186,9 @@ Device classes are also known as "models". By default, device classes are identified by name. If names are different, this method allows establishing an explicit correspondence.

    +One of the device classes may be nil. In this case, the corresponding +other device class is mapped to "nothing", i.e. ignored. +

    Before this method can be used, a schematic netlist needs to be loaded with schematic.

    @@ -145,7 +202,11 @@ Before this method can be used, a schematic netlist needs to be loaded with

    This method will force an equivalence between the net_a and net_b from circuit_a and circuit_b (circuit in the three-argument form is for both circuit_a and circuit_b). -Circuit and nets are string giving a circuit and net by name. +

    +In the four-argument form, the circuits can be either given by name or as Circuit +objects. In the three-argument form, the circuit has to be given by name. +Nets can be either given by name or as Net objects. +

    After using this function, the compare algorithm will consider these nets equivalent. Use this method to provide hints for the comparer in cases which are difficult to resolve otherwise. @@ -153,15 +214,19 @@ resolve otherwise. Before this method can be used, a schematic netlist needs to be loaded with schematic.

    -

    "schematic" - Reads the reference netlist

    +

    "schematic" - Gets, sets or reads the reference netlist

    Usage:

    • schematic(filename)
    • schematic(filename, reader)
    • schematic(netlist)
      • +
    • schematic

    +If no argument is given, the current schematic netlist is returned. nil is +returned if no schematic netlist is set yet. +

    If a filename is given (first two forms), the netlist is read from the given file. If no reader is provided, Spice format will be assumed. The reader object is a NetlistReader object and allows detailed customization of the reader process. diff --git a/src/lay/lay/doc/manual/lvs_intro.xml b/src/lay/lay/doc/manual/lvs_intro.xml index 791254eb8..d3278dd8e 100644 --- a/src/lay/lay/doc/manual/lvs_intro.xml +++ b/src/lay/lay/doc/manual/lvs_intro.xml @@ -342,8 +342,7 @@ connect_global(nwell, "NWELL") 

    schematic("inv.cir")

    - And with this we can trigger the compare step (this will implicitly trigger the netlist - extraction from the layout too): + Finally after having set this up, we can trigger the compare step: 

    compare
    @@ -357,7 +356,7 @@ connect_global(nwell, "NWELL") target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")

    - The extracted netlist is pretty much the same than the reference netlist, but + Since we have a LVS match, the extracted netlist is pretty much the same than the reference netlist, but enhanced by some geometrical parameters such as source and drain area and perimeter:

    @@ -390,8 +389,8 @@ M$2 2 1 4 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U Tie-down diodes are contacts over active regions. The active regions are implanted p+ on the substrate and n+ within the n well (the opposite implant type of transistors). With this doping profile, the metal contact won't form - a Schottky barrier to the Silicon bulk and pretty much behave like an ohmic contact - (so in fact, the "diode" isn't a real diode in the sense of a rectifier). + a Schottky barrier to the Silicon bulk and behave like an ohmic contact. + So in fact, the "diode" isn't a real diode in the sense of a rectifier.

    diff --git a/src/lay/lay/doc/manual/lvs_tweaks.xml b/src/lay/lay/doc/manual/lvs_tweaks.xml index 99c2a6d60..997104258 100644 --- a/src/lay/lay/doc/manual/lvs_tweaks.xml +++ b/src/lay/lay/doc/manual/lvs_tweaks.xml @@ -115,6 +115,31 @@ For example, "NMOS*" will flatten all circuits starting with "NMOS".

    +

    Automatic circuit flattening (netlist alignment)

    + +

    + Instead of flattening circuits explicitly, automatic flattening is provided through + the align method. +

    + +

    + The "align" step is optional, hence useful: it will identify cells in the + layout without a corresponding schematic circuit and flatten them. "Flatten" + means their content is replicated inside their parent circuits and finally + the cell's corresponding circuit is removed. This is useful when the layout + contains structural cells: such cells are inserted not because the schematic + requires them as circuit building blocks, but because layout is easier to + create with these cells. Such cells can be PCells for devices or replication cells + which avoid duplicate layout work. +

    + +

    + The "align" method will also flatten schematic circuits for which there is no + layout cell: +

    + + 
    align
    +

    Black boxing (circuit abstraction)

    diff --git a/src/laybasic/laybasic/layNetlistBrowserModel.cc b/src/laybasic/laybasic/layNetlistBrowserModel.cc index 0bb2b2e23..6c7741aef 100644 --- a/src/laybasic/laybasic/layNetlistBrowserModel.cc +++ b/src/laybasic/laybasic/layNetlistBrowserModel.cc @@ -821,13 +821,10 @@ std::string formatted_value (double v) } static -std::string device_string (const db::Device *device) +std::string device_parameter_string (const db::Device *device) { - if (! device || ! device->device_class ()) { - return std::string (); - } + std::string s; - std::string s = device->device_class ()->name (); bool first = true; const std::vector &pd = device->device_class ()->parameter_definitions (); for (std::vector::const_iterator p = pd.begin (); p != pd.end (); ++p) { @@ -849,6 +846,16 @@ std::string device_string (const db::Device *device) return s; } +static +std::string device_string (const db::Device *device) +{ + if (! device || ! device->device_class ()) { + return std::string (); + } + + return device->device_class ()->name () + device_parameter_string (device); +} + static std::string device_class_string (const db::Device *device, bool dash_for_empty = false) { @@ -862,13 +869,20 @@ std::string device_class_string (const db::Device *device, bool dash_for_empty = } static -std::string devices_string (const std::pair &devices, bool is_single) +std::string devices_string (const std::pair &devices, bool is_single, bool with_parameters) { if (devices.first || devices.second) { - std::string s = device_class_string (devices.first, ! is_single); + std::string s; + s = device_class_string (devices.first, ! is_single); + if (with_parameters) { + s += device_parameter_string (devices.first); + } if (! is_single) { std::string t = device_class_string (devices.second, ! is_single); + if (with_parameters) { + t += device_parameter_string (devices.second); + } if (t != s) { s += var_sep; s += t; @@ -1149,6 +1163,11 @@ IndexedNetlistModel::net_pair nets_from_device_terminals (const IndexedNetlistMo const std::string field_sep (" / "); +static QString escaped (const std::string &s) +{ + return tl::to_qstring (tl::escaped_to_html (s)); +} + QString NetlistBrowserModel::text (const QModelIndex &index) const { @@ -1161,9 +1180,9 @@ NetlistBrowserModel::text (const QModelIndex &index) const // + dual mode: name(a)/name(b) | name(a) | name(b) IndexedNetlistModel::circuit_pair circuits = circuits_from_id (id); if (index.column () == m_object_column) { - return tl::to_qstring (str_from_names (circuits, mp_indexer->is_single ())); + return escaped (str_from_names (circuits, mp_indexer->is_single ())); } else if (!mp_indexer->is_single () && (index.column () == m_first_column || index.column () == m_second_column)) { - return tl::to_qstring (str_from_name (index.column () == m_first_column ? circuits.first : circuits.second)); + return escaped (str_from_name (index.column () == m_first_column ? circuits.first : circuits.second)); } } else if (is_id_circuit_pin (id)) { @@ -1173,9 +1192,9 @@ NetlistBrowserModel::text (const QModelIndex &index) const // + dual mode: xname(a)/xname(b) | xname(a) | xname(b) IndexedNetlistModel::pin_pair pins = pins_from_id (id); if (index.column () == m_object_column) { - return tl::to_qstring (str_from_expanded_names (pins, mp_indexer->is_single ())); + return escaped (str_from_expanded_names (pins, mp_indexer->is_single ())); } else if (!mp_indexer->is_single () && (index.column () == m_first_column || index.column () == m_second_column)) { - return tl::to_qstring (str_from_expanded_name (index.column () == m_first_column ? pins.first : pins.second)); + return escaped (str_from_expanded_name (index.column () == m_first_column ? pins.first : pins.second)); } } else if (is_id_circuit_pin_net (id)) { @@ -1186,7 +1205,7 @@ NetlistBrowserModel::text (const QModelIndex &index) const IndexedNetlistModel::net_pair nets = nets_from_circuit_pins (circuits, pins); if (index.column () == m_object_column) { - return tl::to_qstring (str_from_expanded_names (nets, mp_indexer->is_single ())); + return escaped (str_from_expanded_names (nets, mp_indexer->is_single ())); } else if (index.column () == m_first_column || index.column () == m_second_column) { return make_link_to (nets, index.column ()); } @@ -1199,19 +1218,19 @@ NetlistBrowserModel::text (const QModelIndex &index) const if (mp_indexer->is_single ()) { if (index.column () == m_object_column) { - return tl::to_qstring (device_string (devices.first)); + return escaped (device_string (devices.first)); } else if (index.column () == m_first_column) { - return tl::to_qstring (str_from_expanded_name (devices.first)); + return escaped (str_from_expanded_name (devices.first)); } } else { if (index.column () == m_object_column) { - return tl::to_qstring (devices_string (devices, mp_indexer->is_single ())); + return escaped (devices_string (devices, mp_indexer->is_single (), false /*without parameters*/)); } else if (index.column () == m_first_column) { - return tl::to_qstring (str_from_expanded_name (devices.first) + field_sep + device_string (devices.first)); + return escaped (str_from_expanded_name (devices.first) + field_sep + device_string (devices.first)); } else if (index.column () == m_second_column) { - return tl::to_qstring (str_from_expanded_name (devices.second) + field_sep + device_string (devices.second)); + return escaped (str_from_expanded_name (devices.second) + field_sep + device_string (devices.second)); } } @@ -1227,7 +1246,7 @@ NetlistBrowserModel::text (const QModelIndex &index) const if (index.column () == m_object_column) { - return tl::to_qstring (str_from_names (termdefs, mp_indexer->is_single ())); + return escaped (str_from_names (termdefs, mp_indexer->is_single ())); } else if (index.column () == m_first_column || index.column () == m_second_column) { @@ -1244,9 +1263,9 @@ NetlistBrowserModel::text (const QModelIndex &index) const if (index.column () == m_object_column) { return make_link_to (circuit_refs); } else if (index.column () == m_first_column) { - return tl::to_qstring (str_from_expanded_name (subcircuits.first)); + return escaped (str_from_expanded_name (subcircuits.first)); } else if (index.column () == m_second_column) { - return tl::to_qstring (str_from_expanded_name (subcircuits.second)); + return escaped (str_from_expanded_name (subcircuits.second)); } } else if (is_id_circuit_subcircuit_pin (id)) { @@ -1267,11 +1286,11 @@ NetlistBrowserModel::text (const QModelIndex &index) const // circuit/net: header column = node count, second column net name IndexedNetlistModel::net_pair nets = nets_from_id (id); if (index.column () == m_object_column) { - return tl::to_qstring (str_from_expanded_names (nets, mp_indexer->is_single ())); + return escaped (str_from_expanded_names (nets, mp_indexer->is_single ())); } else if (index.column () == m_first_column && nets.first) { - return tl::to_qstring (nets.first->expanded_name () + " (" + tl::to_string (nets.first->pin_count () + nets.first->terminal_count () + nets.first->subcircuit_pin_count ()) + ")"); + return escaped (nets.first->expanded_name () + " (" + tl::to_string (nets.first->pin_count () + nets.first->terminal_count () + nets.first->subcircuit_pin_count ()) + ")"); } else if (index.column () == m_second_column && nets.second) { - return tl::to_qstring (nets.second->expanded_name () + " (" + tl::to_string (nets.second->pin_count () + nets.second->terminal_count () + nets.second->subcircuit_pin_count ()) + ")"); + return escaped (nets.second->expanded_name () + " (" + tl::to_string (nets.second->pin_count () + nets.second->terminal_count () + nets.second->subcircuit_pin_count ()) + ")"); } } else if (is_id_circuit_net_pin (id)) { @@ -1325,9 +1344,9 @@ NetlistBrowserModel::text (const QModelIndex &index) const std::pair termdefs = terminal_defs_from_terminal_refs (refs); if (mp_indexer->is_single ()) { - return tl::to_qstring (str_from_name (termdefs.first) + field_sep + device_string (devices.first)); + return escaped (str_from_name (termdefs.first) + field_sep + device_string (devices.first)); } else { - return tl::to_qstring (str_from_names (termdefs, mp_indexer->is_single ()) + field_sep + devices_string (devices, mp_indexer->is_single ())); + return escaped (str_from_names (termdefs, mp_indexer->is_single ()) + field_sep + devices_string (devices, mp_indexer->is_single (), true /*with parameters*/)); } } else if (index.column () == m_first_column || index.column () == m_second_column) { @@ -1346,7 +1365,7 @@ NetlistBrowserModel::text (const QModelIndex &index) const if (index.column () == m_object_column) { - return tl::to_qstring (str_from_names (termdefs, mp_indexer->is_single ())); + return escaped (str_from_names (termdefs, mp_indexer->is_single ())); } else if (index.column () == m_first_column || index.column () == m_second_column) { @@ -1434,6 +1453,20 @@ NetlistBrowserModel::status (const QModelIndex &index) const size_t index = circuit_device_index_from_id (id); return mp_indexer->device_from_index (circuits, index).second; + } else if (is_id_circuit_device_terminal (id)) { + + IndexedNetlistModel::device_pair devices = devices_from_id (id); + std::pair device_classes = device_classes_from_devices (devices); + size_t terminal = circuit_device_terminal_index_from_id (id); + + std::pair termdefs = terminal_defs_from_device_classes (device_classes, terminal); + + if (! is_valid_net_pair (nets_from_device_terminals (devices, termdefs))) { + // This indicates a wrong connection: the nets are associated in a way which is a not + // corresponding to a mapped net pair. Report Mismatch here. + return db::NetlistCrossReference::NoMatch; + } + } else if (is_id_circuit_subcircuit (id)) { IndexedNetlistModel::circuit_pair circuits = circuits_from_id (id); @@ -1455,7 +1488,7 @@ NetlistBrowserModel::status (const QModelIndex &index) const if (! is_valid_net_pair (nets_from_subcircuit_pins (subcircuits, pins))) { // This indicates a wrong connection: the nets are associated in a way which is a not // corresponding to a mapped net pair. Report Mismatch here. - return db::NetlistCrossReference::MatchWithWarning; + return db::NetlistCrossReference::NoMatch; } } else if (is_id_circuit_net (id)) { @@ -1472,6 +1505,21 @@ NetlistBrowserModel::status (const QModelIndex &index) const return mp_indexer->device_from_index (circuits, mp_indexer->device_index (devices)).second; + } else if (is_id_circuit_net_device_terminal_others (id)) { + + IndexedNetlistModel::net_terminal_pair termrefs = net_terminalrefs_from_id (id); + size_t other_index = circuit_net_device_terminal_other_index_from_id (id); + + IndexedNetlistModel::device_pair devices = devices_from_termrefs (termrefs); + std::pair device_classes = device_classes_from_devices (devices); + std::pair termdefs = terminal_defs_from_device_classes (device_classes, other_index); + + if (! is_valid_net_pair (nets_from_device_terminals (devices, termdefs))) { + // This indicates a wrong connection: the nets are associated in a way which is a not + // corresponding to a mapped net pair. Report Mismatch here. + return db::NetlistCrossReference::NoMatch; + } + } else if (is_id_circuit_net_subcircuit_pin (id)) { IndexedNetlistModel::circuit_pair circuits = circuits_from_id (id); @@ -1492,7 +1540,7 @@ NetlistBrowserModel::status (const QModelIndex &index) const if (! is_valid_net_pair (nets_from_subcircuit_pins (subcircuits, pins))) { // This indicates a wrong connection: the nets are associated in a way which is a not // corresponding to a mapped net pair. Report Mismatch here. - return db::NetlistCrossReference::MatchWithWarning; + return db::NetlistCrossReference::NoMatch; } } diff --git a/src/laybasic/laybasic/layNetlistCrossReferenceModel.cc b/src/laybasic/laybasic/layNetlistCrossReferenceModel.cc index 6532afed4..0c28f51e3 100644 --- a/src/laybasic/laybasic/layNetlistCrossReferenceModel.cc +++ b/src/laybasic/laybasic/layNetlistCrossReferenceModel.cc @@ -532,6 +532,11 @@ std::string NetlistCrossReferenceModel::device_status_hint (const circuit_pair & "Devices are identified by the nets they are attached to. Unmatched devices mean that\n" "at least one terminal net isn't matched with a corresponding net from the other netlist.\n" "Make all terminal nets match and the devices will match too.")); + } else { + return tl::to_string (tr ("Devices don't match topologically.\n" + "Check the terminal connections to identify the terminals not being connected to\n" + "corresponding nets. Either the devices are not connected correctly or the nets\n" + "need to be fixed before the devices will match too.")); } } else if (cps.second == db::NetlistCrossReference::MatchWithWarning) { return tl::to_string (tr ("Topologically matching devices are found here but either the parameters or the\n" diff --git a/src/laybasic/unit_tests/layNetlistBrowserModelTests.cc b/src/laybasic/unit_tests/layNetlistBrowserModelTests.cc index 65642f6d8..7fac3d3a7 100644 --- a/src/laybasic/unit_tests/layNetlistBrowserModelTests.cc +++ b/src/laybasic/unit_tests/layNetlistBrowserModelTests.cc @@ -289,7 +289,7 @@ TEST (2) // INV2, net 1 has one pin and one terminal at BULK EXPECT_EQ (tl::to_string (model->data (model->index (0, 0, inv2Net0Index), Qt::UserRole).toString ()), "B|B|PMOS|PMOS|$1|$1"); - EXPECT_EQ (tl::to_string (model->data (model->index (0, 0, inv2Net0Index), Qt::DisplayRole).toString ()), "B / PMOS"); + EXPECT_EQ (tl::to_string (model->data (model->index (0, 0, inv2Net0Index), Qt::DisplayRole).toString ()), "B / PMOS [L=0.25, W=3.5]"); EXPECT_EQ (tl::to_string (model->data (model->index (0, 2, inv2Net0Index), Qt::DisplayRole).toString ()), "$1"); EXPECT_EQ (tl::to_string (model->data (model->index (0, 3, inv2Net0Index), Qt::DisplayRole).toString ()), "$1"); diff --git a/src/lvs/lvs/built-in-macros/_lvs_engine.rb b/src/lvs/lvs/built-in-macros/_lvs_engine.rb index bc928d1e6..b7a1dc2b7 100644 --- a/src/lvs/lvs/built-in-macros/_lvs_engine.rb +++ b/src/lvs/lvs/built-in-macros/_lvs_engine.rb @@ -94,6 +94,12 @@ module LVS # @synopsis compare # See \Netter#compare for a description of that function. + # %LVS% + # @name align + # @brief Aligns the extracted netlist vs. the schematic by flattening circuits where required + # @synopsis align + # See \Netter#align for a description of that function. + # %LVS% # @name same_nets # @brief Establishes an equivalence between the nets @@ -143,7 +149,7 @@ module LVS # @synopsis max_depth(n) # See \Netter#max_depth for a description of that function. - %w(schematic compare same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity).each do |f| + %w(schematic compare align same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity).each do |f| eval <<"CODE" def #{f}(*args) _netter.#{f}(*args) diff --git a/src/lvs/lvs/built-in-macros/_lvs_netter.rb b/src/lvs/lvs/built-in-macros/_lvs_netter.rb index 16014e9d0..4b445e3da 100644 --- a/src/lvs/lvs/built-in-macros/_lvs_netter.rb +++ b/src/lvs/lvs/built-in-macros/_lvs_netter.rb @@ -91,6 +91,46 @@ module LVS data end + # %LVS% + # @name align + # @brief Aligns the extracted netlist vs. the schematic + # @synopsis align + # The align method will modify the netlists in case of missing + # corresponding circuits. It will flatten these circuits, thus + # improving the equivalence between the netlists. Top level circuits + # are not flattened. + # + # This feature is in particular useful to remove structural cells + # like device PCells, reuse blocks etc. + # + # This method will also remove schematic circuits for which there is + # no corresponding layout cell. In the extreme case of flat layout this + # will result in a flat vs. flat compare. + # + # "netlist.flatten_circuit(...)" or "schematic.flatten_circuit(...)" + # are other (explicit) ways to flatten circuits. + # + # Please note that flattening circuits has some side effects such + # as loss of details in the cross reference and net layout. + + def align + + nl = _ensure_two_netlists + + # flatten layout cells for which there is no corresponding schematic circuit + @comparer.unmatched_circuits_a(*nl).each do |c| + @engine.info("Flatten layout cell (no schematic): #{c.name}") + nl[0].flatten_circuit(c) + end + + # flatten schematic circuits for which there is no corresponding layout cell + @comparer.unmatched_circuits_b(*nl).each do |c| + @engine.info("Flatten schematic circuit (no layout): #{c.name}") + nl[1].flatten_circuit(c) + end + + end + # %LVS% # @name compare # @brief Compares the extracted netlist vs. the schematic @@ -99,12 +139,19 @@ module LVS # The compare can be configured in more details using \same_nets, \same_circuits, # \same_device_classes and \equivalent_pins. # + # The compare method will also modify the netlists in case of missing + # corresponding circuits: the unpaired circuit will be flattened then. + # # This method will return true, if the netlists are equivalent and false # otherwise. def compare - lvs_data.reference = _ensure_two_netlists[1] + + nl = _ensure_two_netlists + lvs_data.reference = nl[1] + lvs_data.compare(@comparer) + end def _ensure_two_netlists diff --git a/src/lvs/lvs/templates/lvs.lym b/src/lvs/lvs/templates/lvs.lym index 09e9ea06c..7b74b5643 100644 --- a/src/lvs/lvs/templates/lvs.lym +++ b/src/lvs/lvs/templates/lvs.lym @@ -101,6 +101,9 @@ connect_global(ptie, "SUBSTRATE") # Netlist normalization netlist.simplify +# Hierarchy alignment (flatten out unmatched cells) +align + # Netlist vs. netlist compare diff --git a/src/lvs/unit_tests/lvsSimpleTests.cc b/src/lvs/unit_tests/lvsSimpleTests.cc index 7e14387b5..5c3319b22 100644 --- a/src/lvs/unit_tests/lvsSimpleTests.cc +++ b/src/lvs/unit_tests/lvsSimpleTests.cc @@ -118,3 +118,14 @@ TEST(9_blackboxing) { run_test (_this, "ringo_simple_blackboxing", "ringo_for_blackboxing.gds"); } + +TEST(10_simplification_with_align) +{ + run_test (_this, "ringo_simple_simplification_with_align", "ringo_for_simplification.gds"); +} + +TEST(11_device_scaling) +{ + run_test (_this, "ringo_simple_device_scaling", "ringo.gds"); +} + diff --git a/src/lvs/unit_tests/lvsTests.cc b/src/lvs/unit_tests/lvsTests.cc index d3ce9fa7c..d4fc23a89 100644 --- a/src/lvs/unit_tests/lvsTests.cc +++ b/src/lvs/unit_tests/lvsTests.cc @@ -30,10 +30,10 @@ #include "lymMacro.h" #include "tlFileUtils.h" -void run_test (tl::TestBase *_this, const std::string &suffix, const std::string &layout) +void run_test (tl::TestBase *_this, const std::string &lvs_rs, const std::string &suffix, const std::string &layout) { std::string rs = tl::testsrc (); - rs += "/testdata/lvs/" + suffix + ".lvs"; + rs += "/testdata/lvs/" + lvs_rs; std::string src = tl::testsrc (); src += "/testdata/lvs/" + layout; @@ -100,5 +100,12 @@ void run_test (tl::TestBase *_this, const std::string &suffix, const std::string TEST(1_full) { - run_test (_this, "vexriscv", "vexriscv.oas.gz"); + test_is_long_runner (); + run_test (_this, "vexriscv.lvs", "vexriscv", "vexriscv.oas.gz"); +} + +TEST(2_fullWithAlign) +{ + test_is_long_runner (); + run_test (_this, "vexriscv_align.lvs", "vexriscv", "vexriscv.oas.gz"); } diff --git a/testdata/algo/device_extract_au5_flattened_circuits.gds b/testdata/algo/device_extract_au5_flattened_circuits.gds new file mode 100644 index 000000000..40dc8210f Binary files /dev/null and b/testdata/algo/device_extract_au5_flattened_circuits.gds differ diff --git a/testdata/algo/lvs_test1_au.lvsdb.1 b/testdata/algo/lvs_test1_au.lvsdb.1 index b20b9b77b..5f45d3819 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.1 +++ b/testdata/algo/lvs_test1_au.lvsdb.1 @@ -954,8 +954,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(3 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR match diff --git a/testdata/algo/lvs_test1_au.lvsdb.2 b/testdata/algo/lvs_test1_au.lvsdb.2 index f0a135237..cf52cf8cd 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.2 +++ b/testdata/algo/lvs_test1_au.lvsdb.2 @@ -954,8 +954,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(3 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR match diff --git a/testdata/algo/lvs_test1b_au.lvsdb.1 b/testdata/algo/lvs_test1b_au.lvsdb.1 index 58faa611b..ca44150de 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.1 +++ b/testdata/algo/lvs_test1b_au.lvsdb.1 @@ -954,8 +954,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR match diff --git a/testdata/algo/lvs_test1b_au.lvsdb.2 b/testdata/algo/lvs_test1b_au.lvsdb.2 index dbcdf7f3e..2db900155 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.2 +++ b/testdata/algo/lvs_test1b_au.lvsdb.2 @@ -954,8 +954,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR match diff --git a/testdata/algo/lvs_test2_au.lvsdb.1 b/testdata/algo/lvs_test2_au.lvsdb.1 index 7e3552182..85ec734bf 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.1 +++ b/testdata/algo/lvs_test2_au.lvsdb.1 @@ -980,8 +980,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(3 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR nomatch diff --git a/testdata/algo/lvs_test2_au.lvsdb.2 b/testdata/algo/lvs_test2_au.lvsdb.2 index 73670ff54..9dacebd21 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.2 +++ b/testdata/algo/lvs_test2_au.lvsdb.2 @@ -980,8 +980,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(3 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR nomatch diff --git a/testdata/algo/lvs_test2b_au.lvsdb.1 b/testdata/algo/lvs_test2b_au.lvsdb.1 index e1a8825f8..f0a00dfb1 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.1 +++ b/testdata/algo/lvs_test2b_au.lvsdb.1 @@ -980,8 +980,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR nomatch diff --git a/testdata/algo/lvs_test2b_au.lvsdb.2 b/testdata/algo/lvs_test2b_au.lvsdb.2 index 6f4b5e8d3..1cf9af670 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.2 +++ b/testdata/algo/lvs_test2b_au.lvsdb.2 @@ -980,8 +980,8 @@ xref( pin(2 2 match) pin(4 4 match) pin(3 3 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(INV2PAIR INV2PAIR nomatch diff --git a/testdata/algo/nreader7.cir b/testdata/algo/nreader7.cir new file mode 100644 index 000000000..210af361c --- /dev/null +++ b/testdata/algo/nreader7.cir @@ -0,0 +1,31 @@ +* RINGO netlist with global nets + +.GLOBAL VDD +.GLOBAL VSS + +.SUBCKT RINGO FB OUT ENABLE +X$1 1 FB ENABLE ND2X1 +X$2 2 1 INVX1 +X$3 3 2 INVX1 +X$4 4 3 INVX1 +X$5 5 4 INVX1 +X$6 6 5 INVX1 +X$7 7 6 INVX1 +X$8 8 7 INVX1 +X$9 9 8 INVX1 +X$10 10 9 INVX1 +X$11 FB 10 INVX1 +X$12 OUT FB INVX1 +.ENDS RINGO + +.SUBCKT ND2X1 OUT B A +M$1 OUT A VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$2 VDD B OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$3 VSS A INT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$4 INT B OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +.ENDS ND2X1 + +.SUBCKT INVX1 OUT IN +M$1 VDD IN OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$2 VSS IN OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 diff --git a/testdata/drc/drcSimpleTests_11.drc b/testdata/drc/drcSimpleTests_11.drc index e9a059603..9f23a1b5f 100644 --- a/testdata/drc/drcSimpleTests_11.drc +++ b/testdata/drc/drcSimpleTests_11.drc @@ -91,8 +91,8 @@ class CustomResistorExtraction < RBA::GenericDeviceExtractor # -> W = p-sqrt(p*p-A) # (p=P/4) - p = 0.25 * r.perimeter - a = r.area + p = sdbu * 0.25 * r.perimeter + a = sdbu * sdbu * r.area d = Math.sqrt(p * p - a) l = p + d @@ -102,7 +102,10 @@ class CustomResistorExtraction < RBA::GenericDeviceExtractor device = create_device + device.trans = RBA::DCplxTrans::new(RBA::CplxTrans::new(dbu) * (r.bbox.center - RBA::Point::new)); + device.set_parameter(RBA::DeviceClassResistor::PARAM_R, @sheet_rho * l / w); + device.set_parameter(RBA::DeviceClassResistor::PARAM_A, a); define_terminal(device, RBA::DeviceClassResistor::TERMINAL_A, conductor_geometry_index, terminals[0]); define_terminal(device, RBA::DeviceClassResistor::TERMINAL_B, conductor_geometry_index, terminals[1]); diff --git a/testdata/lvs/inv.lvsdb b/testdata/lvs/inv.lvsdb index 33c6d5e86..4b8431f79 100644 --- a/testdata/lvs/inv.lvsdb +++ b/testdata/lvs/inv.lvsdb @@ -18,21 +18,21 @@ layout( layer(l12 'METAL2 (9/0)') layer(l13 'METAL2_LABEL (9/1)') layer(l7) - layer(l1) - layer(l5) + layer(l2) + layer(l6) # Mask layer connectivity connect(l3 l3) connect(l4 l4 l8) - connect(l8 l4 l8 l9 l1 l5) + connect(l8 l4 l8 l9 l2 l6) connect(l9 l8 l9 l10 l11) connect(l10 l9 l10) connect(l11 l9 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) - connect(l5 l8 l5) + connect(l2 l8 l2) + connect(l6 l8 l6) # Global nets and connectivity global(l3 NWELL) @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-575 -450) (450 900)) + rect(l6 (-575 -450) (450 900)) ) terminal(G rect(l4 (-125 -450) (250 900)) ) terminal(D - rect(l5 (125 -450) (450 900)) + rect(l6 (125 -450) (450 900)) ) terminal(B rect(l7 (-125 -450) (250 900)) @@ -98,7 +98,7 @@ layout( rect(l11 (-200 300) (200 200)) rect(l12 (-750 -850) (2000 1000)) rect(l13 (-101 -851) (2 2)) - rect(l5 (-1451 49) (450 900)) + rect(l6 (-1451 49) (450 900)) ) net(3 name(VDD) rect(l8 (550 4350) (200 200)) @@ -109,7 +109,7 @@ layout( rect(l11 (-200 300) (200 200)) rect(l12 (-750 -850) (2000 1000)) rect(l13 (-151 -851) (2 2)) - rect(l1 (-1401 -851) (450 1500)) + rect(l2 (-1401 -851) (450 1500)) ) net(4 name(OUT) rect(l8 (1300 4350) (200 200)) @@ -122,8 +122,8 @@ layout( rect(l9 (-300 -2900) (450 400)) rect(l9 (-450 -1550) (300 850)) rect(l10 (-51 499) (2 2)) - rect(l1 (-351 2649) (450 1500)) - rect(l5 (-450 -5500) (450 900)) + rect(l2 (-351 2649) (450 1500)) + rect(l6 (-450 -5500) (450 900)) ) net(5 name(NWELL) rect(l3 (0 2950) (2000 3200)) diff --git a/testdata/lvs/inv2.lvsdb b/testdata/lvs/inv2.lvsdb index 594a5e685..782d6282e 100644 --- a/testdata/lvs/inv2.lvsdb +++ b/testdata/lvs/inv2.lvsdb @@ -11,34 +11,34 @@ J( L(l14 'METAL2 (9/0)') L(l15 'METAL2_LABEL (9/1)') L(l7) - L(l1) + L(l2) L(l9) - L(l5) + L(l6) L(l10) C(l3 l3 l9) C(l4 l4 l8) - C(l8 l4 l8 l11 l1 l9 l5 l10) + C(l8 l4 l8 l11 l2 l9 l6 l10) C(l11 l8 l11 l12 l13) C(l12 l11 l12) C(l13 l11 l13 l14) C(l14 l13 l14 l15) C(l15 l14 l15) C(l7 l7) - C(l1 l8 l1) + C(l2 l8 l2) C(l9 l3 l8 l9) - C(l5 l8 l5) + C(l6 l8 l6) C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) D(D$PMOS PMOS T(S - R(l1 (-575 -750) (450 1500)) + R(l2 (-575 -750) (450 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (450 1500)) + R(l2 (125 -750) (450 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -46,13 +46,13 @@ J( ) D(D$NMOS NMOS T(S - R(l5 (-575 -450) (450 900)) + R(l6 (-575 -450) (450 900)) ) T(G R(l4 (-125 -450) (250 900)) ) T(D - R(l5 (125 -450) (450 900)) + R(l6 (125 -450) (450 900)) ) T(B R(l7 (-125 -450) (250 900)) @@ -84,7 +84,7 @@ J( R(l13 (-200 300) (200 200)) R(l14 (-2350 -850) (3000 1000)) R(l15 (-151 -851) (2 2)) - R(l1 (-2401 -851) (450 1500)) + R(l2 (-2401 -851) (450 1500)) R(l9 (1050 -1200) (600 1200)) ) N(3 I(OUT) @@ -98,8 +98,8 @@ J( R(l11 (-300 -2900) (450 400)) R(l11 (-450 -1550) (300 850)) R(l12 (-51 499) (2 2)) - R(l1 (-351 2649) (450 1500)) - R(l5 (-450 -5500) (450 900)) + R(l2 (-351 2649) (450 1500)) + R(l6 (-450 -5500) (450 900)) ) N(4 I(VSS) R(l8 (550 300) (200 200)) @@ -114,7 +114,7 @@ J( R(l13 (-200 300) (200 200)) R(l14 (-2350 -850) (3000 1000)) R(l15 (-151 -851) (2 2)) - R(l5 (-2401 49) (450 900)) + R(l6 (-2401 49) (450 900)) R(l10 (1050 -900) (600 1200)) ) D(1 D$PMOS diff --git a/testdata/lvs/ringo_scaled.cir b/testdata/lvs/ringo_scaled.cir new file mode 100644 index 000000000..3cb10be81 --- /dev/null +++ b/testdata/lvs/ringo_scaled.cir @@ -0,0 +1,27 @@ + +.SUBCKT RINGO VSS VDD FB ENABLE OUT +X$1 VDD 1 VSS VDD FB ENABLE VSS ND2X1 +X$2 VDD 2 VSS VDD 1 VSS INVX1 +X$3 VDD 3 VSS VDD 2 VSS INVX1 +X$4 VDD 4 VSS VDD 3 VSS INVX1 +X$5 VDD 5 VSS VDD 4 VSS INVX1 +X$6 VDD 6 VSS VDD 5 VSS INVX1 +X$7 VDD 7 VSS VDD 6 VSS INVX1 +X$8 VDD 8 VSS VDD 7 VSS INVX1 +X$9 VDD 9 VSS VDD 8 VSS INVX1 +X$10 VDD 10 VSS VDD 9 VSS INVX1 +X$11 VDD FB VSS VDD 10 VSS INVX1 +X$12 VDD OUT VSS VDD FB VSS INVX1 +.ENDS RINGO + +.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK +M$1 OUT A VDD NWELL PMOS L=0.5U W=3U +M$2 VDD B OUT NWELL PMOS L=0.5U W=3U +M$3 VSS A 1 BULK NMOS L=0.5U W=1.9U +M$4 1 B OUT BULK NMOS L=0.5U W=1.9U +.ENDS ND2X1 + +.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK +M$1 VDD IN OUT NWELL PMOS L=0.5U W=3U +M$2 VSS IN OUT BULK NMOS L=0.5U W=1.9U +.ENDS INVX1 diff --git a/testdata/lvs/ringo_simple.lvsdb.1 b/testdata/lvs/ringo_simple.lvsdb.1 index 9ed4f2480..a68dae475 100644 --- a/testdata/lvs/ringo_simple.lvsdb.1 +++ b/testdata/lvs/ringo_simple.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-2550 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple.lvsdb.2 b/testdata/lvs/ringo_simple.lvsdb.2 index 2d8585635..834cc43fe 100644 --- a/testdata/lvs/ringo_simple.lvsdb.2 +++ b/testdata/lvs/ringo_simple.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-1175 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_blackboxing.lvsdb b/testdata/lvs/ringo_simple_blackboxing.lvsdb index 172b60755..0e9ead554 100644 --- a/testdata/lvs/ringo_simple_blackboxing.lvsdb +++ b/testdata/lvs/ringo_simple_blackboxing.lvsdb @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7 '13/0') - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -185,10 +185,22 @@ layout( rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) ) - net(12) - net(13) - net(14) - net(15) + net(12 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + ) + net(13 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + ) + net(14 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + ) + net(15 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + ) # Outgoing pins and their connections to nets pin(5 name(FB)) @@ -525,10 +537,6 @@ xref( pin(2 4 match) pin(1 0 match) pin(4 1 match) - circuit(1 1 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) circuit(2 2 match) circuit(3 3 match) circuit(17 4 match) @@ -537,6 +545,10 @@ xref( circuit(20 7 match) circuit(21 8 match) circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_device_scaling.cir b/testdata/lvs/ringo_simple_device_scaling.cir new file mode 100644 index 000000000..44196cb11 --- /dev/null +++ b/testdata/lvs/ringo_simple_device_scaling.cir @@ -0,0 +1,83 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 11 12 13 14 15 +* net 11 FB +* net 12 VDD +* net 13 OUT +* net 14 ENABLE +* net 15 VSS +* cell instance $1 r0 *1 1.8,0 +X$1 12 1 15 12 11 14 15 ND2X1 +* cell instance $2 r0 *1 4.2,0 +X$2 12 2 15 12 1 15 INVX1 +* cell instance $3 r0 *1 6,0 +X$3 12 3 15 12 2 15 INVX1 +* cell instance $4 r0 *1 7.8,0 +X$4 12 4 15 12 3 15 INVX1 +* cell instance $5 r0 *1 9.6,0 +X$5 12 5 15 12 4 15 INVX1 +* cell instance $6 r0 *1 11.4,0 +X$6 12 6 15 12 5 15 INVX1 +* cell instance $7 r0 *1 13.2,0 +X$7 12 7 15 12 6 15 INVX1 +* cell instance $8 r0 *1 15,0 +X$8 12 8 15 12 7 15 INVX1 +* cell instance $9 r0 *1 16.8,0 +X$9 12 9 15 12 8 15 INVX1 +* cell instance $10 r0 *1 18.6,0 +X$10 12 10 15 12 9 15 INVX1 +* cell instance $11 r0 *1 20.4,0 +X$11 12 11 15 12 10 15 INVX1 +* cell instance $12 r0 *1 22.2,0 +X$12 12 13 15 12 11 15 INVX1 +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 1 5 2 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 4 5 6 7 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 B +* net 6 A +* net 7 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 6 1 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 1 5 2 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 3 6 8 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U +* device instance $4 r0 *1 1.55,2.135 NMOS +M$4 8 5 2 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_device_scaling.lvs b/testdata/lvs/ringo_simple_device_scaling.lvs new file mode 100644 index 000000000..afb3caebb --- /dev/null +++ b/testdata/lvs/ringo_simple_device_scaling.lvs @@ -0,0 +1,76 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("ringo_scaled.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ptie = active_outside_nwell & pplus + +# Device extraction + +device_scaling(2.0) + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, contact) +connect(nsd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +netlist.simplify + +compare + diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 new file mode 100644 index 000000000..d4ba4694d --- /dev/null +++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 @@ -0,0 +1,971 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.5) + param(W 3) + param(AS 2.55) + param(AD 1.35) + param(PS 7.7) + param(PD 3.9) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.5) + param(W 3) + param(AS 1.35) + param(AD 2.55) + param(PS 3.9) + param(PD 7.7) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.5) + param(W 1.9) + param(AS 1.615) + param(AD 0.855) + param(PS 5.5) + param(PD 2.8) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.5) + param(W 1.9) + param(AS 0.855) + param(AD 1.615) + param(PS 2.8) + param(PD 5.5) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.5) + param(W 3) + param(AS 2.55) + param(AD 2.55) + param(PS 7.7) + param(PD 7.7) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.5) + param(W 1.9) + param(AS 1.615) + param(AD 1.615) + param(PS 5.5) + param(PD 5.5) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(2 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l9 (-21975 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 new file mode 100644 index 000000000..354c9386a --- /dev/null +++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 @@ -0,0 +1,971 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.5) + param(W 3) + param(AS 2.55) + param(AD 1.35) + param(PS 7.7) + param(PD 3.9) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.5) + param(W 3) + param(AS 1.35) + param(AD 2.55) + param(PS 3.9) + param(PD 7.7) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.5) + param(W 1.9) + param(AS 1.615) + param(AD 0.855) + param(PS 5.5) + param(PD 2.8) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.5) + param(W 1.9) + param(AS 0.855) + param(AD 1.615) + param(PS 2.8) + param(PD 5.5) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.5) + param(W 3) + param(AS 2.55) + param(AD 2.55) + param(PS 7.7) + param(PD 7.7) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.5) + param(W 1.9) + param(AS 1.615) + param(AD 1.615) + param(PS 5.5) + param(PD 5.5) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(2 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(7 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(8 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(9 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(10 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l9 (-21975 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 index 8fc6d3364..2760c734e 100644 --- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 +++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (5210 3010) (180 180)) rect(l11 (-1350 -240) (1160 300)) - rect(l1 (-3100 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-3100 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (7010 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8810 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10610 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (12410 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (14210 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (16010 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17810 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19610 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (21410 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (25210 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-19071 -201) (2 2)) rect(l13 (-171 -201) (400 400)) rect(l13 (18490 -400) (400 400)) - rect(l1 (-545 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-545 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (22600 4500) (1400 3500)) @@ -466,19 +466,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23300 -2550) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (-18850 -1500) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (21775 -1500) (425 1500)) + rect(l2 (-23300 -2550) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (-18850 -1500) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (21775 -1500) (425 1500)) rect(l9 (-2375 -450) (500 1500)) rect(l9 (-22600 -1500) (500 1500)) rect(l9 (25400 -1500) (500 1500)) @@ -488,8 +488,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-151 -101) (2 2)) rect(l13 (-151 -201) (400 400)) - rect(l1 (-675 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-675 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -522,18 +522,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (-1251 -401) (600 800)) - rect(l5 (24400 460) (425 950)) - rect(l5 (-20425 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (-19525 -950) (425 950)) + rect(l6 (24400 460) (425 950)) + rect(l6 (-20425 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (-19525 -950) (425 950)) rect(l10 (24325 -2210) (500 1500)) rect(l10 (-4300 -1500) (500 1500)) rect(l10 (-22600 -1500) (500 1500)) @@ -924,8 +924,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -945,10 +945,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -973,10 +973,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -985,6 +981,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 index 03e96d090..4a0b7e13e 100644 --- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 +++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (5210 3010) (180 180)) rect(l11 (-1350 -240) (1160 300)) - rect(l1 (-1725 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1725 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (7010 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8810 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10610 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (12410 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (14210 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (16010 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17810 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19610 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (21410 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (25210 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-19071 -201) (2 2)) rect(l13 (-171 -201) (400 400)) rect(l13 (18490 -400) (400 400)) - rect(l1 (-545 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-545 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (22600 4500) (1400 3500)) @@ -466,19 +466,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23300 -2550) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (-18850 -1500) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (21775 -1500) (425 1500)) + rect(l2 (-23300 -2550) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (-18850 -1500) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (21775 -1500) (425 1500)) rect(l9 (-2375 -450) (500 1500)) rect(l9 (-22600 -1500) (500 1500)) rect(l9 (25400 -1500) (500 1500)) @@ -488,8 +488,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-151 -101) (2 2)) rect(l13 (-151 -201) (400 400)) - rect(l1 (-675 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-675 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -522,18 +522,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (-1251 -401) (600 800)) - rect(l5 (24400 460) (425 950)) - rect(l5 (-20425 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (-19525 -950) (425 950)) + rect(l6 (24400 460) (425 950)) + rect(l6 (-20425 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (-19525 -950) (425 950)) rect(l10 (24325 -2210) (500 1500)) rect(l10 (-4300 -1500) (500 1500)) rect(l10 (-22600 -1500) (500 1500)) @@ -924,8 +924,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -945,10 +945,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -973,10 +973,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -985,6 +981,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.1 b/testdata/lvs/ringo_simple_io.lvsdb.1 index bff5f1a20..edb8e90ce 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io.lvsdb.1 @@ -9,32 +9,32 @@ J( L(l12 '10/0') L(l13 '11/0') L(l7) - L(l1) + L(l2) L(l9) - L(l5) + L(l6) L(l10) C(l3 l3 l9) C(l4 l4 l8) - C(l8 l4 l8 l11 l1 l9 l5 l10) + C(l8 l4 l8 l11 l2 l9 l6 l10) C(l11 l8 l11 l12) C(l12 l11 l12 l13) C(l13 l12 l13) C(l7 l7) - C(l1 l8 l1) + C(l2 l8 l2) C(l9 l3 l8 l9) - C(l5 l8 l5) + C(l6 l8 l6) C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) D(D$PMOS PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (450 1500)) + R(l2 (125 -750) (450 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -42,13 +42,13 @@ J( ) D(D$PMOS$1 PMOS T(S - R(l1 (-575 -750) (450 1500)) + R(l2 (-575 -750) (450 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -56,13 +56,13 @@ J( ) D(D$PMOS$2 PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -70,13 +70,13 @@ J( ) D(D$NMOS NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (450 950)) + R(l6 (125 -475) (450 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -84,13 +84,13 @@ J( ) D(D$NMOS$1 NMOS T(S - R(l5 (-575 -475) (450 950)) + R(l6 (-575 -475) (450 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -98,13 +98,13 @@ J( ) D(D$NMOS$2 NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -119,8 +119,8 @@ J( R(l11 (-240 -790) (300 1700)) R(l11 (-1350 0) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l1 (-276 -2151) (425 1500)) - R(l1 (-400 -1500) (425 1500)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) ) N(2 I(OUT) R(l8 (1810 1770) (180 180)) @@ -138,9 +138,9 @@ J( R(l11 (-1751 1099) (300 1400)) R(l11 (1100 -1700) (300 300)) R(l11 (-300 0) (300 1400)) - R(l1 (-1750 -1450) (425 1500)) - R(l1 (950 -1500) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1750 -1450) (425 1500)) + R(l2 (950 -1500) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -148,7 +148,7 @@ J( R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l5 (-951 859) (425 950)) + R(l6 (-951 859) (425 950)) ) N(4 R(l3 (-100 4500) (2600 3500)) @@ -175,8 +175,8 @@ J( ) N(7 I(SUBSTRATE)) N(8 - R(l5 (975 1660) (425 950)) - R(l5 (-400 -950) (425 950)) + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) ) P(1 I(VDD)) P(2 I(OUT)) @@ -248,7 +248,7 @@ J( R(l11 (-650 300) (1800 800)) R(l11 (-1450 -1100) (300 300)) R(l11 (299 399) (2 2)) - R(l1 (-651 -2151) (425 1500)) + R(l2 (-651 -2151) (425 1500)) ) N(2 I(OUT) R(l8 (1110 5160) (180 180)) @@ -258,8 +258,8 @@ J( R(l8 (-180 370) (180 180)) R(l11 (-240 -790) (300 4790)) R(l11 (-151 -2501) (2 2)) - R(l1 (-226 1049) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -267,7 +267,7 @@ J( R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (1800 800)) R(l11 (-851 -401) (2 2)) - R(l5 (-651 859) (425 950)) + R(l6 (-651 859) (425 950)) ) N(4 R(l3 (-100 4500) (2000 3500)) @@ -321,63 +321,63 @@ J( N(1 R(l8 (4710 3010) (180 180)) R(l11 (-850 -240) (610 300)) - R(l1 (-2550 1800) (425 1500)) - R(l1 (950 -1500) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-2550 1800) (425 1500)) + R(l2 (950 -1500) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(2 R(l8 (6510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 R(l8 (8310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(4 R(l8 (10110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(5 R(l8 (11910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(6 R(l8 (13710 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(7 R(l8 (15510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(8 R(l8 (17310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(9 R(l8 (19110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(10 R(l8 (20910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(11 I(FB) R(l8 (22710 3010) (180 180)) @@ -391,8 +391,8 @@ J( R(l13 (-17921 -201) (2 2)) R(l13 (-221 -201) (400 400)) R(l13 (17740 -400) (400 400)) - R(l1 (-245 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-245 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(12 I(VDD) R(l3 (500 4500) (1400 3500)) @@ -414,19 +414,19 @@ J( R(l11 (-750 -1450) (300 1400)) R(l11 (-101 -351) (2 2)) R(l11 (549 -401) (600 800)) - R(l1 (-23025 -2550) (425 1500)) - R(l1 (-400 -1500) (425 1500)) - R(l1 (1275 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) + R(l2 (-23025 -2550) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + R(l2 (1275 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) R(l9 (-21975 -450) (500 1500)) R(l9 (22900 -1500) (500 1500)) ) @@ -435,8 +435,8 @@ J( R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) - R(l1 (-625 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-625 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(14 I(ENABLE) R(l8 (2510 3010) (180 180)) @@ -461,18 +461,18 @@ J( R(l11 (-750 -1450) (1200 800)) R(l11 (-551 -401) (2 2)) R(l11 (549 -401) (600 800)) - R(l5 (-23700 460) (425 950)) - R(l5 (1975 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) + R(l6 (-23700 460) (425 950)) + R(l6 (1975 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) R(l10 (-21975 -2210) (500 1500)) R(l10 (22900 -1500) (500 1500)) ) @@ -825,8 +825,8 @@ Z( P(5 5 1) P(0 0 1) P(2 2 1) - D(1 1 1) D(2 2 1) + D(1 1 1) ) ) X(ND2X1 ND2X1 1 @@ -846,10 +846,10 @@ Z( P(6 6 1) P(0 0 1) P(2 2 1) - D(1 1 1) - D(2 2 1) D(3 3 1) D(4 4 1) + D(1 1 1) + D(2 2 1) ) ) X(RINGO RINGO 1 @@ -874,10 +874,6 @@ Z( P(2 4 1) P(1 1 1) P(4 0 1) - X(1 1 1) - X(10 10 1) - X(11 11 1) - X(12 12 1) X(2 2 1) X(3 3 1) X(4 4 1) @@ -886,6 +882,10 @@ Z( X(7 7 1) X(8 8 1) X(9 9 1) + X(10 10 1) + X(11 11 1) + X(12 12 1) + X(1 1 1) ) ) ) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.2 b/testdata/lvs/ringo_simple_io.lvsdb.2 index 64c35b1c6..1db7e627a 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.2 +++ b/testdata/lvs/ringo_simple_io.lvsdb.2 @@ -9,32 +9,32 @@ J( L(l12 '10/0') L(l13 '11/0') L(l7) - L(l1) + L(l2) L(l9) - L(l5) + L(l6) L(l10) C(l3 l3 l9) C(l4 l4 l8) - C(l8 l4 l8 l11 l1 l9 l5 l10) + C(l8 l4 l8 l11 l2 l9 l6 l10) C(l11 l8 l11 l12) C(l12 l11 l12 l13) C(l13 l12 l13) C(l7 l7) - C(l1 l8 l1) + C(l2 l8 l2) C(l9 l3 l8 l9) - C(l5 l8 l5) + C(l6 l8 l6) C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) D(D$PMOS PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (450 1500)) + R(l2 (125 -750) (450 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -42,13 +42,13 @@ J( ) D(D$PMOS$1 PMOS T(S - R(l1 (-575 -750) (450 1500)) + R(l2 (-575 -750) (450 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -56,13 +56,13 @@ J( ) D(D$PMOS$2 PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -70,13 +70,13 @@ J( ) D(D$NMOS NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (450 950)) + R(l6 (125 -475) (450 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -84,13 +84,13 @@ J( ) D(D$NMOS$1 NMOS T(S - R(l5 (-575 -475) (450 950)) + R(l6 (-575 -475) (450 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -98,13 +98,13 @@ J( ) D(D$NMOS$2 NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -119,8 +119,8 @@ J( R(l11 (-240 -790) (300 1700)) R(l11 (-1350 0) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l1 (-276 -2151) (425 1500)) - R(l1 (-400 -1500) (425 1500)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) ) N(2 I(OUT) R(l8 (1810 1770) (180 180)) @@ -138,9 +138,9 @@ J( R(l11 (-1751 1099) (300 1400)) R(l11 (1100 -1700) (300 300)) R(l11 (-300 0) (300 1400)) - R(l1 (-375 -1450) (425 1500)) - R(l1 (-1800 -1500) (425 1500)) - R(l5 (950 -4890) (425 950)) + R(l2 (-375 -1450) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -148,7 +148,7 @@ J( R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l5 (-951 859) (425 950)) + R(l6 (-951 859) (425 950)) ) N(4 R(l3 (-100 4500) (2600 3500)) @@ -175,8 +175,8 @@ J( ) N(7 I(SUBSTRATE)) N(8 - R(l5 (975 1660) (425 950)) - R(l5 (-400 -950) (425 950)) + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) ) P(1 I(VDD)) P(2 I(OUT)) @@ -248,7 +248,7 @@ J( R(l11 (-650 300) (1800 800)) R(l11 (-1450 -1100) (300 300)) R(l11 (299 399) (2 2)) - R(l1 (-651 -2151) (425 1500)) + R(l2 (-651 -2151) (425 1500)) ) N(2 I(OUT) R(l8 (1110 5160) (180 180)) @@ -258,8 +258,8 @@ J( R(l8 (-180 370) (180 180)) R(l11 (-240 -790) (300 4790)) R(l11 (-151 -2501) (2 2)) - R(l1 (-226 1049) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -267,7 +267,7 @@ J( R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (1800 800)) R(l11 (-851 -401) (2 2)) - R(l5 (-651 859) (425 950)) + R(l6 (-651 859) (425 950)) ) N(4 R(l3 (-100 4500) (2000 3500)) @@ -321,63 +321,63 @@ J( N(1 R(l8 (4710 3010) (180 180)) R(l11 (-850 -240) (610 300)) - R(l1 (-1175 1800) (425 1500)) - R(l1 (-1800 -1500) (425 1500)) - R(l5 (950 -4890) (425 950)) + R(l2 (-1175 1800) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) ) N(2 R(l8 (6510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 R(l8 (8310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(4 R(l8 (10110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(5 R(l8 (11910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(6 R(l8 (13710 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(7 R(l8 (15510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(8 R(l8 (17310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(9 R(l8 (19110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(10 R(l8 (20910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(11 I(FB) R(l8 (22710 3010) (180 180)) @@ -391,8 +391,8 @@ J( R(l13 (-17921 -201) (2 2)) R(l13 (-221 -201) (400 400)) R(l13 (17740 -400) (400 400)) - R(l1 (-245 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-245 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(12 I(VDD) R(l3 (500 4500) (1400 3500)) @@ -414,19 +414,19 @@ J( R(l11 (-750 -1450) (300 1400)) R(l11 (-101 -351) (2 2)) R(l11 (549 -401) (600 800)) - R(l1 (-23025 -2550) (425 1500)) - R(l1 (-400 -1500) (425 1500)) - R(l1 (1275 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) + R(l2 (-23025 -2550) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + R(l2 (1275 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) R(l9 (-21975 -450) (500 1500)) R(l9 (22900 -1500) (500 1500)) ) @@ -435,8 +435,8 @@ J( R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) - R(l1 (-625 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-625 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(14 I(ENABLE) R(l8 (2510 3010) (180 180)) @@ -461,18 +461,18 @@ J( R(l11 (-750 -1450) (1200 800)) R(l11 (-551 -401) (2 2)) R(l11 (549 -401) (600 800)) - R(l5 (-23700 460) (425 950)) - R(l5 (1975 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) + R(l6 (-23700 460) (425 950)) + R(l6 (1975 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) R(l10 (-21975 -2210) (500 1500)) R(l10 (22900 -1500) (500 1500)) ) @@ -825,8 +825,8 @@ Z( P(5 5 1) P(0 0 1) P(2 2 1) - D(1 1 1) D(2 2 1) + D(1 1 1) ) ) X(ND2X1 ND2X1 1 @@ -846,10 +846,10 @@ Z( P(6 6 1) P(0 0 1) P(2 2 1) - D(1 1 1) - D(2 2 1) D(3 3 1) D(4 4 1) + D(1 1 1) + D(2 2 1) ) ) X(RINGO RINGO 1 @@ -874,10 +874,6 @@ Z( P(2 4 1) P(1 1 1) P(4 0 1) - X(1 1 1) - X(10 10 1) - X(11 11 1) - X(12 12 1) X(2 2 1) X(3 3 1) X(4 4 1) @@ -886,6 +882,10 @@ Z( X(7 7 1) X(8 8 1) X(9 9 1) + X(10 10 1) + X(11 11 1) + X(12 12 1) + X(1 1 1) ) ) ) diff --git a/testdata/lvs/ringo_simple_io2.l2n.1 b/testdata/lvs/ringo_simple_io2.l2n.1 index 7bf5f3726..3d7cc23b1 100644 --- a/testdata/lvs/ringo_simple_io2.l2n.1 +++ b/testdata/lvs/ringo_simple_io2.l2n.1 @@ -8,32 +8,32 @@ L(l11 '9/0') L(l12 '10/0') L(l13 '11/0') L(l7) -L(l1) +L(l2) L(l9) -L(l5) +L(l6) L(l10) C(l3 l3 l9) C(l4 l4 l8) -C(l8 l4 l8 l11 l1 l9 l5 l10) +C(l8 l4 l8 l11 l2 l9 l6 l10) C(l11 l8 l11 l12) C(l12 l11 l12 l13) C(l13 l12 l13) C(l7 l7) -C(l1 l8 l1) +C(l2 l8 l2) C(l9 l3 l8 l9) -C(l5 l8 l5) +C(l6 l8 l6) C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) D(D$PMOS PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (450 1500)) + R(l2 (125 -750) (450 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -41,13 +41,13 @@ D(D$PMOS PMOS ) D(D$PMOS$1 PMOS T(S - R(l1 (-575 -750) (450 1500)) + R(l2 (-575 -750) (450 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -55,13 +55,13 @@ D(D$PMOS$1 PMOS ) D(D$PMOS$2 PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -69,13 +69,13 @@ D(D$PMOS$2 PMOS ) D(D$NMOS NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (450 950)) + R(l6 (125 -475) (450 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -83,13 +83,13 @@ D(D$NMOS NMOS ) D(D$NMOS$1 NMOS T(S - R(l5 (-575 -475) (450 950)) + R(l6 (-575 -475) (450 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -97,13 +97,13 @@ D(D$NMOS$1 NMOS ) D(D$NMOS$2 NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -118,8 +118,8 @@ X(ND2X1 R(l11 (-240 -790) (300 1700)) R(l11 (-1350 0) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l1 (-276 -2151) (425 1500)) - R(l1 (-400 -1500) (425 1500)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) ) N(2 I(OUT) R(l8 (1810 1770) (180 180)) @@ -137,9 +137,9 @@ X(ND2X1 R(l11 (-1751 1099) (300 1400)) R(l11 (1100 -1700) (300 300)) R(l11 (-300 0) (300 1400)) - R(l1 (-1750 -1450) (425 1500)) - R(l1 (950 -1500) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1750 -1450) (425 1500)) + R(l2 (950 -1500) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -147,7 +147,7 @@ X(ND2X1 R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l5 (-951 859) (425 950)) + R(l6 (-951 859) (425 950)) ) N(4 R(l3 (-100 4500) (2600 3500)) @@ -174,8 +174,8 @@ X(ND2X1 ) N(7 I(SUBSTRATE)) N(8 - R(l5 (975 1660) (425 950)) - R(l5 (-400 -950) (425 950)) + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) ) P(1 I(VDD)) P(2 I(OUT)) @@ -247,7 +247,7 @@ X(INVX1 R(l11 (-650 300) (1800 800)) R(l11 (-1450 -1100) (300 300)) R(l11 (299 399) (2 2)) - R(l1 (-651 -2151) (425 1500)) + R(l2 (-651 -2151) (425 1500)) ) N(2 I(OUT) R(l8 (1110 5160) (180 180)) @@ -257,8 +257,8 @@ X(INVX1 R(l8 (-180 370) (180 180)) R(l11 (-240 -790) (300 4790)) R(l11 (-151 -2501) (2 2)) - R(l1 (-226 1049) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -266,7 +266,7 @@ X(INVX1 R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (1800 800)) R(l11 (-851 -401) (2 2)) - R(l5 (-651 859) (425 950)) + R(l6 (-651 859) (425 950)) ) N(4 R(l3 (-100 4500) (2000 3500)) @@ -320,63 +320,63 @@ X(RINGO N(1 R(l8 (4710 3010) (180 180)) R(l11 (-850 -240) (610 300)) - R(l1 (-2550 1800) (425 1500)) - R(l1 (950 -1500) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-2550 1800) (425 1500)) + R(l2 (950 -1500) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(2 R(l8 (6510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 R(l8 (8310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(4 R(l8 (10110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(5 R(l8 (11910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(6 R(l8 (13710 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(7 R(l8 (15510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(8 R(l8 (17310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(9 R(l8 (19110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(10 R(l8 (20910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(11 I(FB) R(l8 (22710 3010) (180 180)) @@ -390,8 +390,8 @@ X(RINGO R(l13 (-17921 -201) (2 2)) R(l13 (-221 -201) (400 400)) R(l13 (17740 -400) (400 400)) - R(l1 (-245 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-245 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(12 I(VDD) R(l3 (500 4500) (1400 3500)) @@ -413,19 +413,19 @@ X(RINGO R(l11 (-750 -1450) (300 1400)) R(l11 (-101 -351) (2 2)) R(l11 (549 -401) (600 800)) - R(l1 (-23025 -2550) (425 1500)) - R(l1 (-400 -1500) (425 1500)) - R(l1 (1275 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) + R(l2 (-23025 -2550) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + R(l2 (1275 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) R(l9 (-21975 -450) (500 1500)) R(l9 (22900 -1500) (500 1500)) ) @@ -434,8 +434,8 @@ X(RINGO R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) - R(l1 (-625 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-625 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(14 I(ENABLE) R(l8 (2510 3010) (180 180)) @@ -460,18 +460,18 @@ X(RINGO R(l11 (-750 -1450) (1200 800)) R(l11 (-551 -401) (2 2)) R(l11 (549 -401) (600 800)) - R(l5 (-23700 460) (425 950)) - R(l5 (1975 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) + R(l6 (-23700 460) (425 950)) + R(l6 (1975 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) R(l10 (-21975 -2210) (500 1500)) R(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_io2.l2n.2 b/testdata/lvs/ringo_simple_io2.l2n.2 index 9c5f6aa2a..715c73183 100644 --- a/testdata/lvs/ringo_simple_io2.l2n.2 +++ b/testdata/lvs/ringo_simple_io2.l2n.2 @@ -8,32 +8,32 @@ L(l11 '9/0') L(l12 '10/0') L(l13 '11/0') L(l7) -L(l1) +L(l2) L(l9) -L(l5) +L(l6) L(l10) C(l3 l3 l9) C(l4 l4 l8) -C(l8 l4 l8 l11 l1 l9 l5 l10) +C(l8 l4 l8 l11 l2 l9 l6 l10) C(l11 l8 l11 l12) C(l12 l11 l12 l13) C(l13 l12 l13) C(l7 l7) -C(l1 l8 l1) +C(l2 l8 l2) C(l9 l3 l8 l9) -C(l5 l8 l5) +C(l6 l8 l6) C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) D(D$PMOS PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (450 1500)) + R(l2 (125 -750) (450 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -41,13 +41,13 @@ D(D$PMOS PMOS ) D(D$PMOS$1 PMOS T(S - R(l1 (-575 -750) (450 1500)) + R(l2 (-575 -750) (450 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -55,13 +55,13 @@ D(D$PMOS$1 PMOS ) D(D$PMOS$2 PMOS T(S - R(l1 (-550 -750) (425 1500)) + R(l2 (-550 -750) (425 1500)) ) T(G R(l4 (-125 -750) (250 1500)) ) T(D - R(l1 (125 -750) (425 1500)) + R(l2 (125 -750) (425 1500)) ) T(B R(l3 (-125 -750) (250 1500)) @@ -69,13 +69,13 @@ D(D$PMOS$2 PMOS ) D(D$NMOS NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (450 950)) + R(l6 (125 -475) (450 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -83,13 +83,13 @@ D(D$NMOS NMOS ) D(D$NMOS$1 NMOS T(S - R(l5 (-575 -475) (450 950)) + R(l6 (-575 -475) (450 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -97,13 +97,13 @@ D(D$NMOS$1 NMOS ) D(D$NMOS$2 NMOS T(S - R(l5 (-550 -475) (425 950)) + R(l6 (-550 -475) (425 950)) ) T(G R(l4 (-125 -475) (250 950)) ) T(D - R(l5 (125 -475) (425 950)) + R(l6 (125 -475) (425 950)) ) T(B R(l7 (-125 -475) (250 950)) @@ -118,8 +118,8 @@ X(ND2X1 R(l11 (-240 -790) (300 1700)) R(l11 (-1350 0) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l1 (-276 -2151) (425 1500)) - R(l1 (-400 -1500) (425 1500)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) ) N(2 I(OUT) R(l8 (1810 1770) (180 180)) @@ -137,9 +137,9 @@ X(ND2X1 R(l11 (-1751 1099) (300 1400)) R(l11 (1100 -1700) (300 300)) R(l11 (-300 0) (300 1400)) - R(l1 (-375 -1450) (425 1500)) - R(l1 (-1800 -1500) (425 1500)) - R(l5 (950 -4890) (425 950)) + R(l2 (-375 -1450) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -147,7 +147,7 @@ X(ND2X1 R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (2400 800)) R(l11 (-1151 -401) (2 2)) - R(l5 (-951 859) (425 950)) + R(l6 (-951 859) (425 950)) ) N(4 R(l3 (-100 4500) (2600 3500)) @@ -174,8 +174,8 @@ X(ND2X1 ) N(7 I(SUBSTRATE)) N(8 - R(l5 (975 1660) (425 950)) - R(l5 (-400 -950) (425 950)) + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) ) P(1 I(VDD)) P(2 I(OUT)) @@ -247,7 +247,7 @@ X(INVX1 R(l11 (-650 300) (1800 800)) R(l11 (-1450 -1100) (300 300)) R(l11 (299 399) (2 2)) - R(l1 (-651 -2151) (425 1500)) + R(l2 (-651 -2151) (425 1500)) ) N(2 I(OUT) R(l8 (1110 5160) (180 180)) @@ -257,8 +257,8 @@ X(INVX1 R(l8 (-180 370) (180 180)) R(l11 (-240 -790) (300 4790)) R(l11 (-151 -2501) (2 2)) - R(l1 (-226 1049) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 I(VSS) R(l8 (410 1770) (180 180)) @@ -266,7 +266,7 @@ X(INVX1 R(l11 (-240 -1300) (300 1360)) R(l11 (-650 -2160) (1800 800)) R(l11 (-851 -401) (2 2)) - R(l5 (-651 859) (425 950)) + R(l6 (-651 859) (425 950)) ) N(4 R(l3 (-100 4500) (2000 3500)) @@ -320,63 +320,63 @@ X(RINGO N(1 R(l8 (4710 3010) (180 180)) R(l11 (-850 -240) (610 300)) - R(l1 (-1175 1800) (425 1500)) - R(l1 (-1800 -1500) (425 1500)) - R(l5 (950 -4890) (425 950)) + R(l2 (-1175 1800) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) ) N(2 R(l8 (6510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(3 R(l8 (8310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(4 R(l8 (10110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(5 R(l8 (11910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(6 R(l8 (13710 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(7 R(l8 (15510 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(8 R(l8 (17310 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(9 R(l8 (19110 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(10 R(l8 (20910 3010) (180 180)) R(l11 (-1140 -240) (900 300)) - R(l1 (-1275 1800) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-1275 1800) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(11 I(FB) R(l8 (22710 3010) (180 180)) @@ -390,8 +390,8 @@ X(RINGO R(l13 (-17921 -201) (2 2)) R(l13 (-221 -201) (400 400)) R(l13 (17740 -400) (400 400)) - R(l1 (-245 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-245 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(12 I(VDD) R(l3 (500 4500) (1400 3500)) @@ -413,19 +413,19 @@ X(RINGO R(l11 (-750 -1450) (300 1400)) R(l11 (-101 -351) (2 2)) R(l11 (549 -401) (600 800)) - R(l1 (-23025 -2550) (425 1500)) - R(l1 (-400 -1500) (425 1500)) - R(l1 (1275 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) - R(l1 (1375 -1500) (425 1500)) + R(l2 (-23025 -2550) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + R(l2 (1275 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) + R(l2 (1375 -1500) (425 1500)) R(l9 (-21975 -450) (500 1500)) R(l9 (22900 -1500) (500 1500)) ) @@ -434,8 +434,8 @@ X(RINGO R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) - R(l1 (-625 850) (425 1500)) - R(l5 (-425 -4890) (425 950)) + R(l2 (-625 850) (425 1500)) + R(l6 (-425 -4890) (425 950)) ) N(14 I(ENABLE) R(l8 (2510 3010) (180 180)) @@ -460,18 +460,18 @@ X(RINGO R(l11 (-750 -1450) (1200 800)) R(l11 (-551 -401) (2 2)) R(l11 (549 -401) (600 800)) - R(l5 (-23700 460) (425 950)) - R(l5 (1975 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) - R(l5 (1375 -950) (425 950)) + R(l6 (-23700 460) (425 950)) + R(l6 (1975 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) + R(l6 (1375 -950) (425 950)) R(l10 (-21975 -2210) (500 1500)) R(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.1 b/testdata/lvs/ringo_simple_io2.lvsdb.1 index 9ed4f2480..a68dae475 100644 --- a/testdata/lvs/ringo_simple_io2.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io2.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-2550 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.2 b/testdata/lvs/ringo_simple_io2.lvsdb.2 index 2d8585635..834cc43fe 100644 --- a/testdata/lvs/ringo_simple_io2.lvsdb.2 +++ b/testdata/lvs/ringo_simple_io2.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-1175 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 index 925edd988..bee7ccfc8 100644 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-2550 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(nd2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(top RINGO match @@ -953,10 +953,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -965,6 +961,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 index 4930f20f1..f57553a48 100644 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-1175 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(nd2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(top RINGO match @@ -953,10 +953,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -965,6 +961,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 index 2315835c9..4c98e224d 100644 --- a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 +++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-2550 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 index 57fb8a644..45cc8683d 100644 --- a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 +++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-1175 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 index 8027c048c..7fc246d6a 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PM PM terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PM$1 PM terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PM$2 PM terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NM NM terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NM$1 NM terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NM$2 NM terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-2550 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 index 847ff7f63..7ea0be0cd 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PM PM terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PM$1 PM terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PM$2 PM terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NM NM terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NM$1 NM terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NM$2 NM terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -364,63 +364,63 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-1175 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (10110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 rect(l8 (11910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 rect(l8 (13710 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(7 rect(l8 (15510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(8 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(9 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(10 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 name(FB) rect(l8 (22710 3010) (180 180)) @@ -434,8 +434,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,19 +457,19 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23025 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) + rect(l2 (-23025 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) rect(l9 (-21975 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -478,8 +478,8 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -504,18 +504,18 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-23700 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) + rect(l6 (-23700 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) rect(l10 (-21975 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) @@ -905,8 +905,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -926,10 +926,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -954,10 +954,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) circuit(2 2 match) circuit(3 3 match) circuit(4 4 match) @@ -966,6 +962,10 @@ xref( circuit(7 7 match) circuit(8 8 match) circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.1 b/testdata/lvs/ringo_simple_simplification.lvsdb.1 index 278aa58a8..b0e4b5871 100644 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.1 +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.1 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -389,8 +389,8 @@ layout( rect(l11 (1100 -300) (300 300)) rect(l11 (-1101 399) (2 2)) rect(l11 (799 -2101) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) ) net(3 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -400,10 +400,10 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l5 (-450 -4890) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) ) net(4 name(VSS) rect(l8 (410 1770) (180 180)) @@ -414,8 +414,8 @@ layout( rect(l11 (-650 -2160) (2400 800)) rect(l11 (-650 0) (300 1360)) rect(l11 (-1101 -1761) (2 2)) - rect(l5 (-651 859) (425 950)) - rect(l5 (950 -950) (425 950)) + rect(l6 (-651 859) (425 950)) + rect(l6 (950 -950) (425 950)) ) net(5 rect(l3 (-100 4500) (2600 3500)) @@ -486,27 +486,27 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-2550 1800) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 name(FB) rect(l8 (22710 3010) (180 180)) @@ -520,8 +520,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 name(VDD) rect(l3 (1100 4500) (1400 3500)) @@ -543,20 +543,20 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23625 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (3175 -1500) (425 1500)) - rect(l1 (-2225 -1500) (425 1500)) - rect(l1 (3175 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (3175 -1500) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l1 (-3600 -1500) (425 1500)) + rect(l2 (-23625 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l2 (-3600 -1500) (425 1500)) rect(l9 (-19575 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -565,10 +565,10 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l5 (-450 -4890) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) ) net(8 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -593,38 +593,58 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-24300 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (3175 -950) (425 950)) - rect(l5 (-2225 -950) (425 950)) - rect(l5 (3175 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (3175 -950) (425 950)) - rect(l5 (950 -950) (425 950)) - rect(l5 (-3600 -950) (425 950)) + rect(l6 (-24300 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (950 -950) (425 950)) + rect(l6 (-3600 -950) (425 950)) rect(l10 (-19575 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) net(10 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) - net(12) - net(13) - net(14) - net(15) # Outgoing pins and their connections to nets pin(5 name(FB)) @@ -1058,8 +1078,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(INVX2 INVX2 match @@ -1076,8 +1096,8 @@ xref( pin(5 5 match) pin(1 0 match) pin(3 2 match) - device(1 1 match) device(3 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -1097,10 +1117,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -1125,10 +1145,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) circuit(2 2 match) circuit(3 3 match) circuit(17 4 match) @@ -1137,6 +1153,10 @@ xref( circuit(20 7 match) circuit(21 8 match) circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.2 b/testdata/lvs/ringo_simple_simplification.lvsdb.2 index 169191238..2492067a3 100644 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.2 +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.2 @@ -16,22 +16,22 @@ layout( layer(l12 '10/0') layer(l13 '11/0') layer(l7) - layer(l1) + layer(l2) layer(l9) - layer(l5) + layer(l6) layer(l10) # Mask layer connectivity connect(l3 l3 l9) connect(l4 l4 l8) - connect(l8 l4 l8 l11 l1 l9 l5 l10) + connect(l8 l4 l8 l11 l2 l9 l6 l10) connect(l11 l8 l11 l12) connect(l12 l11 l12 l13) connect(l13 l12 l13) connect(l7 l7) - connect(l1 l8 l1) + connect(l2 l8 l2) connect(l9 l3 l8 l9) - connect(l5 l8 l5) + connect(l6 l8 l6) connect(l10 l8 l10) # Global nets and connectivity @@ -46,13 +46,13 @@ layout( # Device abstracts list the pin shapes of the devices. device(D$PMOS PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (450 1500)) + rect(l2 (125 -750) (450 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -60,13 +60,13 @@ layout( ) device(D$PMOS$1 PMOS terminal(S - rect(l1 (-575 -750) (450 1500)) + rect(l2 (-575 -750) (450 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -74,13 +74,13 @@ layout( ) device(D$PMOS$2 PMOS terminal(S - rect(l1 (-550 -750) (425 1500)) + rect(l2 (-550 -750) (425 1500)) ) terminal(G rect(l4 (-125 -750) (250 1500)) ) terminal(D - rect(l1 (125 -750) (425 1500)) + rect(l2 (125 -750) (425 1500)) ) terminal(B rect(l3 (-125 -750) (250 1500)) @@ -88,13 +88,13 @@ layout( ) device(D$NMOS NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (450 950)) + rect(l6 (125 -475) (450 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -102,13 +102,13 @@ layout( ) device(D$NMOS$1 NMOS terminal(S - rect(l5 (-575 -475) (450 950)) + rect(l6 (-575 -475) (450 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -116,13 +116,13 @@ layout( ) device(D$NMOS$2 NMOS terminal(S - rect(l5 (-550 -475) (425 950)) + rect(l6 (-550 -475) (425 950)) ) terminal(G rect(l4 (-125 -475) (250 950)) ) terminal(D - rect(l5 (125 -475) (425 950)) + rect(l6 (125 -475) (425 950)) ) terminal(B rect(l7 (-125 -475) (250 950)) @@ -144,8 +144,8 @@ layout( rect(l11 (-240 -790) (300 1700)) rect(l11 (-1350 0) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l1 (-276 -2151) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) ) net(2 name(OUT) rect(l8 (1810 1770) (180 180)) @@ -163,9 +163,9 @@ layout( rect(l11 (-1751 1099) (300 1400)) rect(l11 (1100 -1700) (300 300)) rect(l11 (-300 0) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -173,7 +173,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (2400 800)) rect(l11 (-1151 -401) (2 2)) - rect(l5 (-951 859) (425 950)) + rect(l6 (-951 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2600 3500)) @@ -200,8 +200,8 @@ layout( ) net(7 name(SUBSTRATE)) net(8 - rect(l5 (975 1660) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -282,7 +282,7 @@ layout( rect(l11 (-650 300) (1800 800)) rect(l11 (-1450 -1100) (300 300)) rect(l11 (299 399) (2 2)) - rect(l1 (-651 -2151) (425 1500)) + rect(l2 (-651 -2151) (425 1500)) ) net(2 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -292,8 +292,8 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 name(VSS) rect(l8 (410 1770) (180 180)) @@ -301,7 +301,7 @@ layout( rect(l11 (-240 -1300) (300 1360)) rect(l11 (-650 -2160) (1800 800)) rect(l11 (-851 -401) (2 2)) - rect(l5 (-651 859) (425 950)) + rect(l6 (-651 859) (425 950)) ) net(4 rect(l3 (-100 4500) (2000 3500)) @@ -389,8 +389,8 @@ layout( rect(l11 (1100 -300) (300 300)) rect(l11 (-1101 399) (2 2)) rect(l11 (799 -2101) (300 1400)) - rect(l1 (-375 -1450) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) ) net(3 name(OUT) rect(l8 (1110 5160) (180 180)) @@ -400,10 +400,10 @@ layout( rect(l8 (-180 370) (180 180)) rect(l11 (-240 -790) (300 4790)) rect(l11 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l5 (-450 -4890) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) ) net(4 name(VSS) rect(l8 (410 1770) (180 180)) @@ -414,8 +414,8 @@ layout( rect(l11 (-650 -2160) (2400 800)) rect(l11 (-650 0) (300 1360)) rect(l11 (-1101 -1761) (2 2)) - rect(l5 (724 859) (425 950)) - rect(l5 (-1800 -950) (425 950)) + rect(l6 (724 859) (425 950)) + rect(l6 (-1800 -950) (425 950)) ) net(5 rect(l3 (-100 4500) (2600 3500)) @@ -486,27 +486,27 @@ layout( net(1 rect(l8 (4710 3010) (180 180)) rect(l11 (-850 -240) (610 300)) - rect(l1 (-1175 1800) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l5 (950 -4890) (425 950)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) ) net(2 rect(l8 (6510 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(3 rect(l8 (19110 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(4 rect(l8 (20910 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(5 name(FB) rect(l8 (22710 3010) (180 180)) @@ -520,8 +520,8 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l1 (-245 850) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(6 name(VDD) rect(l3 (1100 4500) (1400 3500)) @@ -543,20 +543,20 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l1 (-23625 -2550) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l1 (1275 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (3175 -1500) (425 1500)) - rect(l1 (-2225 -1500) (425 1500)) - rect(l1 (3175 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (1375 -1500) (425 1500)) - rect(l1 (4550 -1500) (425 1500)) - rect(l1 (-1800 -1500) (425 1500)) - rect(l1 (-2225 -1500) (425 1500)) + rect(l2 (-23625 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (4550 -1500) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) rect(l9 (-19575 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) @@ -565,10 +565,10 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l1 (-625 850) (425 1500)) - rect(l1 (-400 -1500) (425 1500)) - rect(l5 (-450 -4890) (425 950)) - rect(l5 (-400 -950) (425 950)) + rect(l2 (-625 850) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) ) net(8 name(ENABLE) rect(l8 (2510 3010) (180 180)) @@ -593,38 +593,58 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l5 (-24300 460) (425 950)) - rect(l5 (1975 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (3175 -950) (425 950)) - rect(l5 (-2225 -950) (425 950)) - rect(l5 (3175 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (1375 -950) (425 950)) - rect(l5 (4550 -950) (425 950)) - rect(l5 (-1800 -950) (425 950)) - rect(l5 (-2225 -950) (425 950)) + rect(l6 (-24300 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (4550 -950) (425 950)) + rect(l6 (-1800 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) rect(l10 (-19575 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) net(10 rect(l8 (8310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) net(11 rect(l8 (17310 3010) (180 180)) rect(l11 (-1140 -240) (900 300)) - rect(l1 (-1275 1800) (425 1500)) - rect(l5 (-425 -4890) (425 950)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) ) - net(12) - net(13) - net(14) - net(15) # Outgoing pins and their connections to nets pin(5 name(FB)) @@ -1058,8 +1078,8 @@ xref( pin(5 5 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) device(2 2 match) + device(1 1 match) ) ) circuit(INVX2 INVX2 match @@ -1076,8 +1096,8 @@ xref( pin(5 5 match) pin(1 0 match) pin(3 2 match) - device(1 1 match) device(3 2 match) + device(1 1 match) ) ) circuit(ND2X1 ND2X1 match @@ -1097,10 +1117,10 @@ xref( pin(6 6 match) pin(0 0 match) pin(2 2 match) - device(1 1 match) - device(2 2 match) device(3 3 match) device(4 4 match) + device(1 1 match) + device(2 2 match) ) ) circuit(RINGO RINGO match @@ -1125,10 +1145,6 @@ xref( pin(2 4 match) pin(1 1 match) pin(4 0 match) - circuit(1 1 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) circuit(2 2 match) circuit(3 3 match) circuit(17 4 match) @@ -1137,6 +1153,10 @@ xref( circuit(20 7 match) circuit(21 8 match) circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.cir b/testdata/lvs/ringo_simple_simplification_with_align.cir new file mode 100644 index 000000000..c24088217 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification_with_align.cir @@ -0,0 +1,102 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 5 6 7 8 9 +* net 5 FB +* net 6 VDD +* net 7 OUT +* net 8 ENABLE +* net 9 VSS +* cell instance $1 r0 *1 1.8,0 +X$1 6 1 9 6 5 8 9 ND2X1 +* cell instance $2 r0 *1 4.2,0 +X$2 6 2 9 6 1 9 INVX1 +* cell instance $3 r0 *1 6,0 +X$3 6 10 9 6 2 9 INVX1 +* cell instance $4 r0 *1 16.8,0 +X$4 6 3 9 6 11 9 INVX1 +* cell instance $5 r0 *1 18.6,0 +X$5 6 4 9 6 3 9 INVX1 +* cell instance $6 r0 *1 20.4,0 +X$6 6 5 9 6 4 9 INVX1 +* cell instance $7 r0 *1 22.2,0 +X$7 5 6 7 9 6 9 INVX2 +* cell instance $17 r0 *1 7.8,0 +X$17 6 12 9 6 10 9 INVX1 +* cell instance $18 r0 *1 9.6,0 +X$18 6 13 9 6 12 9 INVX1 +* cell instance $19 r0 *1 11.4,0 +X$19 6 14 9 6 13 9 INVX1 +* cell instance $20 r0 *1 13.2,0 +X$20 6 15 9 6 14 9 INVX1 +* cell instance $21 r0 *1 15,0 +X$21 6 11 9 6 15 9 INVX1 +.ENDS RINGO + +* cell INVX2 +* pin IN +* pin VDD +* pin OUT +* pin VSS +* pin +* pin SUBSTRATE +.SUBCKT INVX2 1 2 3 4 5 6 +* net 1 IN +* net 2 VDD +* net 3 OUT +* net 4 VSS +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U +.ENDS INVX2 + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 4 5 6 7 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 B +* net 6 A +* net 7 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +* device instance $4 r0 *1 1.55,2.135 NMOS +M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvs b/testdata/lvs/ringo_simple_simplification_with_align.lvs new file mode 100644 index 000000000..4591cf3e6 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvs @@ -0,0 +1,76 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("ringo_for_simplification.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, contact) +connect(nsd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +align + +netlist.simplify + +compare + diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 new file mode 100644 index 000000000..b0e4b5871 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 @@ -0,0 +1,1162 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-225 -1300) (675 450)) + rect(l4 (0 -1100) (250 1950)) + rect(l4 (-1225 -1850) (300 300)) + rect(l4 (675 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-950 -2000) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (450 -5390) (250 1450)) + rect(l4 (-950 -1450) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(2 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-1640 -240) (300 1400)) + rect(l11 (-650 300) (2400 800)) + rect(l11 (-2050 -1100) (300 300)) + rect(l11 (1100 -300) (300 300)) + rect(l11 (-1101 399) (2 2)) + rect(l11 (799 -2101) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + ) + net(3 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(4 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (1220 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-1640 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-650 0) (300 1360)) + rect(l11 (-1101 -1761) (2 2)) + rect(l6 (-651 859) (425 950)) + rect(l6 (950 -950) (425 950)) + ) + net(5 + rect(l3 (-100 4500) (2600 3500)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(IN)) + pin(2 name(VDD)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 5800) + param(L 0.25) + param(W 3) + param(AS 0.975) + param(AD 0.975) + param(PS 5.8) + param(PD 5.8) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 5) + ) + device(3 D$NMOS + device(D$NMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 2135) + param(L 0.25) + param(W 1.9) + param(AS 0.6175) + param(AD 0.6175) + param(PS 4.15) + param(PD 4.15) + terminal(S 4) + terminal(G 1) + terminal(D 3) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((600 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-2550 1800) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(2 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 name(VDD) + rect(l3 (1100 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-22341 859) (2 2)) + rect(l11 (-1751 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23625 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l2 (-3600 -1500) (425 1500)) + rect(l9 (-19575 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(7 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(8 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(9 name(VSS) + rect(l8 (1710 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22341 -391) (2 2)) + rect(l11 (-1301 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-24300 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (950 -950) (425 950)) + rect(l6 (-3600 -950) (425 950)) + rect(l10 (-19575 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + net(10 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(5 name(FB)) + pin(6 name(VDD)) + pin(7 name(OUT)) + pin(8 name(ENABLE)) + pin(9 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 6) + pin(1 1) + pin(2 9) + pin(3 6) + pin(4 5) + pin(5 8) + pin(6 9) + ) + circuit(2 INVX1 location(4200 0) + pin(0 6) + pin(1 2) + pin(2 9) + pin(3 6) + pin(4 1) + pin(5 9) + ) + circuit(3 INVX1 location(6000 0) + pin(0 6) + pin(1 10) + pin(2 9) + pin(3 6) + pin(4 2) + pin(5 9) + ) + circuit(4 INVX1 location(16800 0) + pin(0 6) + pin(1 3) + pin(2 9) + pin(3 6) + pin(4 11) + pin(5 9) + ) + circuit(5 INVX1 location(18600 0) + pin(0 6) + pin(1 4) + pin(2 9) + pin(3 6) + pin(4 3) + pin(5 9) + ) + circuit(6 INVX1 location(20400 0) + pin(0 6) + pin(1 5) + pin(2 9) + pin(3 6) + pin(4 4) + pin(5 9) + ) + circuit(7 INVX2 location(22200 0) + pin(0 5) + pin(1 6) + pin(2 7) + pin(3 9) + pin(4 6) + pin(5 9) + ) + circuit(17 INVX1 location(7800 0) + pin(0 6) + pin(1 12) + pin(2 9) + pin(3 6) + pin(4 10) + pin(5 9) + ) + circuit(18 INVX1 location(9600 0) + pin(0 6) + pin(1 13) + pin(2 9) + pin(3 6) + pin(4 12) + pin(5 9) + ) + circuit(19 INVX1 location(11400 0) + pin(0 6) + pin(1 14) + pin(2 9) + pin(3 6) + pin(4 13) + pin(5 9) + ) + circuit(20 INVX1 location(13200 0) + pin(0 6) + pin(1 15) + pin(2 9) + pin(3 6) + pin(4 14) + pin(5 9) + ) + circuit(21 INVX1 location(15000 0) + pin(0 6) + pin(1 11) + pin(2 9) + pin(3 6) + pin(4 15) + pin(5 9) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX2 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX2 INVX2 match + xref( + net(5 4 match) + net(1 5 match) + net(3 2 match) + net(6 6 match) + net(2 1 match) + net(4 3 match) + pin(4 3 match) + pin(0 4 match) + pin(2 1 match) + pin(5 5 match) + pin(1 0 match) + pin(3 2 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(4 15 match) + net(2 7 match) + net(10 8 match) + net(12 9 match) + net(13 10 match) + net(14 11 match) + net(15 12 match) + net(11 13 match) + net(3 14 match) + net(8 4 match) + net(5 3 match) + net(7 5 match) + net(6 2 match) + net(9 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(17 4 match) + circuit(18 5 match) + circuit(19 6 match) + circuit(20 7 match) + circuit(21 8 match) + circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 new file mode 100644 index 000000000..2492067a3 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 @@ -0,0 +1,1162 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-225 -1300) (675 450)) + rect(l4 (0 -1100) (250 1950)) + rect(l4 (-1225 -1850) (300 300)) + rect(l4 (675 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-950 -2000) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (450 -5390) (250 1450)) + rect(l4 (-950 -1450) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(2 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-1640 -240) (300 1400)) + rect(l11 (-650 300) (2400 800)) + rect(l11 (-2050 -1100) (300 300)) + rect(l11 (1100 -300) (300 300)) + rect(l11 (-1101 399) (2 2)) + rect(l11 (799 -2101) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + ) + net(3 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(4 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (1220 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-1640 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-650 0) (300 1360)) + rect(l11 (-1101 -1761) (2 2)) + rect(l6 (724 859) (425 950)) + rect(l6 (-1800 -950) (425 950)) + ) + net(5 + rect(l3 (-100 4500) (2600 3500)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(IN)) + pin(2 name(VDD)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 5800) + param(L 0.25) + param(W 3) + param(AS 0.975) + param(AD 0.975) + param(PS 5.8) + param(PD 5.8) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 5) + ) + device(3 D$NMOS + device(D$NMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 2135) + param(L 0.25) + param(W 1.9) + param(AS 0.6175) + param(AD 0.6175) + param(PS 4.15) + param(PD 4.15) + terminal(S 4) + terminal(G 1) + terminal(D 3) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((600 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l8 (4710 3010) (180 180)) + rect(l11 (-850 -240) (610 300)) + rect(l2 (-1175 1800) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(2 + rect(l8 (6510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 + rect(l8 (19110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(4 + rect(l8 (20910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(5 name(FB) + rect(l8 (22710 3010) (180 180)) + rect(l8 (-19700 720) (180 180)) + rect(l11 (18380 -1140) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + rect(l2 (-245 850) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(6 name(VDD) + rect(l3 (1100 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-22341 859) (2 2)) + rect(l11 (-1751 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l2 (-23625 -2550) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l2 (1275 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l2 (3175 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (1375 -1500) (425 1500)) + rect(l2 (4550 -1500) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l2 (-2225 -1500) (425 1500)) + rect(l9 (-19575 -450) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(7 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + rect(l2 (-625 850) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(8 name(ENABLE) + rect(l8 (2510 3010) (180 180)) + rect(l11 (-250 -250) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(9 name(VSS) + rect(l8 (1710 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22341 -391) (2 2)) + rect(l11 (-1301 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l6 (-24300 460) (425 950)) + rect(l6 (1975 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l6 (3175 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (1375 -950) (425 950)) + rect(l6 (4550 -950) (425 950)) + rect(l6 (-1800 -950) (425 950)) + rect(l6 (-2225 -950) (425 950)) + rect(l10 (-19575 -2210) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + net(10 + rect(l8 (8310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(11 + rect(l8 (17310 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(12 + rect(l8 (10110 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(13 + rect(l8 (11910 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(14 + rect(l8 (13710 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(15 + rect(l8 (15510 3010) (180 180)) + rect(l11 (-1140 -240) (900 300)) + rect(l2 (-1275 1800) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(5 name(FB)) + pin(6 name(VDD)) + pin(7 name(OUT)) + pin(8 name(ENABLE)) + pin(9 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 6) + pin(1 1) + pin(2 9) + pin(3 6) + pin(4 5) + pin(5 8) + pin(6 9) + ) + circuit(2 INVX1 location(4200 0) + pin(0 6) + pin(1 2) + pin(2 9) + pin(3 6) + pin(4 1) + pin(5 9) + ) + circuit(3 INVX1 location(6000 0) + pin(0 6) + pin(1 10) + pin(2 9) + pin(3 6) + pin(4 2) + pin(5 9) + ) + circuit(4 INVX1 location(16800 0) + pin(0 6) + pin(1 3) + pin(2 9) + pin(3 6) + pin(4 11) + pin(5 9) + ) + circuit(5 INVX1 location(18600 0) + pin(0 6) + pin(1 4) + pin(2 9) + pin(3 6) + pin(4 3) + pin(5 9) + ) + circuit(6 INVX1 location(20400 0) + pin(0 6) + pin(1 5) + pin(2 9) + pin(3 6) + pin(4 4) + pin(5 9) + ) + circuit(7 INVX2 location(22200 0) + pin(0 5) + pin(1 6) + pin(2 7) + pin(3 9) + pin(4 6) + pin(5 9) + ) + circuit(17 INVX1 location(7800 0) + pin(0 6) + pin(1 12) + pin(2 9) + pin(3 6) + pin(4 10) + pin(5 9) + ) + circuit(18 INVX1 location(9600 0) + pin(0 6) + pin(1 13) + pin(2 9) + pin(3 6) + pin(4 12) + pin(5 9) + ) + circuit(19 INVX1 location(11400 0) + pin(0 6) + pin(1 14) + pin(2 9) + pin(3 6) + pin(4 13) + pin(5 9) + ) + circuit(20 INVX1 location(13200 0) + pin(0 6) + pin(1 15) + pin(2 9) + pin(3 6) + pin(4 14) + pin(5 9) + ) + circuit(21 INVX1 location(15000 0) + pin(0 6) + pin(1 11) + pin(2 9) + pin(3 6) + pin(4 15) + pin(5 9) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX2 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX2 INVX2 match + xref( + net(5 4 match) + net(1 5 match) + net(3 2 match) + net(6 6 match) + net(2 1 match) + net(4 3 match) + pin(4 3 match) + pin(0 4 match) + pin(2 1 match) + pin(5 5 match) + pin(1 0 match) + pin(3 2 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(4 15 match) + net(2 7 match) + net(10 8 match) + net(12 9 match) + net(13 10 match) + net(14 11 match) + net(15 12 match) + net(11 13 match) + net(3 14 match) + net(8 4 match) + net(5 3 match) + net(7 5 match) + net(6 2 match) + net(9 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(17 4 match) + circuit(18 5 match) + circuit(19 6 match) + circuit(20 7 match) + circuit(21 8 match) + circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/vexriscv_align.lvs b/testdata/lvs/vexriscv_align.lvs new file mode 100644 index 000000000..194924b80 --- /dev/null +++ b/testdata/lvs/vexriscv_align.lvs @@ -0,0 +1,111 @@ + +source($lvs_test_source) + +# will get pretty big: +# report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice(true), "Extracted by KLayout") + +schematic("vexriscv_schematic.cir.gz") + +deep + +# Drawing layers + +nwell = input(1, 0) +pactive = input(4, 0) +nactive = input(3, 0) +ntie = input(5, 0) +ptie = input(6, 0) + +poly = input(7, 0) +cont = input(10, 0) +metal1 = input(11, 0) +via1 = input(14, 0) +metal2 = input(16, 0) +via2 = input(18, 0) +metal3 = input(19, 0) +via3 = input(21, 0) +metal4 = input(22, 0) +via4 = input(25, 0) +metal5 = input(26, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +poly_cont = cont & poly +diff_cont = cont - poly + +pgate = pactive & poly +psd = pactive - pgate + +ngate = nactive & poly +nsd = nactive - ngate + +# Device extraction + +# PMOS transistor device extraction +extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, + "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, + "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(psd, diff_cont) +connect(nsd, diff_cont) +connect(poly, poly_cont) +connect(poly_cont, metal1) +connect(diff_cont, metal1) +connect(diff_cont, ntie) +connect(diff_cont, ptie) +connect(nwell, ntie) +connect(metal1, via1) +connect(via1, metal2) +connect(metal2, via2) +connect(via2, metal3) +connect(metal3, via3) +connect(via3, metal4) +connect(metal4, via4) +connect(via4, metal5) + +# Global +connect_global(ptie, "BULK") +connect_global(bulk, "BULK") + +# Implicit +connect_implicit("VDD") +connect_implicit("VSS") + +# Compare section + +same_device_classes("PMOS", "TP") +same_device_classes("NMOS", "TN") + +# Ignore all caps from the schematic +same_device_classes(nil, "CAP") + +# Increase the default complexity from 100 to 200 +# This is required because the clock tree is incorrect and exhibits manifold ambiguities +# (the netlists are just samples, not necessarily functional). +# The algorithm needs enough freedom to follow all these branches and different variants. +max_branch_complexity(200) + +schematic.combine_devices + +netlist.combine_devices + +align + +if ! compare + raise "Netlists don't match" +else + puts "Congratulations! Netlists match." +end + diff --git a/testdata/ruby/dbNetlistCompare.rb b/testdata/ruby/dbNetlistCompare.rb index 4b383acc6..be77f5bb4 100644 --- a/testdata/ruby/dbNetlistCompare.rb +++ b/testdata/ruby/dbNetlistCompare.rb @@ -954,8 +954,8 @@ match_pins $2 $0 match_pins $3 $2 match_devices $3 $1 match_devices_with_different_parameters $2 $2 -device_mismatch (null) $3 match_devices $1 $4 +device_mismatch (null) $3 end_circuit INV INV NOMATCH END