diff --git a/src/db/db/dbLayoutToNetlist.cc b/src/db/db/dbLayoutToNetlist.cc
index af2026460..0e2adb5d0 100644
--- a/src/db/db/dbLayoutToNetlist.cc
+++ b/src/db/db/dbLayoutToNetlist.cc
@@ -336,7 +336,6 @@ LayoutToNetlist::build_net (const db::Net &net, db::Layout &target, db::Cell &ta
   }
 
   std::map<std::pair<db::cell_index_type, size_t>, db::cell_index_type> cell_map;
-  cell_map.insert (std::make_pair (std::make_pair (net.circuit ()->cell_index (), net.cluster_id ()), target_cell.cell_index ()));
 
   build_net_rec (net, target, target_cell, lmap, cell_name_prefix, cell_map);
 }
@@ -348,6 +347,8 @@ LayoutToNetlist::build_all_nets (const db::CellMapping &cmap, db::Layout &target
     throw tl::Exception (tl::to_string (tr ("The netlist has not been extracted yet")));
   }
 
+  std::map<std::pair<db::cell_index_type, size_t>, db::cell_index_type> cell_map;
+
   const db::Netlist *netlist = mp_netlist.get ();
   for (db::Netlist::const_circuit_iterator c = netlist->begin_circuits (); c != netlist->end_circuits (); ++c) {
 
@@ -390,7 +391,7 @@ LayoutToNetlist::build_all_nets (const db::CellMapping &cmap, db::Layout &target
 
           }
 
-          build_net (*n, target, target.cell (net_ci), lmap, circuit_cell_name_prefix);
+          build_net_rec (*n, target, target.cell (net_ci), lmap, circuit_cell_name_prefix, cell_map);
 
         }
 
diff --git a/src/db/db/gsiDeclDbLayoutToNetlist.cc b/src/db/db/gsiDeclDbLayoutToNetlist.cc
index 1e47fddc8..2b6b003fc 100644
--- a/src/db/db/gsiDeclDbLayoutToNetlist.cc
+++ b/src/db/db/gsiDeclDbLayoutToNetlist.cc
@@ -151,6 +151,54 @@ Class<db::LayoutToNetlist> decl_dbLayoutToNetlist ("db", "LayoutToNetlist",
     "If 'recursive'' is true, the returned region will contain the shapes of\n"
     "all subcircuits too.\n"
   ) +
+  gsi::method ("build_net", &db::LayoutToNetlist::build_net, gsi::arg ("net"), gsi::arg ("target"), gsi::arg ("target_cell"), gsi::arg ("lmap"), gsi::arg ("cell_name"),
+    "@brief Builds a net representation in the given layout and cell\n"
+    "\n"
+    "This method has two modes: recursive and top-level mode. In recursive mode,\n"
+    "it will create a proper hierarchy below the given target cell to hold all subcircuits the\n"
+    "net connects to. It will copy the net's parts from this subcircuits into these cells.\n"
+    "\n"
+    "In top-level mode, only the shapes from the net inside it's circuit are copied to\n"
+    "the given target cell. No other cells are created.\n"
+    "\n"
+    "Recursive mode is picked when a cell name prefix is given. The new cells will be\n"
+    "named like cell_name_prefix + circuit name.\n"
+    "\n"
+    "@param target The target layout\n"
+    "@param target_cell The target cell\n"
+    "@param lmap Target layer indexes (keys) and net regions (values)\n"
+    "@param cell_name_prefix Chooses recursive mode if non-nil\n"
+  ) +
+  gsi::method ("build_all_nets", &db::LayoutToNetlist::build_all_nets, gsi::arg ("cmap"), gsi::arg ("target"), gsi::arg ("lmap"), gsi::arg ("net_cell_name_prefix"), gsi::arg ("circuit_cell_name_prefix"),
+    "@brief Builds a full hierarchical representation of the nets\n"
+    "\n"
+    "This method copies all nets into cells corresponding to the circuits. It uses the cmap\n"
+    "object to determine the target cell (create them with \\cell_mapping_into or \\const_cell_mapping_into.\n"
+    "If no mapping is requested, the specific circuit it skipped.\n"
+    "\n"
+    "The method has two net annotation modes:\n"
+    "\n"
+    "@ul\n"
+    "@li 'No annotation'' (net_cell_name_prefix == 0): the shapes will be put into the target cell simply @/li\n"
+    "@li Individual subcells per net (net_cell_name_prefix != 0): for each net, a subcell is created\n"
+    "    and the net shapes will be put there (name of the subcell = net_cell_name_prefix + net name). @/li\n"
+    "@/ul\n"
+    "\n"
+    "In addition, net hierarchy is covered in two ways:\n"
+    "\n"
+    "@ul\n"
+    "@li No connection indicated (circuit_cell_name_prefix == 0: the net shapes are simply put into their\n"
+    "   respective circuits. The connections are not indicated. @/li\n"
+    "@li Subnet hierarchy (circuit_cell_name_prefix != 0): for each root net, a full hierarchy is built\n"
+    "   to accomodate the subnets (see build_net in recursive mode). @/li\n"
+    "@/ul\n"
+    "\n"
+    "@param cmap The mapping of internal layout to target layout for the circuit mapping\n"
+    "@param target The target layout\n"
+    "@param lmap Target layer indexes (keys) and net regions (values)\n"
+    "@param circuit_cell_name_prefix See method description\n"
+    "@param net_cell_name_prefix See method description\n"
+  ) +
   gsi::method ("probe_net", (db::Net *(db::LayoutToNetlist::*) (const db::Region &, const db::DPoint &)) &db::LayoutToNetlist::probe_net, gsi::arg ("of_layer"), gsi::arg ("point"),
     "@brief Finds the net by probing a specific location on the given layer\n"
     "\n"
diff --git a/testdata/algo/device_extract_au1_rebuild_nr.gds b/testdata/algo/device_extract_au1_rebuild_nr.gds
index ef77178c5..19301649d 100644
Binary files a/testdata/algo/device_extract_au1_rebuild_nr.gds and b/testdata/algo/device_extract_au1_rebuild_nr.gds differ