diff --git a/testdata/algo/lvs_test1_au.lvsdb.2 b/testdata/algo/lvs_test1_au.lvsdb.2
new file mode 100644
index 000000000..eb03fd506
--- /dev/null
+++ b/testdata/algo/lvs_test1_au.lvsdb.2
@@ -0,0 +1,646 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(bulk)
+ layer(nwell '1/0')
+ layer(poly '3/0')
+ layer(poly_lbl '3/1')
+ layer(diff_cont '4/0')
+ layer(poly_cont '5/0')
+ layer(metal1 '6/0')
+ layer(metal1_lbl '6/1')
+ layer(via1 '7/0')
+ layer(metal2 '8/0')
+ layer(metal2_lbl '8/1')
+ layer(ntie)
+ layer(psd)
+ layer(ptie)
+ layer(nsd)
+
+ # Mask layer connectivity
+ connect(nwell nwell ntie)
+ connect(poly poly poly_lbl poly_cont)
+ connect(poly_lbl poly)
+ connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
+ connect(poly_cont poly poly_cont metal1)
+ connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
+ connect(metal1_lbl metal1)
+ connect(via1 metal1 via1 metal2)
+ connect(metal2 via1 metal2 metal2_lbl)
+ connect(metal2_lbl metal2)
+ connect(ntie nwell diff_cont ntie)
+ connect(psd diff_cont psd)
+ connect(ptie diff_cont ptie)
+ connect(nsd diff_cont nsd)
+
+ # Global nets and connectivity
+ global(bulk BULK)
+ global(ptie BULK)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(psd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(psd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(nsd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(nsd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Circuit boundary
+  rect((-1700 -2440) (3100 7820))
+
+  # Nets with their geometries
+  net(1
+   rect(nwell (-1400 1800) (2800 3580))
+   rect(diff_cont (-1510 -650) (220 220))
+   rect(ntie (-510 -450) (800 680))
+  )
+  net(2 name(IN)
+   rect(poly (-525 -250) (250 2500))
+   rect(poly (-1425 -630) (2100 360))
+   rect(poly (-125 -2230) (250 2500))
+   rect(poly (-1050 -3850) (250 2400))
+   rect(poly (550 1200) (250 2400))
+   rect(poly (-250 -6000) (250 2400))
+   rect(poly (-1050 1200) (250 2400))
+   rect(poly_lbl (-525 -2600) (0 0))
+   rect(poly_cont (-830 -110) (220 220))
+  )
+  net(3 name(OUT)
+   rect(diff_cont (-910 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (1380 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -3820) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-1820 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (1310 -3710) (360 2220))
+   rect(metal1 (-1900 -800) (2220 360))
+   rect(metal1 (-2280 -2400) (360 2840))
+   rect(metal1 (-360 -3600) (360 1560))
+   rect(metal1 (1240 2040) (360 1560))
+   rect(metal1 (-360 -5160) (360 1560))
+   rect(metal1 (-1960 2040) (360 1560))
+   rect(metal1_lbl (1420 -2180) (0 0))
+   rect(psd (-1850 525) (525 1750))
+   rect(psd (1050 -1750) (525 1750))
+   rect(nsd (-2100 -5350) (525 1750))
+   rect(nsd (1050 -1750) (525 1750))
+  )
+  net(4 name(VSS)
+   rect(diff_cont (-110 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 980) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(metal1 (-290 -290) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -705) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 -1450) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -775) (2800 1700))
+   rect(metal2_lbl (-160 -540) (0 0))
+   rect(nsd (-1515 -1185) (550 1750))
+  )
+  net(5 name(VDD)
+   rect(diff_cont (-110 2490) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -1420) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (-290 -1490) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -1505) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -1575) (2800 1700))
+   rect(metal2_lbl (-150 -1250) (0 0))
+   rect(psd (-1525 -475) (550 1750))
+  )
+  net(6 name(BULK)
+   rect(diff_cont (-110 -2160) (220 220))
+   rect(ptie (-510 -450) (800 680))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1)
+  pin(2 name(IN))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5 name(VDD))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 3200)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 -400)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Circuit boundary
+  rect((0 -1640) (5740 7820))
+
+  # Nets with their geometries
+  net(1 name(BULK))
+  net(2)
+  net(3)
+  net(4)
+  net(5)
+  net(6)
+  net(7)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(BULK))
+  pin(2)
+  pin(3)
+  pin(4)
+  pin(5)
+  pin(6)
+  pin(7)
+
+  # Subcircuits and their connections
+  circuit(1 INV2 location(1700 800)
+   pin(0 7)
+   pin(1 5)
+   pin(2 4)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+  circuit(2 INV2 location(4340 800)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((-1720 -2440) (26880 7820))
+
+  # Nets with their geometries
+  net(1 name(FB)
+   rect(metal1 (-1700 1620) (360 360))
+   rect(via1 (-305 -305) (250 250))
+   rect(via1 (23190 -250) (250 250))
+   rect(metal2 (-23765 -325) (23840 400))
+   rect(metal2_lbl (-22120 -200) (0 0))
+  )
+  net(2 name(OSC)
+   rect(via1 (24435 1675) (250 250))
+   rect(metal2 (-325 -325) (400 400))
+   rect(metal2_lbl (-200 -200) (0 0))
+  )
+  net(3 name(VDD)
+   rect(metal1 (-180 3900) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 -2220) (0 0))
+  )
+  net(4 name(VSS)
+   rect(metal1 (-180 -2220) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 1100) (0 0))
+  )
+  net(5)
+  net(6)
+  net(7)
+  net(8)
+  net(9)
+  net(10)
+  net(11)
+  net(12)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(FB))
+  pin(2 name(OSC))
+  pin(3 name(VDD))
+  pin(4 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR location(19420 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 10)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR location(-1700 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 8)
+   pin(4 1)
+   pin(5 9)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR location(3580 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 9)
+   pin(5 12)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR location(8860 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 6)
+   pin(4 12)
+   pin(5 11)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR location(14140 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 5)
+   pin(4 11)
+   pin(5 10)
+   pin(6 3)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 5)
+   terminal(G 2)
+   terminal(D 3)
+   terminal(B 1)
+  )
+  device(2 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 4)
+   terminal(G 2)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($1)
+   pin(0 7)
+   pin(1 5)
+   pin(2 4)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+  circuit(2 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('6'))
+  net(6 name('100'))
+  net(7 name('5'))
+  net(8 name('101'))
+  net(9 name('8'))
+  net(10 name('102'))
+  net(11 name('7'))
+  net(12 name('103'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR name($1)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 5)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR name($2)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 6)
+   pin(4 1)
+   pin(5 7)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR name($3)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 8)
+   pin(4 7)
+   pin(5 9)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR name($4)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 10)
+   pin(4 9)
+   pin(5 11)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR name($5)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 12)
+   pin(4 11)
+   pin(5 5)
+   pin(6 3)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INV2 INV2 match
+  xref(
+   net(1 1 match)
+   net(6 6 match)
+   net(2 2 match)
+   net(3 3 match)
+   net(5 5 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(5 5 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(4 4 match)
+   pin(3 3 match)
+   device(3 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INV2PAIR INV2PAIR match
+  xref(
+   net(2 2 match)
+   net(3 3 match)
+   net(4 4 match)
+   net(5 5 match)
+   net(6 6 match)
+   net(7 7 match)
+   net(1 1 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(5 5 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(8 6 match)
+   net(7 8 match)
+   net(6 10 match)
+   net(5 12 match)
+   net(9 7 match)
+   net(10 5 match)
+   net(11 11 match)
+   net(12 9 match)
+   net(1 1 match)
+   net(2 2 match)
+   net(3 3 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+  )
+ )
+)
diff --git a/testdata/algo/lvs_test2_au.lvsdb.2 b/testdata/algo/lvs_test2_au.lvsdb.2
new file mode 100644
index 000000000..969594ebe
--- /dev/null
+++ b/testdata/algo/lvs_test2_au.lvsdb.2
@@ -0,0 +1,677 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(bulk)
+ layer(nwell '1/0')
+ layer(poly '3/0')
+ layer(poly_lbl '3/1')
+ layer(diff_cont '4/0')
+ layer(poly_cont '5/0')
+ layer(metal1 '6/0')
+ layer(metal1_lbl '6/1')
+ layer(via1 '7/0')
+ layer(metal2 '8/0')
+ layer(metal2_lbl '8/1')
+ layer(ntie)
+ layer(psd)
+ layer(ptie)
+ layer(nsd)
+
+ # Mask layer connectivity
+ connect(nwell nwell ntie)
+ connect(poly poly poly_lbl poly_cont)
+ connect(poly_lbl poly)
+ connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
+ connect(poly_cont poly poly_cont metal1)
+ connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
+ connect(metal1_lbl metal1)
+ connect(via1 metal1 via1 metal2)
+ connect(metal2 via1 metal2 metal2_lbl)
+ connect(metal2_lbl metal2)
+ connect(ntie nwell diff_cont ntie)
+ connect(psd diff_cont psd)
+ connect(ptie diff_cont ptie)
+ connect(nsd diff_cont nsd)
+
+ # Global nets and connectivity
+ global(bulk BULK)
+ global(ptie BULK)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(psd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(psd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(psd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(nwell (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(nsd (-650 -875) (525 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (550 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(nsd (-675 -875) (550 1750))
+  )
+  terminal(G
+   rect(poly (-125 -875) (250 1750))
+  )
+  terminal(D
+   rect(nsd (125 -875) (525 1750))
+  )
+  terminal(B
+   rect(bulk (-125 -875) (250 1750))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Circuit boundary
+  rect((-1700 -2440) (3100 7820))
+
+  # Nets with their geometries
+  net(1
+   rect(nwell (-1400 1800) (2800 3580))
+   rect(diff_cont (-1510 -650) (220 220))
+   rect(ntie (-510 -450) (800 680))
+  )
+  net(2 name(IN)
+   rect(poly (-525 -250) (250 2500))
+   rect(poly (-1425 -630) (2100 360))
+   rect(poly (-125 -2230) (250 2500))
+   rect(poly (-1050 -3850) (250 2400))
+   rect(poly (550 1200) (250 2400))
+   rect(poly (-250 -6000) (250 2400))
+   rect(poly (-1050 1200) (250 2400))
+   rect(poly_lbl (-525 -2600) (0 0))
+   rect(poly_cont (-830 -110) (220 220))
+  )
+  net(3 name(OUT)
+   rect(diff_cont (-910 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (1380 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -3820) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-1820 3380) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (1310 -3710) (360 2220))
+   rect(metal1 (-1900 -800) (2220 360))
+   rect(metal1 (-2280 -2400) (360 2840))
+   rect(metal1 (-360 -3600) (360 1560))
+   rect(metal1 (1240 2040) (360 1560))
+   rect(metal1 (-360 -5160) (360 1560))
+   rect(metal1 (-1960 2040) (360 1560))
+   rect(metal1_lbl (1420 -2180) (0 0))
+   rect(psd (-1850 525) (525 1750))
+   rect(psd (1050 -1750) (525 1750))
+   rect(nsd (-2100 -5350) (525 1750))
+   rect(nsd (1050 -1750) (525 1750))
+  )
+  net(4 name(VSS)
+   rect(diff_cont (-110 90) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 980) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(diff_cont (-220 -620) (220 220))
+   rect(metal1 (-290 -290) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -705) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 -1450) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -775) (2800 1700))
+   rect(metal2_lbl (-160 -540) (0 0))
+   rect(nsd (-1515 -1185) (550 1750))
+  )
+  net(5 name(VDD)
+   rect(diff_cont (-110 2490) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 -1420) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(diff_cont (-220 180) (220 220))
+   rect(metal1 (-290 -1490) (360 1560))
+   rect(metal1 (-360 -1560) (360 1560))
+   rect(via1 (-305 -1505) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(via1 (-250 150) (250 250))
+   rect(metal2 (-1525 -1575) (2800 1700))
+   rect(metal2_lbl (-150 -1250) (0 0))
+   rect(psd (-1525 -475) (550 1750))
+  )
+  net(6 name(BULK)
+   rect(diff_cont (-110 -2160) (220 220))
+   rect(ptie (-510 -450) (800 680))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1)
+  pin(2 name(IN))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5 name(VDD))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 3200)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(800 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(-400 -400)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Circuit boundary
+  rect((0 -1640) (5740 7820))
+
+  # Nets with their geometries
+  net(1 name(BULK))
+  net(2)
+  net(3)
+  net(4)
+  net(5)
+  net(6)
+  net(7)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(BULK))
+  pin(2)
+  pin(3)
+  pin(4)
+  pin(5)
+  pin(6)
+  pin(7)
+
+  # Subcircuits and their connections
+  circuit(1 INV2 location(1700 800)
+   pin(0 7)
+   pin(1 5)
+   pin(2 4)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+  circuit(2 INV2 location(4340 800)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((-1720 -2440) (26880 7820))
+
+  # Nets with their geometries
+  net(1 name(FB)
+   rect(metal1 (-1700 1620) (360 360))
+   rect(via1 (-305 -305) (250 250))
+   rect(via1 (23190 -250) (250 250))
+   rect(metal2 (-23765 -325) (23840 400))
+   rect(metal2_lbl (-22120 -200) (0 0))
+  )
+  net(2 name(OSC)
+   rect(via1 (24435 1675) (250 250))
+   rect(metal2 (-325 -325) (400 400))
+   rect(metal2_lbl (-200 -200) (0 0))
+  )
+  net(3 name(VDD)
+   rect(metal1 (-180 3900) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 -2220) (0 0))
+  )
+  net(4 name(VSS)
+   rect(metal1 (-180 -2220) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal1 (2280 -1120) (360 1120))
+   rect(metal2_lbl (-23940 1100) (0 0))
+  )
+  net(5)
+  net(6)
+  net(7)
+  net(8)
+  net(9)
+  net(10)
+  net(11)
+  net(12)
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(FB))
+  pin(2 name(OSC))
+  pin(3 name(VDD))
+  pin(4 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR location(19420 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 10)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR location(-1700 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 8)
+   pin(4 1)
+   pin(5 9)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR location(3580 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 9)
+   pin(5 12)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR location(8860 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 6)
+   pin(4 12)
+   pin(5 11)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR location(14140 -800)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 5)
+   pin(4 11)
+   pin(5 10)
+   pin(6 3)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(INV2
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 5)
+   terminal(G 2)
+   terminal(D 3)
+   terminal(B 1)
+  )
+  device(2 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 3.5)
+   param(AS 1.4)
+   param(AD 1.4)
+   param(PS 6.85)
+   param(PD 6.85)
+   terminal(S 4)
+   terminal(G 2)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INV2PAIR
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(INV2PAIRX
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('5'))
+  net(6 name('6'))
+  net(7 name('7'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+  pin(5 name('5'))
+  pin(6 name('6'))
+  pin(7 name('7'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2 name($2)
+   pin(0 7)
+   pin(1 4)
+   pin(2 6)
+   pin(3 3)
+   pin(4 2)
+   pin(5 1)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name('1'))
+  net(2 name('2'))
+  net(3 name('3'))
+  net(4 name('4'))
+  net(5 name('6'))
+  net(6 name('5'))
+  net(7 name('101'))
+  net(8 name('8'))
+  net(9 name('102'))
+  net(10 name('7'))
+  net(11 name('103'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('1'))
+  pin(2 name('2'))
+  pin(3 name('3'))
+  pin(4 name('4'))
+
+  # Subcircuits and their connections
+  circuit(1 INV2PAIR name($1)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 5)
+   pin(5 2)
+   pin(6 3)
+  )
+  circuit(2 INV2PAIR name($2)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 1)
+   pin(4 1)
+   pin(5 6)
+   pin(6 3)
+  )
+  circuit(3 INV2PAIR name($3)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 7)
+   pin(4 6)
+   pin(5 8)
+   pin(6 3)
+  )
+  circuit(4 INV2PAIR name($4)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 9)
+   pin(4 8)
+   pin(5 10)
+   pin(6 3)
+  )
+  circuit(5 INV2PAIR name($5)
+   pin(0 4)
+   pin(1 3)
+   pin(2 4)
+   pin(3 11)
+   pin(4 10)
+   pin(5 5)
+   pin(6 3)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(() INV2PAIRX mismatch
+  xref(
+  )
+ )
+ circuit(INV2 INV2 match
+  xref(
+   net(1 1 match)
+   net(6 6 match)
+   net(2 2 match)
+   net(3 3 match)
+   net(5 5 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(5 5 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(4 4 match)
+   pin(3 3 match)
+   device(3 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INV2PAIR INV2PAIR nomatch
+  xref(
+   net(2 2 mismatch)
+   net(3 3 mismatch)
+   net(4 4 mismatch)
+   net(5 5 mismatch)
+   net(6 6 match)
+   net(7 7 mismatch)
+   net(1 1 mismatch)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(5 5 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   circuit(1 () mismatch)
+   circuit(2 1 match)
+  )
+ )
+ circuit(RINGO RINGO nomatch
+  log(
+   entry(error description('Net $I22 is not matching any net from reference netlist'))
+   entry(error description('Net FB is not matching any net from reference netlist'))
+  )
+  xref(
+   net(8 () mismatch)
+   net(7 7 match)
+   net(6 9 match)
+   net(5 11 match)
+   net(9 6 match)
+   net(10 5 match)
+   net(11 10 match)
+   net(12 8 match)
+   net(1 1 mismatch)
+   net(2 2 match)
+   net(3 3 match)
+   net(4 4 match)
+   pin(0 0 match)
+   pin(1 1 match)
+   pin(2 2 match)
+   pin(3 3 match)
+   circuit(() 2 mismatch)
+   circuit(2 () mismatch)
+   circuit(1 1 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+  )
+ )
+)
diff --git a/testdata/lvs/nand2_split_gate.lvsdb.2 b/testdata/lvs/nand2_split_gate.lvsdb.2
new file mode 100644
index 000000000..0c99205ab
--- /dev/null
+++ b/testdata/lvs/nand2_split_gate.lvsdb.2
@@ -0,0 +1,407 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(NAND2_WITH_DIODES)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 'NWELL (1/0)')
+ layer(l4 'POLY (5/0)')
+ layer(l8 'CONTACT (6/0)')
+ layer(l11 'METAL1 (7/0)')
+ layer(l12 'METAL1_LABEL (7/1)')
+ layer(l13 'VIA1 (8/0)')
+ layer(l14 'METAL2 (9/0)')
+ layer(l15 'METAL2_LABEL (9/1)')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12 l13)
+ connect(l12 l11)
+ connect(l13 l11 l13 l14)
+ connect(l14 l13 l14 l15)
+ connect(l15 l14)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (500 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-625 -750) (500 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-575 -450) (450 900))
+  )
+  terminal(G
+   rect(l4 (-125 -450) (250 900))
+  )
+  terminal(D
+   rect(l6 (125 -450) (500 900))
+  )
+  terminal(B
+   rect(l7 (-125 -450) (250 900))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-625 -450) (500 900))
+  )
+  terminal(G
+   rect(l4 (-125 -450) (250 900))
+  )
+  terminal(D
+   rect(l6 (125 -450) (450 900))
+  )
+  terminal(B
+   rect(l7 (-125 -450) (250 900))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(NAND2_WITH_DIODES
+
+  # Circuit boundary
+  rect((0 0) (3750 6150))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l4 (350 2750) (550 400))
+   rect(l4 (0 -2050) (250 3100))
+   rect(l4 (-250 0) (250 1650))
+   rect(l4 (-250 -5800) (250 1050))
+   rect(l4 (-250 300) (250 1050))
+   rect(l8 (-700 400) (200 200))
+   rect(l11 (-300 -300) (400 400))
+   text(l12 B (-200 -200))
+  )
+  net(2 name(A)
+   rect(l4 (1900 3400) (550 400))
+   rect(l4 (-800 -2700) (250 3100))
+   rect(l4 (-250 0) (250 1650))
+   rect(l4 (-250 -5800) (250 1050))
+   rect(l4 (-250 300) (250 1050))
+   rect(l8 (250 1050) (200 200))
+   rect(l11 (-300 -300) (400 400))
+   text(l12 A (-200 -200))
+  )
+  net(3
+   rect(l8 (1300 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 650) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l11 (-250 -2150) (300 900))
+   rect(l11 (-300 -900) (300 850))
+   rect(l11 (-300 500) (300 900))
+   rect(l11 (-300 -900) (300 850))
+   rect(l6 (-400 -2200) (500 900))
+   rect(l6 (-500 450) (500 900))
+  )
+  net(4 name(OUT)
+   rect(l8 (2050 300) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 650) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-950 2000) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l11 (500 -5350) (300 850))
+   rect(l11 (-300 -50) (300 1950))
+   rect(l11 (-300 -1400) (300 850))
+   rect(l11 (-300 300) (450 400))
+   rect(l11 (-1200 -300) (1050 300))
+   rect(l11 (-1050 1150) (300 1400))
+   rect(l11 (-300 -2700) (300 1950))
+   text(l12 OUT (700 -2000))
+   rect(l2 (-1100 1300) (500 1500))
+   rect(l6 (250 -5500) (450 900))
+   rect(l6 (-450 450) (450 900))
+  )
+  net(5 name(VDD)
+   rect(l3 (0 2950) (3750 3200))
+   rect(l8 (-3200 -1800) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (1300 -1200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (700 -800) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l11 (-2650 -1200) (300 1600))
+   rect(l11 (1200 -1600) (300 1600))
+   rect(l11 (600 -1200) (300 1200))
+   rect(l13 (-2650 -800) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l13 (1300 -700) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l13 (700 -700) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l14 (-3150 -850) (3750 1000))
+   text(l15 VDD (-100 -850))
+   rect(l2 (-3200 -850) (450 1500))
+   rect(l2 (1000 -1500) (450 1500))
+   rect(l9 (400 -1200) (600 1200))
+  )
+  net(6 name(VSS)
+   rect(l8 (550 1650) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -2050) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (2200 -550) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l11 (-2650 -50) (300 1350))
+   rect(l11 (-300 -2400) (300 1050))
+   rect(l11 (2100 -1050) (300 1200))
+   rect(l13 (-2650 -1100) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l13 (2200 -700) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l14 (-3150 -850) (3750 1000))
+   text(l15 VSS (-100 -850))
+   rect(l6 (-3200 1400) (450 900))
+   rect(l6 (-450 -2250) (450 900))
+   rect(l10 (1850 -900) (600 1200))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+  pin(4 name(OUT))
+  pin(5 name(VDD))
+  pin(6 name(VSS))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(1025 4950)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.675)
+   param(AD 0.375)
+   param(PS 3.9)
+   param(PD 2)
+   terminal(S 5)
+   terminal(G 1)
+   terminal(D 4)
+   terminal(B 5)
+  )
+  device(2 D$PMOS$1
+   location(1775 4950)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.375)
+   param(AD 0.675)
+   param(PS 2)
+   param(PD 3.9)
+   terminal(S 4)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   device(D$NMOS location(0 1350))
+   connect(0 S S)
+   connect(1 S S)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D D)
+   connect(0 B B)
+   connect(1 B B)
+   location(1025 650)
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0.81)
+   param(AD 0.45)
+   param(PS 5.4)
+   param(PD 2.8)
+   terminal(S 6)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 6)
+  )
+  device(4 D$NMOS$1
+   device(D$NMOS$1 location(0 1350))
+   connect(0 S S)
+   connect(1 S S)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D D)
+   connect(0 B B)
+   connect(1 B B)
+   location(1775 650)
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0.45)
+   param(AD 0.81)
+   param(PS 2.8)
+   param(PD 5.4)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(NAND2_WITH_DIODES
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+  net(3 name(OUT))
+  net(4 name(VSS))
+  net(5 name(VDD))
+  net(6 name($1))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5 name(VDD))
+
+  # Devices and their connections
+  device(1 PMOS
+   name('1')
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(2 PMOS
+   name('2')
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 1)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(3 NMOS
+   name('3')
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 4)
+  )
+  device(4 NMOS
+   name('4')
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 1)
+   terminal(D 6)
+   terminal(B 4)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(NAND2_WITH_DIODES NAND2_WITH_DIODES match
+  xref(
+   net(3 6 match)
+   net(2 1 match)
+   net(1 2 match)
+   net(4 3 match)
+   net(5 5 match)
+   net(6 4 match)
+   pin(1 0 match)
+   pin(0 1 match)
+   pin(2 2 match)
+   pin(3 4 match)
+   pin(4 3 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/nand2_split_gate_early.lvsdb.2 b/testdata/lvs/nand2_split_gate_early.lvsdb.2
new file mode 100644
index 000000000..0c99205ab
--- /dev/null
+++ b/testdata/lvs/nand2_split_gate_early.lvsdb.2
@@ -0,0 +1,407 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(NAND2_WITH_DIODES)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 'NWELL (1/0)')
+ layer(l4 'POLY (5/0)')
+ layer(l8 'CONTACT (6/0)')
+ layer(l11 'METAL1 (7/0)')
+ layer(l12 'METAL1_LABEL (7/1)')
+ layer(l13 'VIA1 (8/0)')
+ layer(l14 'METAL2 (9/0)')
+ layer(l15 'METAL2_LABEL (9/1)')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12 l13)
+ connect(l12 l11)
+ connect(l13 l11 l13 l14)
+ connect(l14 l13 l14 l15)
+ connect(l15 l14)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (500 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-625 -750) (500 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-575 -450) (450 900))
+  )
+  terminal(G
+   rect(l4 (-125 -450) (250 900))
+  )
+  terminal(D
+   rect(l6 (125 -450) (500 900))
+  )
+  terminal(B
+   rect(l7 (-125 -450) (250 900))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-625 -450) (500 900))
+  )
+  terminal(G
+   rect(l4 (-125 -450) (250 900))
+  )
+  terminal(D
+   rect(l6 (125 -450) (450 900))
+  )
+  terminal(B
+   rect(l7 (-125 -450) (250 900))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(NAND2_WITH_DIODES
+
+  # Circuit boundary
+  rect((0 0) (3750 6150))
+
+  # Nets with their geometries
+  net(1 name(B)
+   rect(l4 (350 2750) (550 400))
+   rect(l4 (0 -2050) (250 3100))
+   rect(l4 (-250 0) (250 1650))
+   rect(l4 (-250 -5800) (250 1050))
+   rect(l4 (-250 300) (250 1050))
+   rect(l8 (-700 400) (200 200))
+   rect(l11 (-300 -300) (400 400))
+   text(l12 B (-200 -200))
+  )
+  net(2 name(A)
+   rect(l4 (1900 3400) (550 400))
+   rect(l4 (-800 -2700) (250 3100))
+   rect(l4 (-250 0) (250 1650))
+   rect(l4 (-250 -5800) (250 1050))
+   rect(l4 (-250 300) (250 1050))
+   rect(l8 (250 1050) (200 200))
+   rect(l11 (-300 -300) (400 400))
+   text(l12 A (-200 -200))
+  )
+  net(3
+   rect(l8 (1300 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 650) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l11 (-250 -2150) (300 900))
+   rect(l11 (-300 -900) (300 850))
+   rect(l11 (-300 500) (300 900))
+   rect(l11 (-300 -900) (300 850))
+   rect(l6 (-400 -2200) (500 900))
+   rect(l6 (-500 450) (500 900))
+  )
+  net(4 name(OUT)
+   rect(l8 (2050 300) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 650) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-950 2000) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -200) (200 200))
+   rect(l11 (500 -5350) (300 850))
+   rect(l11 (-300 -50) (300 1950))
+   rect(l11 (-300 -1400) (300 850))
+   rect(l11 (-300 300) (450 400))
+   rect(l11 (-1200 -300) (1050 300))
+   rect(l11 (-1050 1150) (300 1400))
+   rect(l11 (-300 -2700) (300 1950))
+   text(l12 OUT (700 -2000))
+   rect(l2 (-1100 1300) (500 1500))
+   rect(l6 (250 -5500) (450 900))
+   rect(l6 (-450 450) (450 900))
+  )
+  net(5 name(VDD)
+   rect(l3 (0 2950) (3750 3200))
+   rect(l8 (-3200 -1800) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (1300 -1200) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (700 -800) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l11 (-2650 -1200) (300 1600))
+   rect(l11 (1200 -1600) (300 1600))
+   rect(l11 (600 -1200) (300 1200))
+   rect(l13 (-2650 -800) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l13 (1300 -700) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l13 (700 -700) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l14 (-3150 -850) (3750 1000))
+   text(l15 VDD (-100 -850))
+   rect(l2 (-3200 -850) (450 1500))
+   rect(l2 (1000 -1500) (450 1500))
+   rect(l9 (400 -1200) (600 1200))
+  )
+  net(6 name(VSS)
+   rect(l8 (550 1650) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (-200 -2050) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l8 (2200 -550) (200 200))
+   rect(l8 (-200 300) (200 200))
+   rect(l11 (-2650 -50) (300 1350))
+   rect(l11 (-300 -2400) (300 1050))
+   rect(l11 (2100 -1050) (300 1200))
+   rect(l13 (-2650 -1100) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l13 (2200 -700) (200 200))
+   rect(l13 (-200 300) (200 200))
+   rect(l14 (-3150 -850) (3750 1000))
+   text(l15 VSS (-100 -850))
+   rect(l6 (-3200 1400) (450 900))
+   rect(l6 (-450 -2250) (450 900))
+   rect(l10 (1850 -900) (600 1200))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(B))
+  pin(2 name(A))
+  pin(4 name(OUT))
+  pin(5 name(VDD))
+  pin(6 name(VSS))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(1025 4950)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.675)
+   param(AD 0.375)
+   param(PS 3.9)
+   param(PD 2)
+   terminal(S 5)
+   terminal(G 1)
+   terminal(D 4)
+   terminal(B 5)
+  )
+  device(2 D$PMOS$1
+   location(1775 4950)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.375)
+   param(AD 0.675)
+   param(PS 2)
+   param(PD 3.9)
+   terminal(S 4)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   device(D$NMOS location(0 1350))
+   connect(0 S S)
+   connect(1 S S)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D D)
+   connect(0 B B)
+   connect(1 B B)
+   location(1025 650)
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0.81)
+   param(AD 0.45)
+   param(PS 5.4)
+   param(PD 2.8)
+   terminal(S 6)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 6)
+  )
+  device(4 D$NMOS$1
+   device(D$NMOS$1 location(0 1350))
+   connect(0 S S)
+   connect(1 S S)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D D)
+   connect(0 B B)
+   connect(1 B B)
+   location(1775 650)
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0.45)
+   param(AD 0.81)
+   param(PS 2.8)
+   param(PD 5.4)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 6)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(NAND2_WITH_DIODES
+
+  # Nets
+  net(1 name(A))
+  net(2 name(B))
+  net(3 name(OUT))
+  net(4 name(VSS))
+  net(5 name(VDD))
+  net(6 name($1))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(A))
+  pin(2 name(B))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5 name(VDD))
+
+  # Devices and their connections
+  device(1 PMOS
+   name('1')
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 2)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(2 PMOS
+   name('2')
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 1)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(3 NMOS
+   name('3')
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 2)
+   terminal(D 4)
+   terminal(B 4)
+  )
+  device(4 NMOS
+   name('4')
+   param(L 0.25)
+   param(W 1.8)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 1)
+   terminal(D 6)
+   terminal(B 4)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(NAND2_WITH_DIODES NAND2_WITH_DIODES match
+  xref(
+   net(3 6 match)
+   net(2 1 match)
+   net(1 2 match)
+   net(4 3 match)
+   net(5 5 match)
+   net(6 4 match)
+   pin(1 0 match)
+   pin(0 1 match)
+   pin(2 2 match)
+   pin(3 4 match)
+   pin(4 3 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_fixed_sources.gds b/testdata/lvs/ringo_fixed_sources.gds
new file mode 100644
index 000000000..2c6d93de5
Binary files /dev/null and b/testdata/lvs/ringo_fixed_sources.gds differ
diff --git a/testdata/lvs/ringo_layout_var.lvsdb.2 b/testdata/lvs/ringo_layout_var.lvsdb.2
new file mode 100644
index 000000000..fbe29c86e
--- /dev/null
+++ b/testdata/lvs/ringo_layout_var.lvsdb.2
@@ -0,0 +1,1013 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX1B
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1B location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1B location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1B location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INVX1B INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(3 3 match)
+   circuit(5 5 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(2 2 match)
+   circuit(4 4 match)
+   circuit(6 6 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_compare2.lvsdb.2 b/testdata/lvs/ringo_simple_compare2.lvsdb.2
new file mode 100644
index 000000000..4bfcca0be
--- /dev/null
+++ b/testdata/lvs/ringo_simple_compare2.lvsdb.2
@@ -0,0 +1,908 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2
new file mode 100644
index 000000000..d77d08cb2
--- /dev/null
+++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2
@@ -0,0 +1,908 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.5)
+   param(W 3)
+   param(AS 2.55)
+   param(AD 1.35)
+   param(PS 7.7)
+   param(PD 3.9)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.5)
+   param(W 3)
+   param(AS 1.35)
+   param(AD 2.55)
+   param(PS 3.9)
+   param(PD 7.7)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.5)
+   param(W 1.9)
+   param(AS 1.615)
+   param(AD 0.855)
+   param(PS 5.5)
+   param(PD 2.8)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.5)
+   param(W 1.9)
+   param(AS 0.855)
+   param(AD 1.615)
+   param(PS 2.8)
+   param(PD 5.5)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.5)
+   param(W 3)
+   param(AS 2.55)
+   param(AD 2.55)
+   param(PS 7.7)
+   param(PD 7.7)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.5)
+   param(W 1.9)
+   param(AS 1.615)
+   param(AD 1.615)
+   param(PS 5.5)
+   param(PD 5.5)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.5)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.5)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.5)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.5)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 8)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.5)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.5)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.2 b/testdata/lvs/ringo_simple_dmos.lvsdb.2
new file mode 100644
index 000000000..94072e582
--- /dev/null
+++ b/testdata/lvs/ringo_simple_dmos.lvsdb.2
@@ -0,0 +1,886 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l4 '1/0')
+ layer(l5 '5/0')
+ layer(l10 '8/0')
+ layer(l13 '9/0')
+ layer(l14 '10/0')
+ layer(l15 '11/0')
+ layer(l9)
+ layer(l3)
+ layer(l1)
+ layer(l11)
+ layer(l8)
+ layer(l6)
+ layer(l12)
+
+ # Mask layer connectivity
+ connect(l4 l4 l11)
+ connect(l5 l5 l10)
+ connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
+ connect(l13 l10 l13 l14)
+ connect(l14 l13 l14 l15)
+ connect(l15 l14 l15)
+ connect(l9 l9)
+ connect(l3 l10 l3)
+ connect(l1 l10 l1)
+ connect(l11 l4 l10 l11)
+ connect(l8 l10 l8)
+ connect(l6 l10 l6)
+ connect(l12 l10 l12)
+
+ # Global nets and connectivity
+ global(l9 SUBSTRATE)
+ global(l12 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l3 (125 -750) (450 1500))
+  )
+  terminal(G
+   rect(l5 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l1 (-550 -750) (425 1500))
+  )
+  terminal(B
+   rect(l4 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l3 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l5 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l1 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l4 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l3 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l5 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l1 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l4 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l8 (125 -475) (450 950))
+  )
+  terminal(G
+   rect(l5 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(B
+   rect(l9 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l8 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l5 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l9 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l8 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l5 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l9 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l10 (1110 5160) (180 180))
+   rect(l10 (-180 920) (180 180))
+   rect(l10 (-180 -730) (180 180))
+   rect(l13 (-240 -790) (300 1700))
+   rect(l13 (-1350 0) (2400 800))
+   rect(l13 (-1150 -400) (0 0))
+   rect(l3 (-250 -2150) (425 1500))
+   rect(l3 (-450 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l10 (1810 1770) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l10 (-1580 3760) (180 180))
+   rect(l10 (-180 -730) (180 180))
+   rect(l10 (-180 -730) (180 180))
+   rect(l10 (1220 920) (180 180))
+   rect(l10 (-180 -1280) (180 180))
+   rect(l10 (-180 370) (180 180))
+   polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l13 (-110 1390) (300 1400))
+   polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l13 (-140 -500) (0 0))
+   rect(l13 (-1750 1100) (300 1400))
+   rect(l13 (1100 -1700) (300 300))
+   rect(l13 (-300 0) (300 1400))
+   rect(l1 (-1750 -1450) (425 1500))
+   rect(l1 (950 -1500) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l10 (410 1770) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l13 (-240 -1300) (300 1360))
+   rect(l13 (-650 -2160) (2400 800))
+   rect(l13 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l8 (1000 1660) (425 950))
+   rect(l8 (-450 -950) (425 950))
+  )
+  net(5
+   rect(l4 (-100 4500) (2600 3500))
+  )
+  net(6 name(B)
+   rect(l5 (1425 2860) (250 1940))
+   rect(l5 (-345 -950) (300 300))
+   rect(l5 (-205 650) (250 2000))
+   rect(l5 (-250 -2000) (250 2000))
+   rect(l5 (-250 -5390) (250 1450))
+   rect(l10 (-285 1050) (180 180))
+   rect(l13 (-70 -90) (0 0))
+   rect(l13 (-170 -150) (300 300))
+  )
+  net(7 name(A)
+   rect(l5 (725 2860) (250 1940))
+   rect(l5 (-325 -1850) (300 300))
+   rect(l5 (-225 1550) (250 2000))
+   rect(l5 (-250 -2000) (250 2000))
+   rect(l5 (-250 -5390) (250 1450))
+   rect(l10 (-265 150) (180 180))
+   rect(l13 (-90 -90) (0 0))
+   rect(l13 (-150 -150) (300 300))
+  )
+  net(8 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(5)
+  pin(6 name(B))
+  pin(7 name(A))
+  pin(8 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 7)
+   terminal(D 2)
+   terminal(B 5)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 4)
+   terminal(G 7)
+   terminal(D 3)
+   terminal(B 8)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 4)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 8)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l10 (410 6260) (180 180))
+   rect(l10 (-180 -730) (180 180))
+   rect(l10 (-180 -730) (180 180))
+   rect(l13 (-240 -240) (300 1400))
+   rect(l13 (-650 300) (1800 800))
+   rect(l13 (-1450 -1100) (300 300))
+   rect(l13 (300 400) (0 0))
+   rect(l3 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l10 (1110 5160) (180 180))
+   rect(l10 (-180 920) (180 180))
+   rect(l10 (-180 -730) (180 180))
+   rect(l10 (-180 -4120) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l13 (-240 -790) (300 4790))
+   rect(l13 (-150 -2500) (0 0))
+   rect(l1 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l10 (410 1770) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l13 (-240 -1300) (300 1360))
+   rect(l13 (-650 -2160) (1800 800))
+   rect(l13 (-850 -400) (0 0))
+   rect(l8 (-650 860) (425 950))
+  )
+  net(4
+   rect(l4 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l5 (725 2860) (250 1940))
+   rect(l5 (-525 -1850) (300 300))
+   rect(l5 (-25 1550) (250 2000))
+   rect(l5 (-250 -2000) (250 2000))
+   rect(l5 (-250 -5390) (250 1450))
+   rect(l10 (-465 150) (180 180))
+   rect(l13 (-90 -90) (0 0))
+   rect(l13 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l13 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l13 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l13 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l13 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l13 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l13 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l13 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l13 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l13 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l13 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l13 (21750 2950) (900 300))
+   rect(l13 (-19530 590) (320 320))
+   rect(l13 (17820 -320) (320 320))
+   rect(l14 (-18400 -260) (200 200))
+   rect(l14 (17940 -200) (200 200))
+   rect(l15 (-18040 -300) (17740 400))
+   rect(l15 (-17920 -200) (0 0))
+   rect(l15 (-220 -200) (400 400))
+   rect(l15 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l4 (500 4500) (1400 3500))
+   rect(l4 (-1900 -3500) (600 3500))
+   rect(l4 (23300 -3500) (1400 3500))
+   rect(l4 (-100 -3500) (600 3500))
+   rect(l10 (-24690 -1240) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l10 (-180 -1280) (180 180))
+   rect(l10 (23220 370) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l10 (-180 -1280) (180 180))
+   rect(l13 (-21740 860) (0 0))
+   rect(l13 (-2350 -450) (1200 800))
+   rect(l13 (-750 -1450) (300 1400))
+   rect(l13 (-100 -350) (0 0))
+   rect(l13 (-1250 -400) (600 800))
+   rect(l13 (23400 -800) (1200 800))
+   rect(l13 (-750 -1450) (300 1400))
+   rect(l13 (-100 -350) (0 0))
+   rect(l13 (550 -400) (600 800))
+   rect(l11 (-24850 -1500) (500 1500))
+   rect(l11 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l13 (23440 3840) (320 320))
+   rect(l14 (-260 -260) (200 200))
+   rect(l15 (-100 -100) (0 0))
+   rect(l15 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l13 (2440 2940) (320 320))
+   rect(l14 (-260 -260) (200 200))
+   rect(l15 (-100 -100) (0 0))
+   rect(l15 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l10 (1110 1610) (180 180))
+   rect(l10 (-180 -1280) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l10 (23220 370) (180 180))
+   rect(l10 (-180 -1280) (180 180))
+   rect(l10 (-180 370) (180 180))
+   rect(l13 (-21740 -390) (0 0))
+   rect(l13 (-1900 -400) (300 1400))
+   rect(l13 (-750 -1450) (1200 800))
+   rect(l13 (-550 -400) (0 0))
+   rect(l13 (-1250 -400) (600 800))
+   rect(l13 (23850 -750) (300 1400))
+   rect(l13 (-750 -1450) (1200 800))
+   rect(l13 (-550 -400) (0 0))
+   rect(l13 (550 -400) (600 800))
+   rect(l12 (-24850 -800) (500 1500))
+   rect(l12 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 nomatch
+  log(
+   entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
+   entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
+   entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
+  )
+  xref(
+   net(5 4 match)
+   net(4 3 mismatch)
+   net(7 6 match)
+   net(6 5 match)
+   net(2 2 match)
+   net(8 7 mismatch)
+   net(1 1 match)
+   net(3 8 mismatch)
+   pin(() 2 mismatch)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 () mismatch)
+   device(3 3 match)
+   device(4 4 mismatch)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n  A: ND2X1\n  B: ND2X1')
+  xref(
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_dmos_fixed.lvs b/testdata/lvs/ringo_simple_dmos_fixed.lvs
new file mode 100644
index 000000000..5f375e95f
--- /dev/null
+++ b/testdata/lvs/ringo_simple_dmos_fixed.lvs
@@ -0,0 +1,83 @@
+
+source($lvs_test_source, "RINGO")
+
+report_lvs($lvs_test_target_lvsdb, true)
+
+target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
+
+schematic("ringo.cir")
+
+deep
+
+# Drawing layers
+
+nwell       = input(1, 0)
+active      = input(2, 0)
+pplus       = input(3, 0)
+nplus       = input(4, 0)
+poly        = input(5, 0)
+contact     = input(8, 0)
+metal1      = input(9, 0)
+via1        = input(10, 0)
+metal2      = input(11, 0)
+source      = input(14, 0)
+
+# Bulk layer for terminal provisioning
+
+bulk        = polygon_layer
+
+# Computed layers
+
+active_in_nwell       = active & nwell
+pactive               = active_in_nwell & pplus
+pgate                 = pactive & poly
+psd                   = pactive - pgate
+ps                    = psd & source
+pd                    = psd - source
+ntie                  = active_in_nwell & nplus
+
+active_outside_nwell  = active - nwell
+nactive               = active_outside_nwell & nplus
+ngate                 = nactive & poly
+nsd                   = nactive - ngate
+ns                    = nsd & source
+nd                    = nsd - source
+ptie                  = active_outside_nwell & pplus
+
+# Device extraction
+
+# PMOS transistor device extraction
+extract_devices(dmos4("PMOS"), { "S" => ps, "D" => pd, "G" => pgate, "W" => nwell, 
+                                 "tS" => ps, "tD" => pd, "tG" => poly, "tW" => nwell })
+
+# NMOS transistor device extraction
+extract_devices(dmos4("NMOS"), { "S" => ns, "D" => nd, "G" => ngate, "W" => bulk, 
+                                 "tS" => ns, "tD" => nd, "tG" => poly, "tW" => bulk })
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(ps,         pd)
+connect(ns,         nd)
+connect(ps,         contact)
+connect(pd,         contact)
+connect(ns,         contact)
+connect(nd,         contact)
+connect(poly,       contact)
+connect(ntie,       contact)
+connect(nwell,      ntie)
+connect(ptie,       contact)
+connect(contact,    metal1)
+connect(metal1,     via1)
+connect(via1,       metal2)
+
+# Global
+connect_global(bulk, "SUBSTRATE")
+connect_global(ptie, "SUBSTRATE")
+
+# Compare section
+
+netlist.simplify
+
+compare
+
diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2
new file mode 100644
index 000000000..a6f463150
--- /dev/null
+++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2
@@ -0,0 +1,965 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS$1
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$2
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (27600 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l4 (26050 2800) (525 550))
+   rect(l4 (-525 -300) (300 300))
+   rect(l4 (-25 -2000) (250 1450))
+   rect(l8 (-465 310) (180 180))
+   rect(l11 (-240 -240) (300 300))
+  )
+  net(2
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(3
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(4
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(5
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(6
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(7
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(8
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(9
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(10
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(11
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(12 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(13 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l3 (0 -3500) (600 3500))
+   rect(l3 (0 -3500) (600 3500))
+   rect(l3 (0 -3500) (600 3500))
+   rect(l8 (-26490 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l9 (-26650 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(14 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(16 name(VSS)
+   rect(l8 (26010 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (520 -730) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-25780 -890) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (1260 -40) (300 1360))
+   rect(l11 (400 -1360) (300 1360))
+   rect(l11 (-24000 -1710) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l11 (0 -800) (600 800))
+   rect(l6 (-1025 400) (425 950))
+   rect(l6 (-1100 -950) (425 950))
+   rect(l10 (-25375 -2150) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(12 name(FB))
+  pin(13 name(VDD))
+  pin(14 name(OUT))
+  pin(15 name(ENABLE))
+  pin(16 name(VSS))
+
+  # Devices and their connections
+  device(1 D$NMOS
+   location(26450 2075)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 16)
+   terminal(G 1)
+   terminal(D 16)
+   terminal(B 16)
+  )
+
+  # Subcircuits and their connections
+  circuit(3 ND2X1 location(1800 0)
+   pin(0 13)
+   pin(1 2)
+   pin(2 16)
+   pin(3 13)
+   pin(4 12)
+   pin(5 15)
+   pin(6 16)
+  )
+  circuit(4 INVX1 location(4200 0)
+   pin(0 13)
+   pin(1 3)
+   pin(2 16)
+   pin(3 13)
+   pin(4 2)
+   pin(5 16)
+  )
+  circuit(5 INVX1 location(6000 0)
+   pin(0 13)
+   pin(1 4)
+   pin(2 16)
+   pin(3 13)
+   pin(4 3)
+   pin(5 16)
+  )
+  circuit(6 INVX1 location(7800 0)
+   pin(0 13)
+   pin(1 5)
+   pin(2 16)
+   pin(3 13)
+   pin(4 4)
+   pin(5 16)
+  )
+  circuit(7 INVX1 location(9600 0)
+   pin(0 13)
+   pin(1 6)
+   pin(2 16)
+   pin(3 13)
+   pin(4 5)
+   pin(5 16)
+  )
+  circuit(8 INVX1 location(11400 0)
+   pin(0 13)
+   pin(1 7)
+   pin(2 16)
+   pin(3 13)
+   pin(4 6)
+   pin(5 16)
+  )
+  circuit(9 INVX1 location(13200 0)
+   pin(0 13)
+   pin(1 8)
+   pin(2 16)
+   pin(3 13)
+   pin(4 7)
+   pin(5 16)
+  )
+  circuit(10 INVX1 location(15000 0)
+   pin(0 13)
+   pin(1 9)
+   pin(2 16)
+   pin(3 13)
+   pin(4 8)
+   pin(5 16)
+  )
+  circuit(11 INVX1 location(16800 0)
+   pin(0 13)
+   pin(1 10)
+   pin(2 16)
+   pin(3 13)
+   pin(4 9)
+   pin(5 16)
+  )
+  circuit(12 INVX1 location(18600 0)
+   pin(0 13)
+   pin(1 11)
+   pin(2 16)
+   pin(3 13)
+   pin(4 10)
+   pin(5 16)
+  )
+  circuit(13 INVX1 location(20400 0)
+   pin(0 13)
+   pin(1 12)
+   pin(2 16)
+   pin(3 13)
+   pin(4 11)
+   pin(5 16)
+  )
+  circuit(14 INVX1 location(22200 0)
+   pin(0 13)
+   pin(1 14)
+   pin(2 16)
+   pin(3 13)
+   pin(4 12)
+   pin(5 16)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 8)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+  net(16 name(DUMMY))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Devices and their connections
+  device(1 NMOS
+   name($1)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 16)
+   terminal(D 1)
+   terminal(B 1)
+  )
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(2 6 match)
+   net(11 15 match)
+   net(3 7 match)
+   net(4 8 match)
+   net(5 9 match)
+   net(6 10 match)
+   net(7 11 match)
+   net(8 12 match)
+   net(9 13 match)
+   net(10 14 match)
+   net(1 16 match)
+   net(15 4 match)
+   net(12 3 match)
+   net(14 5 match)
+   net(13 2 match)
+   net(16 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   device(1 1 match)
+   circuit(4 2 match)
+   circuit(5 3 match)
+   circuit(6 4 match)
+   circuit(7 5 match)
+   circuit(8 6 match)
+   circuit(9 7 match)
+   circuit(10 8 match)
+   circuit(11 9 match)
+   circuit(12 10 match)
+   circuit(13 11 match)
+   circuit(14 12 match)
+   circuit(3 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2
new file mode 100644
index 000000000..6ae8d34f4
--- /dev/null
+++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2
@@ -0,0 +1,927 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (28300 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (1160 300))
+  )
+  net(2
+   rect(l11 (6050 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7850 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9650 2950) (900 300))
+  )
+  net(5
+   rect(l11 (11450 2950) (900 300))
+  )
+  net(6
+   rect(l11 (13250 2950) (900 300))
+  )
+  net(7
+   rect(l11 (15050 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16850 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18650 2950) (900 300))
+  )
+  net(10
+   rect(l11 (20450 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (22250 2950) (2900 300))
+   rect(l11 (-21980 590) (320 320))
+   rect(l11 (18570 -320) (320 320))
+   rect(l12 (-19150 -260) (200 200))
+   rect(l12 (18690 -200) (200 200))
+   rect(l13 (-18840 -300) (18890 400))
+   rect(l13 (-19070 -200) (0 0))
+   rect(l13 (-170 -200) (400 400))
+   rect(l13 (18490 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (22600 4500) (1400 3500))
+   rect(l3 (-23500 -3500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (25800 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-5090 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-22280 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (25720 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-4890 1010) (0 0))
+   rect(l11 (2800 -50) (0 0))
+   rect(l11 (-22150 -100) (0 0))
+   rect(l11 (19750 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-22750 -400) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (25900 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-5250 -1500) (500 1500))
+   rect(l9 (-22600 -1500) (500 1500))
+   rect(l9 (25400 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (25990 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-150 -100) (0 0))
+   rect(l13 (-150 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2490 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-150 -100) (0 0))
+   rect(l13 (-150 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (27010 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-3980 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-22280 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (24710 -290) (0 0))
+   rect(l11 (-3850 0) (0 0))
+   rect(l11 (-19200 -100) (0 0))
+   rect(l11 (24000 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l11 (-5150 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-22300 -350) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l10 (26250 -800) (500 1500))
+   rect(l10 (-4300 -1500) (500 1500))
+   rect(l10 (-22600 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4700 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6500 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(8300 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(10100 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11900 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13700 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15500 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(17300 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(19100 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20900 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(24700 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_io.lvsdb.2 b/testdata/lvs/ringo_simple_io.lvsdb.2
new file mode 100644
index 000000000..d3768aef4
--- /dev/null
+++ b/testdata/lvs/ringo_simple_io.lvsdb.2
@@ -0,0 +1,832 @@
+#%lvsdb-klayout
+J(
+ W(RINGO)
+ U(0.001)
+ L(l3 '1/0')
+ L(l4 '5/0')
+ L(l8 '8/0')
+ L(l11 '9/0')
+ L(l12 '10/0')
+ L(l13 '11/0')
+ L(l7)
+ L(l2)
+ L(l9)
+ L(l6)
+ L(l10)
+ C(l3 l3 l9)
+ C(l4 l4 l8)
+ C(l8 l4 l8 l11 l2 l9 l6 l10)
+ C(l11 l8 l11 l12)
+ C(l12 l11 l12 l13)
+ C(l13 l12 l13)
+ C(l7 l7)
+ C(l2 l8 l2)
+ C(l9 l3 l8 l9)
+ C(l6 l8 l6)
+ C(l10 l8 l10)
+ G(l7 SUBSTRATE)
+ G(l10 SUBSTRATE)
+ K(PMOS MOS4)
+ K(NMOS MOS4)
+ D(D$PMOS PMOS
+  T(S
+   R(l2 (-550 -750) (425 1500))
+  )
+  T(G
+   R(l4 (-125 -750) (250 1500))
+  )
+  T(D
+   R(l2 (125 -750) (450 1500))
+  )
+  T(B
+   R(l3 (-125 -750) (250 1500))
+  )
+ )
+ D(D$PMOS$1 PMOS
+  T(S
+   R(l2 (-575 -750) (450 1500))
+  )
+  T(G
+   R(l4 (-125 -750) (250 1500))
+  )
+  T(D
+   R(l2 (125 -750) (425 1500))
+  )
+  T(B
+   R(l3 (-125 -750) (250 1500))
+  )
+ )
+ D(D$PMOS$2 PMOS
+  T(S
+   R(l2 (-550 -750) (425 1500))
+  )
+  T(G
+   R(l4 (-125 -750) (250 1500))
+  )
+  T(D
+   R(l2 (125 -750) (425 1500))
+  )
+  T(B
+   R(l3 (-125 -750) (250 1500))
+  )
+ )
+ D(D$NMOS NMOS
+  T(S
+   R(l6 (-550 -475) (425 950))
+  )
+  T(G
+   R(l4 (-125 -475) (250 950))
+  )
+  T(D
+   R(l6 (125 -475) (450 950))
+  )
+  T(B
+   R(l7 (-125 -475) (250 950))
+  )
+ )
+ D(D$NMOS$1 NMOS
+  T(S
+   R(l6 (-575 -475) (450 950))
+  )
+  T(G
+   R(l4 (-125 -475) (250 950))
+  )
+  T(D
+   R(l6 (125 -475) (425 950))
+  )
+  T(B
+   R(l7 (-125 -475) (250 950))
+  )
+ )
+ D(D$NMOS$2 NMOS
+  T(S
+   R(l6 (-550 -475) (425 950))
+  )
+  T(G
+   R(l4 (-125 -475) (250 950))
+  )
+  T(D
+   R(l6 (125 -475) (425 950))
+  )
+  T(B
+   R(l7 (-125 -475) (250 950))
+  )
+ )
+ X(ND2X1
+  R((-100 400) (2600 7600))
+  N(1 I(VDD)
+   R(l8 (1110 5160) (180 180))
+   R(l8 (-180 920) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l11 (-240 -790) (300 1700))
+   R(l11 (-1350 0) (2400 800))
+   R(l11 (-1150 -400) (0 0))
+   R(l2 (-275 -2150) (425 1500))
+   R(l2 (-400 -1500) (425 1500))
+  )
+  N(2 I(OUT)
+   R(l8 (1810 1770) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (-1580 3760) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (1220 920) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (-180 370) (180 180))
+   Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   R(l11 (-110 1390) (300 1400))
+   Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   R(l11 (-140 -500) (0 0))
+   R(l11 (-1750 1100) (300 1400))
+   R(l11 (1100 -1700) (300 300))
+   R(l11 (-300 0) (300 1400))
+   R(l2 (-375 -1450) (425 1500))
+   R(l2 (-1800 -1500) (425 1500))
+   R(l6 (950 -4890) (425 950))
+  )
+  N(3 I(VSS)
+   R(l8 (410 1770) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-240 -1300) (300 1360))
+   R(l11 (-650 -2160) (2400 800))
+   R(l11 (-1150 -400) (0 0))
+   R(l6 (-950 860) (425 950))
+  )
+  N(4
+   R(l3 (-100 4500) (2600 3500))
+  )
+  N(5 I(B)
+   R(l4 (1425 2860) (250 1940))
+   R(l4 (-345 -950) (300 300))
+   R(l4 (-205 650) (250 2000))
+   R(l4 (-250 -2000) (250 2000))
+   R(l4 (-250 -5390) (250 1450))
+   R(l8 (-285 1050) (180 180))
+   R(l11 (-70 -90) (0 0))
+   R(l11 (-170 -150) (300 300))
+  )
+  N(6 I(A)
+   R(l4 (725 2860) (250 1940))
+   R(l4 (-325 -1850) (300 300))
+   R(l4 (-225 1550) (250 2000))
+   R(l4 (-250 -2000) (250 2000))
+   R(l4 (-250 -5390) (250 1450))
+   R(l8 (-265 150) (180 180))
+   R(l11 (-90 -90) (0 0))
+   R(l11 (-150 -150) (300 300))
+  )
+  N(7 I(SUBSTRATE))
+  N(8
+   R(l6 (975 1660) (425 950))
+   R(l6 (-400 -950) (425 950))
+  )
+  P(1 I(VDD))
+  P(2 I(OUT))
+  P(3 I(VSS))
+  P(4)
+  P(5 I(B))
+  P(6 I(A))
+  P(7 I(SUBSTRATE))
+  D(1 D$PMOS
+   Y(850 5800)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.6375)
+   E(AD 0.3375)
+   E(PS 3.85)
+   E(PD 1.95)
+   T(S 2)
+   T(G 6)
+   T(D 1)
+   T(B 4)
+  )
+  D(2 D$PMOS$1
+   Y(1550 5800)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.3375)
+   E(AD 0.6375)
+   E(PS 1.95)
+   E(PD 3.85)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(3 D$NMOS
+   Y(850 2135)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.40375)
+   E(AD 0.21375)
+   E(PS 2.75)
+   E(PD 1.4)
+   T(S 3)
+   T(G 6)
+   T(D 8)
+   T(B 7)
+  )
+  D(4 D$NMOS$1
+   Y(1550 2135)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.21375)
+   E(AD 0.40375)
+   E(PS 1.4)
+   E(PD 2.75)
+   T(S 8)
+   T(G 5)
+   T(D 2)
+   T(B 7)
+  )
+ )
+ X(INVX1
+  R((-100 400) (2000 7600))
+  N(1 I(VDD)
+   R(l8 (410 6260) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l11 (-240 -240) (300 1400))
+   R(l11 (-650 300) (1800 800))
+   R(l11 (-1450 -1100) (300 300))
+   R(l11 (300 400) (0 0))
+   R(l2 (-650 -2150) (425 1500))
+  )
+  N(2 I(OUT)
+   R(l8 (1110 5160) (180 180))
+   R(l8 (-180 920) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (-180 -4120) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-240 -790) (300 4790))
+   R(l11 (-150 -2500) (0 0))
+   R(l2 (-225 1050) (425 1500))
+   R(l6 (-425 -4890) (425 950))
+  )
+  N(3 I(VSS)
+   R(l8 (410 1770) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-240 -1300) (300 1360))
+   R(l11 (-650 -2160) (1800 800))
+   R(l11 (-850 -400) (0 0))
+   R(l6 (-650 860) (425 950))
+  )
+  N(4
+   R(l3 (-100 4500) (2000 3500))
+  )
+  N(5 I(IN)
+   R(l4 (725 2860) (250 1940))
+   R(l4 (-525 -1850) (300 300))
+   R(l4 (-25 1550) (250 2000))
+   R(l4 (-250 -2000) (250 2000))
+   R(l4 (-250 -5390) (250 1450))
+   R(l8 (-465 150) (180 180))
+   R(l11 (-90 -90) (0 0))
+   R(l11 (-150 -150) (300 300))
+  )
+  N(6 I(SUBSTRATE))
+  P(1 I(VDD))
+  P(2 I(OUT))
+  P(3 I(VSS))
+  P(4)
+  P(5 I(IN))
+  P(6 I(SUBSTRATE))
+  D(1 D$PMOS$2
+   Y(850 5800)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.6375)
+   E(AD 0.6375)
+   E(PS 3.85)
+   E(PD 3.85)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(2 D$NMOS$2
+   Y(850 2135)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.40375)
+   E(AD 0.40375)
+   E(PS 2.75)
+   E(PD 2.75)
+   T(S 3)
+   T(G 5)
+   T(D 2)
+   T(B 6)
+  )
+ )
+ X(RINGO
+  R((0 350) (25800 7650))
+  N(1
+   R(l11 (4040 2950) (610 300))
+  )
+  N(2
+   R(l11 (5550 2950) (900 300))
+  )
+  N(3
+   R(l11 (7350 2950) (900 300))
+  )
+  N(4
+   R(l11 (9150 2950) (900 300))
+  )
+  N(5
+   R(l11 (10950 2950) (900 300))
+  )
+  N(6
+   R(l11 (12750 2950) (900 300))
+  )
+  N(7
+   R(l11 (14550 2950) (900 300))
+  )
+  N(8
+   R(l11 (16350 2950) (900 300))
+  )
+  N(9
+   R(l11 (18150 2950) (900 300))
+  )
+  N(10
+   R(l11 (19950 2950) (900 300))
+  )
+  N(11 I(FB)
+   R(l11 (21750 2950) (900 300))
+   R(l11 (-19530 590) (320 320))
+   R(l11 (17820 -320) (320 320))
+   R(l12 (-18400 -260) (200 200))
+   R(l12 (17940 -200) (200 200))
+   R(l13 (-18040 -300) (17740 400))
+   R(l13 (-17920 -200) (0 0))
+   R(l13 (-220 -200) (400 400))
+   R(l13 (17740 -400) (400 400))
+  )
+  N(12 I(VDD)
+   R(l3 (500 4500) (1400 3500))
+   R(l3 (-1900 -3500) (600 3500))
+   R(l3 (23300 -3500) (1400 3500))
+   R(l3 (-100 -3500) (600 3500))
+   R(l8 (-24690 -1240) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (23220 370) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l11 (-21740 860) (0 0))
+   R(l11 (-2350 -450) (1200 800))
+   R(l11 (-750 -1450) (300 1400))
+   R(l11 (-100 -350) (0 0))
+   R(l11 (-1250 -400) (600 800))
+   R(l11 (23400 -800) (1200 800))
+   R(l11 (-750 -1450) (300 1400))
+   R(l11 (-100 -350) (0 0))
+   R(l11 (550 -400) (600 800))
+   R(l9 (-24850 -1500) (500 1500))
+   R(l9 (22900 -1500) (500 1500))
+  )
+  N(13 I(OUT)
+   R(l11 (23440 3840) (320 320))
+   R(l12 (-260 -260) (200 200))
+   R(l13 (-100 -100) (0 0))
+   R(l13 (-200 -200) (400 400))
+  )
+  N(14 I(ENABLE)
+   R(l11 (2440 2940) (320 320))
+   R(l12 (-260 -260) (200 200))
+   R(l13 (-100 -100) (0 0))
+   R(l13 (-200 -200) (400 400))
+  )
+  N(15 I(VSS)
+   R(l8 (1110 1610) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (23220 370) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-21740 -390) (0 0))
+   R(l11 (-1900 -400) (300 1400))
+   R(l11 (-750 -1450) (1200 800))
+   R(l11 (-550 -400) (0 0))
+   R(l11 (-1250 -400) (600 800))
+   R(l11 (23850 -750) (300 1400))
+   R(l11 (-750 -1450) (1200 800))
+   R(l11 (-550 -400) (0 0))
+   R(l11 (550 -400) (600 800))
+   R(l10 (-24850 -800) (500 1500))
+   R(l10 (22900 -1500) (500 1500))
+  )
+  P(11 I(FB))
+  P(12 I(VDD))
+  P(13 I(OUT))
+  P(14 I(ENABLE))
+  P(15 I(VSS))
+  X(1 ND2X1 Y(1800 0)
+   P(0 12)
+   P(1 1)
+   P(2 15)
+   P(3 12)
+   P(4 11)
+   P(5 14)
+   P(6 15)
+  )
+  X(2 INVX1 Y(4200 0)
+   P(0 12)
+   P(1 2)
+   P(2 15)
+   P(3 12)
+   P(4 1)
+   P(5 15)
+  )
+  X(3 INVX1 Y(6000 0)
+   P(0 12)
+   P(1 3)
+   P(2 15)
+   P(3 12)
+   P(4 2)
+   P(5 15)
+  )
+  X(4 INVX1 Y(7800 0)
+   P(0 12)
+   P(1 4)
+   P(2 15)
+   P(3 12)
+   P(4 3)
+   P(5 15)
+  )
+  X(5 INVX1 Y(9600 0)
+   P(0 12)
+   P(1 5)
+   P(2 15)
+   P(3 12)
+   P(4 4)
+   P(5 15)
+  )
+  X(6 INVX1 Y(11400 0)
+   P(0 12)
+   P(1 6)
+   P(2 15)
+   P(3 12)
+   P(4 5)
+   P(5 15)
+  )
+  X(7 INVX1 Y(13200 0)
+   P(0 12)
+   P(1 7)
+   P(2 15)
+   P(3 12)
+   P(4 6)
+   P(5 15)
+  )
+  X(8 INVX1 Y(15000 0)
+   P(0 12)
+   P(1 8)
+   P(2 15)
+   P(3 12)
+   P(4 7)
+   P(5 15)
+  )
+  X(9 INVX1 Y(16800 0)
+   P(0 12)
+   P(1 9)
+   P(2 15)
+   P(3 12)
+   P(4 8)
+   P(5 15)
+  )
+  X(10 INVX1 Y(18600 0)
+   P(0 12)
+   P(1 10)
+   P(2 15)
+   P(3 12)
+   P(4 9)
+   P(5 15)
+  )
+  X(11 INVX1 Y(20400 0)
+   P(0 12)
+   P(1 11)
+   P(2 15)
+   P(3 12)
+   P(4 10)
+   P(5 15)
+  )
+  X(12 INVX1 Y(22200 0)
+   P(0 12)
+   P(1 13)
+   P(2 15)
+   P(3 12)
+   P(4 11)
+   P(5 15)
+  )
+ )
+)
+H(
+ K(PMOS MOS4)
+ K(NMOS MOS4)
+ X(ND2X1
+  N(1 I(VDD))
+  N(2 I(OUT))
+  N(3 I(VSS))
+  N(4 I(NWELL))
+  N(5 I(B))
+  N(6 I(A))
+  N(7 I(BULK))
+  N(8 I('1'))
+  P(1 I(VDD))
+  P(2 I(OUT))
+  P(3 I(VSS))
+  P(4 I(NWELL))
+  P(5 I(B))
+  P(6 I(A))
+  P(7 I(BULK))
+  D(1 PMOS
+   I($1)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 1)
+   T(G 6)
+   T(D 2)
+   T(B 4)
+  )
+  D(2 PMOS
+   I($2)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(3 NMOS
+   I($3)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 3)
+   T(G 6)
+   T(D 8)
+   T(B 7)
+  )
+  D(4 NMOS
+   I($4)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 8)
+   T(G 5)
+   T(D 2)
+   T(B 7)
+  )
+ )
+ X(INVX1
+  N(1 I(VDD))
+  N(2 I(OUT))
+  N(3 I(VSS))
+  N(4 I(NWELL))
+  N(5 I(IN))
+  N(6 I(BULK))
+  P(1 I(VDD))
+  P(2 I(OUT))
+  P(3 I(VSS))
+  P(4 I(NWELL))
+  P(5 I(IN))
+  P(6 I(BULK))
+  D(1 PMOS
+   I($1)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(2 NMOS
+   I($2)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 3)
+   T(G 5)
+   T(D 2)
+   T(B 6)
+  )
+ )
+ X(RINGO
+  N(1 I(VSS))
+  N(2 I(VDD))
+  N(3 I(FB))
+  N(4 I(ENABLE))
+  N(5 I(OUT))
+  N(6 I('1'))
+  N(7 I('2'))
+  N(8 I('3'))
+  N(9 I('4'))
+  N(10 I('5'))
+  N(11 I('6'))
+  N(12 I('7'))
+  N(13 I('8'))
+  N(14 I('9'))
+  N(15 I('10'))
+  P(1 I(VSS))
+  P(2 I(VDD))
+  P(3 I(FB))
+  P(4 I(ENABLE))
+  P(5 I(OUT))
+  X(1 ND2X1 I($1)
+   P(0 2)
+   P(1 6)
+   P(2 1)
+   P(3 2)
+   P(4 3)
+   P(5 4)
+   P(6 1)
+  )
+  X(2 INVX1 I($2)
+   P(0 2)
+   P(1 7)
+   P(2 1)
+   P(3 2)
+   P(4 6)
+   P(5 1)
+  )
+  X(3 INVX1 I($3)
+   P(0 2)
+   P(1 8)
+   P(2 1)
+   P(3 2)
+   P(4 7)
+   P(5 1)
+  )
+  X(4 INVX1 I($4)
+   P(0 2)
+   P(1 9)
+   P(2 1)
+   P(3 2)
+   P(4 8)
+   P(5 1)
+  )
+  X(5 INVX1 I($5)
+   P(0 2)
+   P(1 10)
+   P(2 1)
+   P(3 2)
+   P(4 9)
+   P(5 1)
+  )
+  X(6 INVX1 I($6)
+   P(0 2)
+   P(1 11)
+   P(2 1)
+   P(3 2)
+   P(4 10)
+   P(5 1)
+  )
+  X(7 INVX1 I($7)
+   P(0 2)
+   P(1 12)
+   P(2 1)
+   P(3 2)
+   P(4 11)
+   P(5 1)
+  )
+  X(8 INVX1 I($8)
+   P(0 2)
+   P(1 13)
+   P(2 1)
+   P(3 2)
+   P(4 12)
+   P(5 1)
+  )
+  X(9 INVX1 I($9)
+   P(0 2)
+   P(1 14)
+   P(2 1)
+   P(3 2)
+   P(4 13)
+   P(5 1)
+  )
+  X(10 INVX1 I($10)
+   P(0 2)
+   P(1 15)
+   P(2 1)
+   P(3 2)
+   P(4 14)
+   P(5 1)
+  )
+  X(11 INVX1 I($11)
+   P(0 2)
+   P(1 3)
+   P(2 1)
+   P(3 2)
+   P(4 15)
+   P(5 1)
+  )
+  X(12 INVX1 I($12)
+   P(0 2)
+   P(1 5)
+   P(2 1)
+   P(3 2)
+   P(4 3)
+   P(5 1)
+  )
+ )
+)
+Z(
+ X(INVX1 INVX1 1
+  Z(
+   N(4 4 1)
+   N(5 5 1)
+   N(2 2 1)
+   N(6 6 1)
+   N(1 1 1)
+   N(3 3 1)
+   P(3 3 1)
+   P(4 4 1)
+   P(1 1 1)
+   P(5 5 1)
+   P(0 0 1)
+   P(2 2 1)
+   D(2 2 1)
+   D(1 1 1)
+  )
+ )
+ X(ND2X1 ND2X1 1
+  Z(
+   N(8 8 1)
+   N(4 4 1)
+   N(6 6 1)
+   N(5 5 1)
+   N(2 2 1)
+   N(7 7 1)
+   N(1 1 1)
+   N(3 3 1)
+   P(3 3 1)
+   P(5 5 1)
+   P(4 4 1)
+   P(1 1 1)
+   P(6 6 1)
+   P(0 0 1)
+   P(2 2 1)
+   D(3 3 1)
+   D(4 4 1)
+   D(1 1 1)
+   D(2 2 1)
+  )
+ )
+ X(RINGO RINGO 1
+  Z(
+   N(1 6 1)
+   N(10 15 1)
+   N(2 7 1)
+   N(3 8 1)
+   N(4 9 1)
+   N(5 10 1)
+   N(6 11 1)
+   N(7 12 1)
+   N(8 13 1)
+   N(9 14 1)
+   N(14 4 1)
+   N(11 3 1)
+   N(13 5 1)
+   N(12 2 1)
+   N(15 1 1)
+   P(3 3 1)
+   P(0 2 1)
+   P(2 4 1)
+   P(1 1 1)
+   P(4 0 1)
+   X(2 2 1)
+   X(3 3 1)
+   X(4 4 1)
+   X(5 5 1)
+   X(6 6 1)
+   X(7 7 1)
+   X(8 8 1)
+   X(9 9 1)
+   X(10 10 1)
+   X(11 11 1)
+   X(12 12 1)
+   X(1 1 1)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.2 b/testdata/lvs/ringo_simple_io2.lvsdb.2
new file mode 100644
index 000000000..4bfcca0be
--- /dev/null
+++ b/testdata/lvs/ringo_simple_io2.lvsdb.2
@@ -0,0 +1,908 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2
new file mode 100644
index 000000000..e500fb5a3
--- /dev/null
+++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2
@@ -0,0 +1,908 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(top)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(nd2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INV
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(top
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 nd2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INV location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INV location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INV location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INV location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INV location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INV location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INV location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INV location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INV location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INV location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INV location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INV INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(nd2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(top RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2
new file mode 100644
index 000000000..b06039efe
--- /dev/null
+++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2
@@ -0,0 +1,908 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(A))
+  net(6 name(B))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(A))
+  pin(6 name(B))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 5 match)
+   net(5 6 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 4 match)
+   pin(4 5 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2
new file mode 100644
index 000000000..55dbc29ba
--- /dev/null
+++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2
@@ -0,0 +1,910 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l5 '5/0')
+ layer(l14 '8/0')
+ layer(l17 '9/0')
+ layer(l18 '10/0')
+ layer(l19 '11/0')
+ layer(l8)
+ layer(l4)
+ layer(l15)
+ layer(l9)
+ layer(l16)
+
+ # Mask layer connectivity
+ connect(l3 l3 l15)
+ connect(l5 l5 l14)
+ connect(l14 l5 l14 l17 l4 l15 l9 l16)
+ connect(l17 l14 l17 l18)
+ connect(l18 l17 l18 l19)
+ connect(l19 l18 l19)
+ connect(l8 l8)
+ connect(l4 l14 l4)
+ connect(l15 l3 l14 l15)
+ connect(l9 l14 l9)
+ connect(l16 l14 l16)
+
+ # Global nets and connectivity
+ global(l8 SUBSTRATE)
+ global(l16 SUBSTRATE)
+
+ # Device class section
+ class(PM MOS4)
+ class(NM MOS4)
+ class(PMHV MOS4)
+ class(NMHV MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PM PM
+  terminal(S
+   rect(l4 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l5 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l4 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PM$1 PM
+  terminal(S
+   rect(l4 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l5 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l4 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PM$2 PM
+  terminal(S
+   rect(l4 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l5 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l4 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NM NM
+  terminal(S
+   rect(l9 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l5 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l9 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l8 (-125 -475) (250 950))
+  )
+ )
+ device(D$NM$1 NM
+  terminal(S
+   rect(l9 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l5 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l9 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l8 (-125 -475) (250 950))
+  )
+ )
+ device(D$NM$2 NM
+  terminal(S
+   rect(l9 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l5 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l9 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l8 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l14 (1110 5160) (180 180))
+   rect(l14 (-180 920) (180 180))
+   rect(l14 (-180 -730) (180 180))
+   rect(l17 (-240 -790) (300 1700))
+   rect(l17 (-1350 0) (2400 800))
+   rect(l17 (-1150 -400) (0 0))
+   rect(l4 (-275 -2150) (425 1500))
+   rect(l4 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l14 (1810 1770) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l14 (-1580 3760) (180 180))
+   rect(l14 (-180 -730) (180 180))
+   rect(l14 (-180 -730) (180 180))
+   rect(l14 (1220 920) (180 180))
+   rect(l14 (-180 -1280) (180 180))
+   rect(l14 (-180 370) (180 180))
+   polygon(l17 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l17 (-110 1390) (300 1400))
+   polygon(l17 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l17 (-140 -500) (0 0))
+   rect(l17 (-1750 1100) (300 1400))
+   rect(l17 (1100 -1700) (300 300))
+   rect(l17 (-300 0) (300 1400))
+   rect(l4 (-375 -1450) (425 1500))
+   rect(l4 (-1800 -1500) (425 1500))
+   rect(l9 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l14 (410 1770) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l17 (-240 -1300) (300 1360))
+   rect(l17 (-650 -2160) (2400 800))
+   rect(l17 (-1150 -400) (0 0))
+   rect(l9 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l5 (1425 2860) (250 1940))
+   rect(l5 (-345 -950) (300 300))
+   rect(l5 (-205 650) (250 2000))
+   rect(l5 (-250 -2000) (250 2000))
+   rect(l5 (-250 -5390) (250 1450))
+   rect(l14 (-285 1050) (180 180))
+   rect(l17 (-70 -90) (0 0))
+   rect(l17 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l5 (725 2860) (250 1940))
+   rect(l5 (-325 -1850) (300 300))
+   rect(l5 (-225 1550) (250 2000))
+   rect(l5 (-250 -2000) (250 2000))
+   rect(l5 (-250 -5390) (250 1450))
+   rect(l14 (-265 150) (180 180))
+   rect(l17 (-90 -90) (0 0))
+   rect(l17 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l9 (975 1660) (425 950))
+   rect(l9 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PM
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PM$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NM
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NM$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l14 (410 6260) (180 180))
+   rect(l14 (-180 -730) (180 180))
+   rect(l14 (-180 -730) (180 180))
+   rect(l17 (-240 -240) (300 1400))
+   rect(l17 (-650 300) (1800 800))
+   rect(l17 (-1450 -1100) (300 300))
+   rect(l17 (300 400) (0 0))
+   rect(l4 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l14 (1110 5160) (180 180))
+   rect(l14 (-180 920) (180 180))
+   rect(l14 (-180 -730) (180 180))
+   rect(l14 (-180 -4120) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l17 (-240 -790) (300 4790))
+   rect(l17 (-150 -2500) (0 0))
+   rect(l4 (-225 1050) (425 1500))
+   rect(l9 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l14 (410 1770) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l17 (-240 -1300) (300 1360))
+   rect(l17 (-650 -2160) (1800 800))
+   rect(l17 (-850 -400) (0 0))
+   rect(l9 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l5 (725 2860) (250 1940))
+   rect(l5 (-525 -1850) (300 300))
+   rect(l5 (-25 1550) (250 2000))
+   rect(l5 (-250 -2000) (250 2000))
+   rect(l5 (-250 -5390) (250 1450))
+   rect(l14 (-465 150) (180 180))
+   rect(l17 (-90 -90) (0 0))
+   rect(l17 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PM$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NM$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l17 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l17 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l17 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l17 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l17 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l17 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l17 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l17 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l17 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l17 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l17 (21750 2950) (900 300))
+   rect(l17 (-19530 590) (320 320))
+   rect(l17 (17820 -320) (320 320))
+   rect(l18 (-18400 -260) (200 200))
+   rect(l18 (17940 -200) (200 200))
+   rect(l19 (-18040 -300) (17740 400))
+   rect(l19 (-17920 -200) (0 0))
+   rect(l19 (-220 -200) (400 400))
+   rect(l19 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l14 (-24690 -1240) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l14 (-180 -1280) (180 180))
+   rect(l14 (23220 370) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l14 (-180 -1280) (180 180))
+   rect(l17 (-21740 860) (0 0))
+   rect(l17 (-2350 -450) (1200 800))
+   rect(l17 (-750 -1450) (300 1400))
+   rect(l17 (-100 -350) (0 0))
+   rect(l17 (-1250 -400) (600 800))
+   rect(l17 (23400 -800) (1200 800))
+   rect(l17 (-750 -1450) (300 1400))
+   rect(l17 (-100 -350) (0 0))
+   rect(l17 (550 -400) (600 800))
+   rect(l15 (-24850 -1500) (500 1500))
+   rect(l15 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l17 (23440 3840) (320 320))
+   rect(l18 (-260 -260) (200 200))
+   rect(l19 (-100 -100) (0 0))
+   rect(l19 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l17 (2440 2940) (320 320))
+   rect(l18 (-260 -260) (200 200))
+   rect(l19 (-100 -100) (0 0))
+   rect(l19 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l14 (1110 1610) (180 180))
+   rect(l14 (-180 -1280) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l14 (23220 370) (180 180))
+   rect(l14 (-180 -1280) (180 180))
+   rect(l14 (-180 370) (180 180))
+   rect(l17 (-21740 -390) (0 0))
+   rect(l17 (-1900 -400) (300 1400))
+   rect(l17 (-750 -1450) (1200 800))
+   rect(l17 (-550 -400) (0 0))
+   rect(l17 (-1250 -400) (600 800))
+   rect(l17 (23850 -750) (300 1400))
+   rect(l17 (-750 -1450) (1200 800))
+   rect(l17 (-550 -400) (0 0))
+   rect(l17 (550 -400) (600 800))
+   rect(l16 (-24850 -800) (500 1500))
+   rect(l16 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.2 b/testdata/lvs/ringo_simple_simplification.lvsdb.2
new file mode 100644
index 000000000..475506d1f
--- /dev/null
+++ b/testdata/lvs/ringo_simple_simplification.lvsdb.2
@@ -0,0 +1,1095 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-225 -1300) (675 450))
+   rect(l4 (0 -1100) (250 1950))
+   rect(l4 (-1225 -1850) (300 300))
+   rect(l4 (675 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-950 -2000) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (450 -5390) (250 1450))
+   rect(l4 (-950 -1450) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(2 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-1640 -240) (300 1400))
+   rect(l11 (-650 300) (2400 800))
+   rect(l11 (-2050 -1100) (300 300))
+   rect(l11 (1100 -300) (300 300))
+   rect(l11 (-1100 400) (0 0))
+   rect(l11 (800 -2100) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+  )
+  net(3 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+   rect(l6 (-450 -4890) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+  net(4 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (1220 -730) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-1640 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-650 0) (300 1360))
+   rect(l11 (-1100 -1760) (0 0))
+   rect(l6 (725 860) (425 950))
+   rect(l6 (-1800 -950) (425 950))
+  )
+  net(5
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(IN))
+  pin(2 name(VDD))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5)
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 5800)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0.975)
+   param(AD 0.975)
+   param(PS 5.8)
+   param(PD 5.8)
+   terminal(S 2)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 2135)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0.6175)
+   param(AD 0.6175)
+   param(PS 4.15)
+   param(PD 4.15)
+   terminal(S 4)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((600 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(4
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(5 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(6 name(VDD)
+   rect(l3 (1100 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-22340 860) (0 0))
+   rect(l11 (-1750 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(7 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(8 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(9 name(VSS)
+   rect(l8 (1710 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-22340 -390) (0 0))
+   rect(l11 (-1300 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+  net(10
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(11
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(12
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(13
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(14
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(15
+   rect(l11 (14550 2950) (900 300))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(FB))
+  pin(6 name(VDD))
+  pin(7 name(OUT))
+  pin(8 name(ENABLE))
+  pin(9 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 6)
+   pin(1 1)
+   pin(2 9)
+   pin(3 6)
+   pin(4 5)
+   pin(5 8)
+   pin(6 9)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 6)
+   pin(1 2)
+   pin(2 9)
+   pin(3 6)
+   pin(4 1)
+   pin(5 9)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 6)
+   pin(1 10)
+   pin(2 9)
+   pin(3 6)
+   pin(4 2)
+   pin(5 9)
+  )
+  circuit(4 INVX1 location(16800 0)
+   pin(0 6)
+   pin(1 3)
+   pin(2 9)
+   pin(3 6)
+   pin(4 11)
+   pin(5 9)
+  )
+  circuit(5 INVX1 location(18600 0)
+   pin(0 6)
+   pin(1 4)
+   pin(2 9)
+   pin(3 6)
+   pin(4 3)
+   pin(5 9)
+  )
+  circuit(6 INVX1 location(20400 0)
+   pin(0 6)
+   pin(1 5)
+   pin(2 9)
+   pin(3 6)
+   pin(4 4)
+   pin(5 9)
+  )
+  circuit(7 INVX2 location(22200 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 9)
+   pin(4 6)
+   pin(5 9)
+  )
+  circuit(17 INVX1 location(7800 0)
+   pin(0 6)
+   pin(1 12)
+   pin(2 9)
+   pin(3 6)
+   pin(4 10)
+   pin(5 9)
+  )
+  circuit(18 INVX1 location(9600 0)
+   pin(0 6)
+   pin(1 13)
+   pin(2 9)
+   pin(3 6)
+   pin(4 12)
+   pin(5 9)
+  )
+  circuit(19 INVX1 location(11400 0)
+   pin(0 6)
+   pin(1 14)
+   pin(2 9)
+   pin(3 6)
+   pin(4 13)
+   pin(5 9)
+  )
+  circuit(20 INVX1 location(13200 0)
+   pin(0 6)
+   pin(1 15)
+   pin(2 9)
+   pin(3 6)
+   pin(4 14)
+   pin(5 9)
+  )
+  circuit(21 INVX1 location(15000 0)
+   pin(0 6)
+   pin(1 11)
+   pin(2 9)
+   pin(3 6)
+   pin(4 15)
+   pin(5 9)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 8)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX2 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INVX2 INVX2 match
+  xref(
+   net(5 4 match)
+   net(1 5 match)
+   net(3 2 match)
+   net(6 6 match)
+   net(2 1 match)
+   net(4 3 match)
+   pin(4 3 match)
+   pin(0 4 match)
+   pin(2 1 match)
+   pin(5 5 match)
+   pin(1 0 match)
+   pin(3 2 match)
+   device(3 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(4 15 match)
+   net(2 7 match)
+   net(10 8 match)
+   net(12 9 match)
+   net(13 10 match)
+   net(14 11 match)
+   net(15 12 match)
+   net(11 13 match)
+   net(3 14 match)
+   net(8 4 match)
+   net(5 3 match)
+   net(7 5 match)
+   net(6 2 match)
+   net(9 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(17 4 match)
+   circuit(18 5 match)
+   circuit(19 6 match)
+   circuit(20 7 match)
+   circuit(21 8 match)
+   circuit(4 9 match)
+   circuit(5 10 match)
+   circuit(6 11 match)
+   circuit(7 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2
new file mode 100644
index 000000000..650cb1b5a
--- /dev/null
+++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2
@@ -0,0 +1,1095 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-225 -1300) (675 450))
+   rect(l4 (0 -1100) (250 1950))
+   rect(l4 (-1225 -1850) (300 300))
+   rect(l4 (675 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-950 -2000) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (450 -5390) (250 1450))
+   rect(l4 (-950 -1450) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(2 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-1640 -240) (300 1400))
+   rect(l11 (-650 300) (2400 800))
+   rect(l11 (-2050 -1100) (300 300))
+   rect(l11 (1100 -300) (300 300))
+   rect(l11 (-1100 400) (0 0))
+   rect(l11 (800 -2100) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+  )
+  net(3 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+   rect(l6 (-450 -4890) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+  net(4 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (1220 -730) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-1640 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-650 0) (300 1360))
+   rect(l11 (-1100 -1760) (0 0))
+   rect(l6 (725 860) (425 950))
+   rect(l6 (-1800 -950) (425 950))
+  )
+  net(5
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(IN))
+  pin(2 name(VDD))
+  pin(3 name(OUT))
+  pin(4 name(VSS))
+  pin(5)
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   device(D$PMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 5800)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0.975)
+   param(AD 0.975)
+   param(PS 5.8)
+   param(PD 5.8)
+   terminal(S 2)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 5)
+  )
+  device(3 D$NMOS
+   device(D$NMOS$1 location(700 0))
+   connect(0 S S)
+   connect(1 S D)
+   connect(0 G G)
+   connect(1 G G)
+   connect(0 D D)
+   connect(1 D S)
+   connect(0 B B)
+   connect(1 B B)
+   location(850 2135)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0.6175)
+   param(AD 0.6175)
+   param(PS 4.15)
+   param(PD 4.15)
+   terminal(S 4)
+   terminal(G 1)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((600 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(4
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(5 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(6 name(VDD)
+   rect(l3 (1100 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-22340 860) (0 0))
+   rect(l11 (-1750 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(7 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(8 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(9 name(VSS)
+   rect(l8 (1710 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-22340 -390) (0 0))
+   rect(l11 (-1300 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+  net(10
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(11
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(12
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(13
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(14
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(15
+   rect(l11 (14550 2950) (900 300))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(FB))
+  pin(6 name(VDD))
+  pin(7 name(OUT))
+  pin(8 name(ENABLE))
+  pin(9 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 6)
+   pin(1 1)
+   pin(2 9)
+   pin(3 6)
+   pin(4 5)
+   pin(5 8)
+   pin(6 9)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 6)
+   pin(1 2)
+   pin(2 9)
+   pin(3 6)
+   pin(4 1)
+   pin(5 9)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 6)
+   pin(1 10)
+   pin(2 9)
+   pin(3 6)
+   pin(4 2)
+   pin(5 9)
+  )
+  circuit(4 INVX1 location(16800 0)
+   pin(0 6)
+   pin(1 3)
+   pin(2 9)
+   pin(3 6)
+   pin(4 11)
+   pin(5 9)
+  )
+  circuit(5 INVX1 location(18600 0)
+   pin(0 6)
+   pin(1 4)
+   pin(2 9)
+   pin(3 6)
+   pin(4 3)
+   pin(5 9)
+  )
+  circuit(6 INVX1 location(20400 0)
+   pin(0 6)
+   pin(1 5)
+   pin(2 9)
+   pin(3 6)
+   pin(4 4)
+   pin(5 9)
+  )
+  circuit(7 INVX2 location(22200 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 9)
+   pin(4 6)
+   pin(5 9)
+  )
+  circuit(13 INVX1 location(7800 0)
+   pin(0 6)
+   pin(1 12)
+   pin(2 9)
+   pin(3 6)
+   pin(4 10)
+   pin(5 9)
+  )
+  circuit(14 INVX1 location(9600 0)
+   pin(0 6)
+   pin(1 13)
+   pin(2 9)
+   pin(3 6)
+   pin(4 12)
+   pin(5 9)
+  )
+  circuit(15 INVX1 location(11400 0)
+   pin(0 6)
+   pin(1 14)
+   pin(2 9)
+   pin(3 6)
+   pin(4 13)
+   pin(5 9)
+  )
+  circuit(16 INVX1 location(13200 0)
+   pin(0 6)
+   pin(1 15)
+   pin(2 9)
+   pin(3 6)
+   pin(4 14)
+   pin(5 9)
+  )
+  circuit(17 INVX1 location(15000 0)
+   pin(0 6)
+   pin(1 11)
+   pin(2 9)
+   pin(3 6)
+   pin(4 15)
+   pin(5 9)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 8)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(INVX2
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 3)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.9)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX2 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(INVX2 INVX2 match
+  xref(
+   net(5 4 match)
+   net(1 5 match)
+   net(3 2 match)
+   net(6 6 match)
+   net(2 1 match)
+   net(4 3 match)
+   pin(4 3 match)
+   pin(0 4 match)
+   pin(2 1 match)
+   pin(5 5 match)
+   pin(1 0 match)
+   pin(3 2 match)
+   device(3 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(4 15 match)
+   net(2 7 match)
+   net(10 8 match)
+   net(12 9 match)
+   net(13 10 match)
+   net(14 11 match)
+   net(15 12 match)
+   net(11 13 match)
+   net(3 14 match)
+   net(8 4 match)
+   net(5 3 match)
+   net(7 5 match)
+   net(6 2 match)
+   net(9 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(13 4 match)
+   circuit(14 5 match)
+   circuit(15 6 match)
+   circuit(16 7 match)
+   circuit(17 8 match)
+   circuit(4 9 match)
+   circuit(5 10 match)
+   circuit(6 11 match)
+   circuit(7 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/ringo_simple_with_tol.lvsdb.2 b/testdata/lvs/ringo_simple_with_tol.lvsdb.2
new file mode 100644
index 000000000..6316f5d39
--- /dev/null
+++ b/testdata/lvs/ringo_simple_with_tol.lvsdb.2
@@ -0,0 +1,908 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(RINGO)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l3 '1/0')
+ layer(l4 '5/0')
+ layer(l8 '8/0')
+ layer(l11 '9/0')
+ layer(l12 '10/0')
+ layer(l13 '11/0')
+ layer(l7)
+ layer(l2)
+ layer(l9)
+ layer(l6)
+ layer(l10)
+
+ # Mask layer connectivity
+ connect(l3 l3 l9)
+ connect(l4 l4 l8)
+ connect(l8 l4 l8 l11 l2 l9 l6 l10)
+ connect(l11 l8 l11 l12)
+ connect(l12 l11 l12 l13)
+ connect(l13 l12 l13)
+ connect(l7 l7)
+ connect(l2 l8 l2)
+ connect(l9 l3 l8 l9)
+ connect(l6 l8 l6)
+ connect(l10 l8 l10)
+
+ # Global nets and connectivity
+ global(l7 SUBSTRATE)
+ global(l10 SUBSTRATE)
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$PMOS PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (450 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$1 PMOS
+  terminal(S
+   rect(l2 (-575 -750) (450 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$PMOS$2 PMOS
+  terminal(S
+   rect(l2 (-550 -750) (425 1500))
+  )
+  terminal(G
+   rect(l4 (-125 -750) (250 1500))
+  )
+  terminal(D
+   rect(l2 (125 -750) (425 1500))
+  )
+  terminal(B
+   rect(l3 (-125 -750) (250 1500))
+  )
+ )
+ device(D$NMOS NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (450 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$1 NMOS
+  terminal(S
+   rect(l6 (-575 -475) (450 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+ device(D$NMOS$2 NMOS
+  terminal(S
+   rect(l6 (-550 -475) (425 950))
+  )
+  terminal(G
+   rect(l4 (-125 -475) (250 950))
+  )
+  terminal(D
+   rect(l6 (125 -475) (425 950))
+  )
+  terminal(B
+   rect(l7 (-125 -475) (250 950))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Circuit boundary
+  rect((-100 400) (2600 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -790) (300 1700))
+   rect(l11 (-1350 0) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l2 (-275 -2150) (425 1500))
+   rect(l2 (-400 -1500) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1810 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-1580 3760) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (1220 920) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   rect(l11 (-110 1390) (300 1400))
+   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   rect(l11 (-140 -500) (0 0))
+   rect(l11 (-1750 1100) (300 1400))
+   rect(l11 (1100 -1700) (300 300))
+   rect(l11 (-300 0) (300 1400))
+   rect(l2 (-375 -1450) (425 1500))
+   rect(l2 (-1800 -1500) (425 1500))
+   rect(l6 (950 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (2400 800))
+   rect(l11 (-1150 -400) (0 0))
+   rect(l6 (-950 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2600 3500))
+  )
+  net(5 name(B)
+   rect(l4 (1425 2860) (250 1940))
+   rect(l4 (-345 -950) (300 300))
+   rect(l4 (-205 650) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-285 1050) (180 180))
+   rect(l11 (-70 -90) (0 0))
+   rect(l11 (-170 -150) (300 300))
+  )
+  net(6 name(A)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-325 -1850) (300 300))
+   rect(l4 (-225 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-265 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(7 name(SUBSTRATE))
+  net(8
+   rect(l6 (975 1660) (425 950))
+   rect(l6 (-400 -950) (425 950))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.3375)
+   param(PS 3.85)
+   param(PD 1.95)
+   terminal(S 2)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 D$PMOS$1
+   location(1550 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.3375)
+   param(AD 0.6375)
+   param(PS 1.95)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(3 D$NMOS
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.21375)
+   param(PS 2.75)
+   param(PD 1.4)
+   terminal(S 3)
+   terminal(G 6)
+   terminal(D 8)
+   terminal(B 7)
+  )
+  device(4 D$NMOS$1
+   location(1550 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.21375)
+   param(AD 0.40375)
+   param(PS 1.4)
+   param(PD 2.75)
+   terminal(S 8)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Circuit boundary
+  rect((-100 400) (2000 7600))
+
+  # Nets with their geometries
+  net(1 name(VDD)
+   rect(l8 (410 6260) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l11 (-240 -240) (300 1400))
+   rect(l11 (-650 300) (1800 800))
+   rect(l11 (-1450 -1100) (300 300))
+   rect(l11 (300 400) (0 0))
+   rect(l2 (-650 -2150) (425 1500))
+  )
+  net(2 name(OUT)
+   rect(l8 (1110 5160) (180 180))
+   rect(l8 (-180 920) (180 180))
+   rect(l8 (-180 -730) (180 180))
+   rect(l8 (-180 -4120) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -790) (300 4790))
+   rect(l11 (-150 -2500) (0 0))
+   rect(l2 (-225 1050) (425 1500))
+   rect(l6 (-425 -4890) (425 950))
+  )
+  net(3 name(VSS)
+   rect(l8 (410 1770) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-240 -1300) (300 1360))
+   rect(l11 (-650 -2160) (1800 800))
+   rect(l11 (-850 -400) (0 0))
+   rect(l6 (-650 860) (425 950))
+  )
+  net(4
+   rect(l3 (-100 4500) (2000 3500))
+  )
+  net(5 name(IN)
+   rect(l4 (725 2860) (250 1940))
+   rect(l4 (-525 -1850) (300 300))
+   rect(l4 (-25 1550) (250 2000))
+   rect(l4 (-250 -2000) (250 2000))
+   rect(l4 (-250 -5390) (250 1450))
+   rect(l8 (-465 150) (180 180))
+   rect(l11 (-90 -90) (0 0))
+   rect(l11 (-150 -150) (300 300))
+  )
+  net(6 name(SUBSTRATE))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4)
+  pin(5 name(IN))
+  pin(6 name(SUBSTRATE))
+
+  # Devices and their connections
+  device(1 D$PMOS$2
+   location(850 5800)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0.6375)
+   param(AD 0.6375)
+   param(PS 3.85)
+   param(PD 3.85)
+   terminal(S 1)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 D$NMOS$2
+   location(850 2135)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0.40375)
+   param(AD 0.40375)
+   param(PS 2.75)
+   param(PD 2.75)
+   terminal(S 3)
+   terminal(G 5)
+   terminal(D 2)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Circuit boundary
+  rect((0 350) (25800 7650))
+
+  # Nets with their geometries
+  net(1
+   rect(l11 (4040 2950) (610 300))
+  )
+  net(2
+   rect(l11 (5550 2950) (900 300))
+  )
+  net(3
+   rect(l11 (7350 2950) (900 300))
+  )
+  net(4
+   rect(l11 (9150 2950) (900 300))
+  )
+  net(5
+   rect(l11 (10950 2950) (900 300))
+  )
+  net(6
+   rect(l11 (12750 2950) (900 300))
+  )
+  net(7
+   rect(l11 (14550 2950) (900 300))
+  )
+  net(8
+   rect(l11 (16350 2950) (900 300))
+  )
+  net(9
+   rect(l11 (18150 2950) (900 300))
+  )
+  net(10
+   rect(l11 (19950 2950) (900 300))
+  )
+  net(11 name(FB)
+   rect(l11 (21750 2950) (900 300))
+   rect(l11 (-19530 590) (320 320))
+   rect(l11 (17820 -320) (320 320))
+   rect(l12 (-18400 -260) (200 200))
+   rect(l12 (17940 -200) (200 200))
+   rect(l13 (-18040 -300) (17740 400))
+   rect(l13 (-17920 -200) (0 0))
+   rect(l13 (-220 -200) (400 400))
+   rect(l13 (17740 -400) (400 400))
+  )
+  net(12 name(VDD)
+   rect(l3 (500 4500) (1400 3500))
+   rect(l3 (-1900 -3500) (600 3500))
+   rect(l3 (23300 -3500) (1400 3500))
+   rect(l3 (-100 -3500) (600 3500))
+   rect(l8 (-24690 -1240) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l11 (-21740 860) (0 0))
+   rect(l11 (-2350 -450) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23400 -800) (1200 800))
+   rect(l11 (-750 -1450) (300 1400))
+   rect(l11 (-100 -350) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l9 (-24850 -1500) (500 1500))
+   rect(l9 (22900 -1500) (500 1500))
+  )
+  net(13 name(OUT)
+   rect(l11 (23440 3840) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(14 name(ENABLE)
+   rect(l11 (2440 2940) (320 320))
+   rect(l12 (-260 -260) (200 200))
+   rect(l13 (-100 -100) (0 0))
+   rect(l13 (-200 -200) (400 400))
+  )
+  net(15 name(VSS)
+   rect(l8 (1110 1610) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l8 (23220 370) (180 180))
+   rect(l8 (-180 -1280) (180 180))
+   rect(l8 (-180 370) (180 180))
+   rect(l11 (-21740 -390) (0 0))
+   rect(l11 (-1900 -400) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (-1250 -400) (600 800))
+   rect(l11 (23850 -750) (300 1400))
+   rect(l11 (-750 -1450) (1200 800))
+   rect(l11 (-550 -400) (0 0))
+   rect(l11 (550 -400) (600 800))
+   rect(l10 (-24850 -800) (500 1500))
+   rect(l10 (22900 -1500) (500 1500))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(11 name(FB))
+  pin(12 name(VDD))
+  pin(13 name(OUT))
+  pin(14 name(ENABLE))
+  pin(15 name(VSS))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 location(1800 0)
+   pin(0 12)
+   pin(1 1)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 14)
+   pin(6 15)
+  )
+  circuit(2 INVX1 location(4200 0)
+   pin(0 12)
+   pin(1 2)
+   pin(2 15)
+   pin(3 12)
+   pin(4 1)
+   pin(5 15)
+  )
+  circuit(3 INVX1 location(6000 0)
+   pin(0 12)
+   pin(1 3)
+   pin(2 15)
+   pin(3 12)
+   pin(4 2)
+   pin(5 15)
+  )
+  circuit(4 INVX1 location(7800 0)
+   pin(0 12)
+   pin(1 4)
+   pin(2 15)
+   pin(3 12)
+   pin(4 3)
+   pin(5 15)
+  )
+  circuit(5 INVX1 location(9600 0)
+   pin(0 12)
+   pin(1 5)
+   pin(2 15)
+   pin(3 12)
+   pin(4 4)
+   pin(5 15)
+  )
+  circuit(6 INVX1 location(11400 0)
+   pin(0 12)
+   pin(1 6)
+   pin(2 15)
+   pin(3 12)
+   pin(4 5)
+   pin(5 15)
+  )
+  circuit(7 INVX1 location(13200 0)
+   pin(0 12)
+   pin(1 7)
+   pin(2 15)
+   pin(3 12)
+   pin(4 6)
+   pin(5 15)
+  )
+  circuit(8 INVX1 location(15000 0)
+   pin(0 12)
+   pin(1 8)
+   pin(2 15)
+   pin(3 12)
+   pin(4 7)
+   pin(5 15)
+  )
+  circuit(9 INVX1 location(16800 0)
+   pin(0 12)
+   pin(1 9)
+   pin(2 15)
+   pin(3 12)
+   pin(4 8)
+   pin(5 15)
+  )
+  circuit(10 INVX1 location(18600 0)
+   pin(0 12)
+   pin(1 10)
+   pin(2 15)
+   pin(3 12)
+   pin(4 9)
+   pin(5 15)
+  )
+  circuit(11 INVX1 location(20400 0)
+   pin(0 12)
+   pin(1 11)
+   pin(2 15)
+   pin(3 12)
+   pin(4 10)
+   pin(5 15)
+  )
+  circuit(12 INVX1 location(22200 0)
+   pin(0 12)
+   pin(1 13)
+   pin(2 15)
+   pin(3 12)
+   pin(4 11)
+   pin(5 15)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(PMOS MOS4)
+ class(NMOS MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(ND2X1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(B))
+  net(6 name(A))
+  net(7 name(BULK))
+  net(8 name('1'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(B))
+  pin(6 name(A))
+  pin(7 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.251)
+   param(W 1.6)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 4)
+  )
+  device(2 PMOS
+   name($2)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(3 NMOS
+   name($3)
+   param(L 0.26)
+   param(W 1)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 7)
+  )
+  device(4 NMOS
+   name($4)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 8)
+   terminal(B 7)
+  )
+
+ )
+ circuit(INVX1
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(OUT))
+  net(3 name(VSS))
+  net(4 name(NWELL))
+  net(5 name(IN))
+  net(6 name(BULK))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(OUT))
+  pin(3 name(VSS))
+  pin(4 name(NWELL))
+  pin(5 name(IN))
+  pin(6 name(BULK))
+
+  # Devices and their connections
+  device(1 PMOS
+   name($1)
+   param(L 0.25)
+   param(W 1.5)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 1)
+   terminal(B 4)
+  )
+  device(2 NMOS
+   name($2)
+   param(L 0.25)
+   param(W 0.95)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 5)
+   terminal(D 3)
+   terminal(B 6)
+  )
+
+ )
+ circuit(RINGO
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name(FB))
+  net(4 name(ENABLE))
+  net(5 name(OUT))
+  net(6 name('1'))
+  net(7 name('2'))
+  net(8 name('3'))
+  net(9 name('4'))
+  net(10 name('5'))
+  net(11 name('6'))
+  net(12 name('7'))
+  net(13 name('8'))
+  net(14 name('9'))
+  net(15 name('10'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name(FB))
+  pin(4 name(ENABLE))
+  pin(5 name(OUT))
+
+  # Subcircuits and their connections
+  circuit(1 ND2X1 name($1)
+   pin(0 2)
+   pin(1 6)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 4)
+   pin(6 1)
+  )
+  circuit(2 INVX1 name($2)
+   pin(0 2)
+   pin(1 7)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+   pin(5 1)
+  )
+  circuit(3 INVX1 name($3)
+   pin(0 2)
+   pin(1 8)
+   pin(2 1)
+   pin(3 2)
+   pin(4 7)
+   pin(5 1)
+  )
+  circuit(4 INVX1 name($4)
+   pin(0 2)
+   pin(1 9)
+   pin(2 1)
+   pin(3 2)
+   pin(4 8)
+   pin(5 1)
+  )
+  circuit(5 INVX1 name($5)
+   pin(0 2)
+   pin(1 10)
+   pin(2 1)
+   pin(3 2)
+   pin(4 9)
+   pin(5 1)
+  )
+  circuit(6 INVX1 name($6)
+   pin(0 2)
+   pin(1 11)
+   pin(2 1)
+   pin(3 2)
+   pin(4 10)
+   pin(5 1)
+  )
+  circuit(7 INVX1 name($7)
+   pin(0 2)
+   pin(1 12)
+   pin(2 1)
+   pin(3 2)
+   pin(4 11)
+   pin(5 1)
+  )
+  circuit(8 INVX1 name($8)
+   pin(0 2)
+   pin(1 13)
+   pin(2 1)
+   pin(3 2)
+   pin(4 12)
+   pin(5 1)
+  )
+  circuit(9 INVX1 name($9)
+   pin(0 2)
+   pin(1 14)
+   pin(2 1)
+   pin(3 2)
+   pin(4 13)
+   pin(5 1)
+  )
+  circuit(10 INVX1 name($10)
+   pin(0 2)
+   pin(1 15)
+   pin(2 1)
+   pin(3 2)
+   pin(4 14)
+   pin(5 1)
+  )
+  circuit(11 INVX1 name($11)
+   pin(0 2)
+   pin(1 3)
+   pin(2 1)
+   pin(3 2)
+   pin(4 15)
+   pin(5 1)
+  )
+  circuit(12 INVX1 name($12)
+   pin(0 2)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 3)
+   pin(5 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(INVX1 INVX1 match
+  xref(
+   net(4 4 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(6 6 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(5 5 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(2 2 match)
+   device(1 1 match)
+  )
+ )
+ circuit(ND2X1 ND2X1 match
+  xref(
+   net(8 8 match)
+   net(4 4 match)
+   net(6 6 match)
+   net(5 5 match)
+   net(2 2 match)
+   net(7 7 match)
+   net(1 1 match)
+   net(3 3 match)
+   pin(3 3 match)
+   pin(5 5 match)
+   pin(4 4 match)
+   pin(1 1 match)
+   pin(6 6 match)
+   pin(0 0 match)
+   pin(2 2 match)
+   device(3 3 match)
+   device(4 4 match)
+   device(1 1 match)
+   device(2 2 match)
+  )
+ )
+ circuit(RINGO RINGO match
+  xref(
+   net(1 6 match)
+   net(10 15 match)
+   net(2 7 match)
+   net(3 8 match)
+   net(4 9 match)
+   net(5 10 match)
+   net(6 11 match)
+   net(7 12 match)
+   net(8 13 match)
+   net(9 14 match)
+   net(14 4 match)
+   net(11 3 match)
+   net(13 5 match)
+   net(12 2 match)
+   net(15 1 match)
+   pin(3 3 match)
+   pin(0 2 match)
+   pin(2 4 match)
+   pin(1 1 match)
+   pin(4 0 match)
+   circuit(2 2 match)
+   circuit(3 3 match)
+   circuit(4 4 match)
+   circuit(5 5 match)
+   circuit(6 6 match)
+   circuit(7 7 match)
+   circuit(8 8 match)
+   circuit(9 9 match)
+   circuit(10 10 match)
+   circuit(11 11 match)
+   circuit(12 12 match)
+   circuit(1 1 match)
+  )
+ )
+)
diff --git a/testdata/lvs/test_22a.lvsdb.2 b/testdata/lvs/test_22a.lvsdb.2
new file mode 100644
index 000000000..b2354cc21
--- /dev/null
+++ b/testdata/lvs/test_22a.lvsdb.2
@@ -0,0 +1,2590 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(SP6TArray_2X4)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1)
+ layer(l2)
+ layer(l3)
+ layer(l4)
+ layer(l5 '64/20')
+ layer(l6)
+ layer(l7 '66/20')
+ layer(l8)
+ layer(l9 '67/20')
+ layer(l10)
+ layer(l11 '68/20')
+ layer(l12 '68/16')
+ layer(l13 '69/20')
+ layer(l14 '69/16')
+ layer(l15)
+ layer(l16)
+ layer(l17)
+ layer(l18)
+ layer(l19)
+ layer(l20)
+ layer(l21 '66/44')
+ layer(l22 '66/20')
+ layer(l23 '67/44')
+ layer(l24 '68/44')
+ layer(l25)
+ layer(l26)
+ layer(l27)
+
+ # Mask layer connectivity
+ connect(l1 l1)
+ connect(l2 l2 l3 l4 l6 l21)
+ connect(l3 l2 l3)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5)
+ connect(l6 l2 l6)
+ connect(l7 l7 l8)
+ connect(l8 l7 l8)
+ connect(l9 l9 l10 l21 l23)
+ connect(l10 l9 l10)
+ connect(l11 l11 l12 l23 l24)
+ connect(l12 l11 l12)
+ connect(l13 l13 l14 l24 l25)
+ connect(l14 l13 l14)
+ connect(l15 l15 l16 l25 l26)
+ connect(l16 l15 l16)
+ connect(l17 l17 l18 l26 l27)
+ connect(l18 l17 l18)
+ connect(l19 l19 l20 l27)
+ connect(l20 l19 l20)
+ connect(l21 l2 l9 l21 l22)
+ connect(l22 l21 l22)
+ connect(l23 l9 l11 l23)
+ connect(l24 l11 l13 l24)
+ connect(l25 l13 l15 l25)
+ connect(l26 l15 l17 l26)
+ connect(l27 l17 l19 l27)
+
+ # Global nets and connectivity
+ global(l1 vss)
+ global(l6 vss)
+
+ # Device class section
+ class(active_res RES)
+ class(poly_res RES)
+ class(sky130_fd_pr__diode_pw2nd_05v5 DIODE)
+ class(sky130_fd_pr__diode_pd2nw_05v5 DIODE)
+ class(sky130_fd_pr__nfet_01v8__model MOS4)
+ class(sky130_fd_pr__nfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__nfet_g5v0d10v5__model MOS4)
+ class(sky130_fd_pr__pfet_01v8__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_hvt__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__pfet_g5v0d10v5__model MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$sky130_fd_pr__nfet_01v8__model sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   polygon(l2 (75 -210) (0 420) (105 0) (0 340) (420 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-315 -835) (0 420) (105 0) (0 340) (420 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   rect(l2 (-210 75) (420 280))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$2 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -355) (420 280))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$4 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -210) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (280 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$5 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-355 -210) (280 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   polygon(l2 (75 -210) (0 420) (105 0) (0 340) (420 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$6 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-210 -835) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   rect(l2 (-210 75) (420 280))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$7 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -355) (420 280))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$8 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (280 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$9 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-355 -210) (280 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$10 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -210) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$11 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$1 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (280 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$2 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-355 -210) (280 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$3 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TArray_2X4
+
+  # Circuit boundary
+  rect((-385 -305) (9490 6160))
+
+  # Nets with their geometries
+  net(1 name(vdd)
+   rect(l2 (-205 -125) (9130 250))
+   rect(l2 (-9050 270) (265 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l2 (-9050 4610) (9130 250))
+   rect(l2 (-9050 -940) (265 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l4 (-9050 -5280) (9130 250))
+   rect(l4 (-9130 5300) (9130 250))
+   rect(l5 (-7130 -5980) (2950 1300))
+   rect(l5 (-5130 -1300) (2950 1300))
+   rect(l5 (1410 -1300) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l5 (-9490 3560) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l9 (-9270 -5940) (2510 170))
+   rect(l9 (-330 -170) (2510 170))
+   rect(l9 (-330 -170) (2510 170))
+   rect(l9 (-330 -170) (2510 170))
+   rect(l9 (-8970 0) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-8970 4695) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (1930 0) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (1930 0) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (1930 0) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
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+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
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+   rect(l11 (-260 -320) (260 320))
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+   rect(l13 (-2500 -260) (2500 260))
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+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
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+   rect(l14 (-2500 -260) (2500 260))
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+   rect(l14 (-6860 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
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+   rect(l14 (-2500 -260) (4680 260))
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+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-8890 435) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-8890 4775) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 435) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -775) (170 170))
+   rect(l21 (-170 435) (170 170))
+   rect(l23 (-8890 -5720) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-8890 5380) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-8880 -5710) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-8870 5400) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+  )
+  net(2 name('bl[0]')
+   rect(l2 (395 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(3 name('bl_n[0]')
+   rect(l2 (1365 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -290) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(4 name('bl[1]')
+   rect(l2 (2575 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(5 name('bl_n[1]')
+   rect(l2 (3545 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -290) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -290) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(6 name('bl[2]')
+   rect(l2 (4755 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(7 name('bl_n[2]')
+   rect(l2 (5725 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(8 name('bl[3]')
+   rect(l2 (6935 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(9 name('bl_n[3]')
+   rect(l2 (7905 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(10
+   rect(l2 (1445 395) (445 420))
+   polygon(l2 (-525 910) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+   polygon(l9 (-405 -1280) (0 560) (-245 0) (0 170) (245 0) (0 840) (170 0) (0 -1570))
+   rect(l21 (-335 560) (170 170))
+   rect(l21 (-5 -650) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l22 (-1365 -980) (950 150))
+   rect(l22 (-1100 -840) (150 2010))
+   rect(l22 (950 -1320) (330 270))
+  )
+  net(11
+   rect(l7 (290 955) (950 150))
+   rect(l7 (-1100 -840) (150 2010))
+   rect(l7 (950 -1320) (330 270))
+  )
+  net(12
+   rect(l2 (290 395) (445 420))
+   polygon(l2 (-445 910) (0 420) (105 0) (0 340) (420 0) (0 -760))
+   polygon(l9 (-290 -1280) (0 1570) (170 0) (0 -480) (245 0) (0 -170) (-245 0) (0 -920))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-5 -570) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (0 -150) (950 150))
+   rect(l22 (0 -1320) (150 2010))
+  )
+  net(13
+   rect(l7 (940 1435) (950 150))
+   rect(l7 (-1280 -270) (330 270))
+   rect(l7 (950 -1320) (150 2010))
+  )
+  net(14
+   rect(l7 (2470 955) (950 150))
+   rect(l7 (-1100 -840) (150 2010))
+   rect(l7 (950 -1320) (330 270))
+  )
+  net(15
+   polygon(l2 (3545 1725) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+   rect(l2 (-445 -1330) (445 420))
+   polygon(l9 (-405 -370) (0 560) (-245 0) (0 170) (245 0) (0 840) (170 0) (0 -1570))
+   rect(l21 (-335 560) (170 170))
+   rect(l21 (-5 590) (170 170))
+   rect(l21 (-170 -1410) (170 170))
+   rect(l22 (-1365 260) (950 150))
+   rect(l22 (-1100 -840) (150 2010))
+   rect(l22 (950 -1320) (330 270))
+  )
+  net(16
+   polygon(l2 (2470 1725) (0 420) (105 0) (0 340) (420 0) (0 -760))
+   rect(l2 (-525 -1330) (445 420))
+   polygon(l9 (-210 -370) (0 1570) (170 0) (0 -480) (245 0) (0 -170) (-245 0) (0 -920))
+   rect(l21 (-170 1320) (170 170))
+   rect(l21 (-170 -1410) (170 170))
+   rect(l21 (-5 670) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (0 -150) (950 150))
+   rect(l22 (0 -1320) (150 2010))
+  )
+  net(17
+   rect(l7 (3120 1435) (950 150))
+   rect(l7 (-1280 -270) (330 270))
+   rect(l7 (950 -1320) (150 2010))
+  )
+  net(18
+   rect(l2 (5805 395) (445 420))
+   polygon(l2 (-525 910) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+   polygon(l9 (-405 -1280) (0 560) (-245 0) (0 170) (245 0) (0 840) (170 0) (0 -1570))
+   rect(l21 (-335 560) (170 170))
+   rect(l21 (-5 -650) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l22 (-1365 -980) (950 150))
+   rect(l22 (-1100 -840) (150 2010))
+   rect(l22 (950 -1320) (330 270))
+  )
+  net(19
+   rect(l7 (4650 955) (950 150))
+   rect(l7 (-1100 -840) (150 2010))
+   rect(l7 (950 -1320) (330 270))
+  )
+  net(20
+   rect(l2 (4650 395) (445 420))
+   polygon(l2 (-445 910) (0 420) (105 0) (0 340) (420 0) (0 -760))
+   polygon(l9 (-290 -1280) (0 1570) (170 0) (0 -480) (245 0) (0 -170) (-245 0) (0 -920))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-5 -570) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (0 -150) (950 150))
+   rect(l22 (0 -1320) (150 2010))
+  )
+  net(21
+   rect(l7 (5300 1435) (950 150))
+   rect(l7 (-1280 -270) (330 270))
+   rect(l7 (950 -1320) (150 2010))
+  )
+  net(22
+   rect(l2 (7985 395) (445 420))
+   polygon(l2 (-525 910) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+   polygon(l9 (-405 -1280) (0 560) (-245 0) (0 170) (245 0) (0 840) (170 0) (0 -1570))
+   rect(l21 (-335 560) (170 170))
+   rect(l21 (-5 -650) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l22 (-1365 -980) (950 150))
+   rect(l22 (-1100 -840) (150 2010))
+   rect(l22 (950 -1320) (330 270))
+  )
+  net(23
+   rect(l7 (6830 955) (950 150))
+   rect(l7 (-1100 -840) (150 2010))
+   rect(l7 (950 -1320) (330 270))
+  )
+  net(24
+   polygon(l2 (6830 1725) (0 420) (105 0) (0 340) (420 0) (0 -760))
+   rect(l2 (-525 -1330) (445 420))
+   polygon(l9 (-210 -370) (0 1570) (170 0) (0 -480) (245 0) (0 -170) (-245 0) (0 -920))
+   rect(l21 (-170 1320) (170 170))
+   rect(l21 (-170 -1410) (170 170))
+   rect(l21 (-5 670) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (0 -150) (950 150))
+   rect(l22 (0 -1320) (150 2010))
+  )
+  net(25
+   rect(l7 (7480 1435) (950 150))
+   rect(l7 (-1280 -270) (330 270))
+   rect(l7 (950 -1320) (150 2010))
+  )
+  net(26 name('wl[0]')
+   rect(l9 (1005 2135) (170 500))
+   rect(l9 (2010 -500) (170 500))
+   rect(l9 (2010 -500) (170 500))
+   rect(l9 (2010 -500) (170 500))
+   polygon(l11 (-6755 -880) (0 320) (15 0) (0 290) (230 0) (0 -290) (15 0) (0 -320))
+   polygon(l11 (1920 0) (0 320) (15 0) (0 290) (230 0) (0 -290) (15 0) (0 -320))
+   polygon(l11 (1920 0) (0 320) (15 0) (0 290) (230 0) (0 -290) (15 0) (0 -320))
+   polygon(l11 (1920 0) (0 320) (15 0) (0 290) (230 0) (0 -290) (15 0) (0 -320))
+   rect(l13 (-7760 30) (2180 260))
+   rect(l13 (-2180 -260) (8720 260))
+   rect(l13 (-8720 -260) (2180 260))
+   rect(l13 (-2180 -260) (4360 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l13 (0 -260) (2180 260))
+   rect(l13 (-2180 -260) (4360 260))
+   rect(l13 (-4360 -260) (2180 260))
+   rect(l13 (0 -260) (2180 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l14 (-8720 -260) (4360 260))
+   rect(l14 (-4360 -260) (8720 260))
+   rect(l14 (-8720 -260) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l14 (0 -260) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l14 (0 -260) (4360 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l14 (0 -130) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l14 (0 -260) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l21 (-7715 340) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   polygon(l22 (-6760 -250) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+   polygon(l22 (1910 0) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+   polygon(l22 (1910 0) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+   polygon(l22 (1910 0) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+   rect(l23 (-6760 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-6700 -465) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+  )
+  net(27
+   polygon(l7 (955 2305) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+  )
+  net(28
+   polygon(l7 (7495 2305) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+  )
+  net(29
+   polygon(l7 (3135 2305) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+  )
+  net(30
+   polygon(l7 (5315 2305) (0 180) (-690 0) (0 150) (1650 0) (0 -150) (-690 0) (0 -180))
+  )
+  net(31 name('wl[1]')
+   rect(l9 (1005 2915) (170 500))
+   rect(l9 (2010 -500) (170 500))
+   rect(l9 (2010 -500) (170 500))
+   rect(l9 (2010 -500) (170 500))
+   polygon(l11 (-6740 -230) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   polygon(l11 (1950 0) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   polygon(l11 (1950 0) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   polygon(l11 (1950 0) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   rect(l13 (-7745 320) (2180 260))
+   rect(l13 (-2180 -260) (4360 260))
+   rect(l13 (-4360 -260) (8720 260))
+   rect(l13 (-8720 -260) (2180 260))
+   rect(l13 (0 -260) (2180 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l13 (0 -260) (2180 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l13 (-2180 -260) (4360 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l13 (-2180 -260) (2180 260))
+   rect(l14 (-8720 -260) (8720 260))
+   rect(l14 (-8720 -260) (4360 260))
+   rect(l14 (-4360 -260) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l14 (0 -260) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l14 (0 -260) (2180 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l14 (0 -130) (2180 260))
+   rect(l14 (-2180 -260) (4360 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l14 (-2180 -260) (2180 260))
+   rect(l21 (-7715 -770) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   polygon(l22 (-7450 -250) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+   polygon(l22 (530 0) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+   polygon(l22 (530 0) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+   polygon(l22 (530 0) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+   rect(l23 (-7450 330) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-6700 145) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+  )
+  net(32
+   polygon(l2 (395 3065) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+   polygon(l9 (-210 -1620) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-5 230) (170 170))
+   rect(l21 (-335 670) (170 170))
+   rect(l22 (-85 -1060) (330 270))
+   rect(l22 (0 -270) (950 150))
+   rect(l22 (0 -840) (150 2010))
+  )
+  net(33
+   rect(l7 (940 3965) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+   rect(l7 (950 -960) (150 2010))
+  )
+  net(34
+   polygon(l2 (1365 3065) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+   polygon(l9 (-405 -1620) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-335 590) (170 170))
+   rect(l21 (-5 310) (170 170))
+   rect(l22 (-1365 -580) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   rect(l22 (950 -960) (330 270))
+  )
+  net(35
+   polygon(l2 (2575 3065) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+   polygon(l9 (-210 -1620) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-5 230) (170 170))
+   rect(l21 (-335 670) (170 170))
+   rect(l22 (-85 -1060) (330 270))
+   rect(l22 (0 -270) (950 150))
+   rect(l22 (0 -840) (150 2010))
+  )
+  net(36
+   rect(l7 (3120 3965) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+   rect(l7 (950 -960) (150 2010))
+  )
+  net(37
+   polygon(l2 (4755 3065) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+   polygon(l9 (-210 -1620) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-5 230) (170 170))
+   rect(l21 (-335 670) (170 170))
+   rect(l22 (-85 -1060) (330 270))
+   rect(l22 (0 -270) (950 150))
+   rect(l22 (0 -840) (150 2010))
+  )
+  net(38
+   rect(l7 (5300 3965) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+   rect(l7 (950 -960) (150 2010))
+  )
+  net(39
+   polygon(l2 (5725 3065) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+   polygon(l9 (-405 -1620) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-335 590) (170 170))
+   rect(l21 (-5 310) (170 170))
+   rect(l22 (-1365 -580) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   rect(l22 (950 -960) (330 270))
+  )
+  net(40
+   polygon(l2 (6935 3065) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+   polygon(l9 (-210 -1620) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-5 230) (170 170))
+   rect(l21 (-335 670) (170 170))
+   rect(l22 (-85 -1060) (330 270))
+   rect(l22 (0 -270) (950 150))
+   rect(l22 (0 -840) (150 2010))
+  )
+  net(41
+   rect(l7 (7480 3965) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+   rect(l7 (950 -960) (150 2010))
+  )
+  net(42
+   polygon(l2 (7905 3065) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+   polygon(l9 (-405 -1620) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-335 590) (170 170))
+   rect(l21 (-5 310) (170 170))
+   rect(l22 (-1365 -580) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   rect(l22 (950 -960) (330 270))
+  )
+  net(43
+   polygon(l7 (265 2915) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(44
+   polygon(l7 (6805 2915) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(45
+   polygon(l7 (2445 2915) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(46
+   polygon(l7 (4625 2915) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(47
+   rect(l7 (290 4445) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+   rect(l7 (950 -960) (330 270))
+  )
+  net(48
+   rect(l7 (2470 4445) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+   rect(l7 (950 -960) (330 270))
+  )
+  net(49
+   polygon(l2 (3545 3065) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+   polygon(l9 (-405 -1620) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-335 840) (170 170))
+   rect(l21 (-5 -930) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l22 (-1365 -580) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   rect(l22 (950 -960) (330 270))
+  )
+  net(50
+   rect(l7 (4650 4445) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+   rect(l7 (950 -960) (330 270))
+  )
+  net(51
+   rect(l7 (6830 4445) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+   rect(l7 (950 -960) (330 270))
+  )
+  net(52 name(vss)
+   rect(l2 (-125 1725) (265 420))
+   rect(l2 (-265 270) (250 720))
+   rect(l2 (1915 -1410) (280 420))
+   rect(l2 (-265 270) (250 720))
+   rect(l2 (1915 -1410) (280 420))
+   rect(l2 (-265 270) (250 720))
+   rect(l2 (1915 -1410) (280 420))
+   rect(l2 (-265 270) (250 720))
+   rect(l2 (1915 -1410) (265 420))
+   rect(l2 (-250 270) (250 720))
+   rect(l2 (-8970 270) (265 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l6 (-8970 -1410) (250 720))
+   rect(l6 (1930 -720) (250 720))
+   rect(l6 (1930 -720) (250 720))
+   rect(l6 (1930 -720) (250 720))
+   rect(l6 (1930 -720) (250 720))
+   rect(l9 (-8930 -525) (170 1170))
+   rect(l9 (-170 -2010) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (-170 -330) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (2010 -2010) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (-170 -330) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (2010 -2010) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (-170 -330) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l9 (-170 -2010) (170 1170))
+   rect(l11 (-8935 -325) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l13 (-9010 -290) (9040 260))
+   rect(l13 (-9040 -260) (4680 260))
+   rect(l13 (-4680 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (4680 260))
+   rect(l13 (-4680 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l14 (-9040 -260) (9040 260))
+   rect(l14 (-9040 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (4680 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (4680 260))
+   rect(l14 (-4680 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l14 (2020 -130) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l21 (-8965 -1055) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-8890 670) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l23 (-8890 -1010) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l24 (-8880 -160) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+  )
+
+  # Devices and their connections
+  device(1 D$sky130_fd_pr__nfet_01v8__model
+   location(215 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 10)
+   terminal(D 12)
+   terminal(B 52)
+  )
+  device(2 D$sky130_fd_pr__nfet_01v8__model$1
+   location(605 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 12)
+   terminal(G 26)
+   terminal(D 2)
+   terminal(B 52)
+  )
+  device(3 D$sky130_fd_pr__nfet_01v8__model$2
+   location(605 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 2)
+   terminal(G 31)
+   terminal(D 32)
+   terminal(B 52)
+  )
+  device(4 D$sky130_fd_pr__nfet_01v8__model$3
+   location(215 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 32)
+   terminal(G 34)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(5 D$sky130_fd_pr__nfet_01v8__model$4
+   location(1965 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 10)
+   terminal(G 12)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(6 D$sky130_fd_pr__nfet_01v8__model$5
+   location(2395 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 15)
+   terminal(D 16)
+   terminal(B 52)
+  )
+  device(7 D$sky130_fd_pr__nfet_01v8__model$6
+   location(1575 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 10)
+   terminal(G 26)
+   terminal(D 3)
+   terminal(B 52)
+  )
+  device(8 D$sky130_fd_pr__nfet_01v8__model$1
+   location(2785 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 16)
+   terminal(G 26)
+   terminal(D 4)
+   terminal(B 52)
+  )
+  device(9 D$sky130_fd_pr__nfet_01v8__model$7
+   location(1575 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 3)
+   terminal(G 31)
+   terminal(D 34)
+   terminal(B 52)
+  )
+  device(10 D$sky130_fd_pr__nfet_01v8__model$2
+   location(2785 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 4)
+   terminal(G 31)
+   terminal(D 35)
+   terminal(B 52)
+  )
+  device(11 D$sky130_fd_pr__nfet_01v8__model$8
+   location(1965 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 34)
+   terminal(G 32)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(12 D$sky130_fd_pr__nfet_01v8__model$9
+   location(2395 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 35)
+   terminal(G 49)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(13 D$sky130_fd_pr__nfet_01v8__model$4
+   location(4145 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 15)
+   terminal(G 16)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(14 D$sky130_fd_pr__nfet_01v8__model$5
+   location(4575 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 18)
+   terminal(D 20)
+   terminal(B 52)
+  )
+  device(15 D$sky130_fd_pr__nfet_01v8__model$6
+   location(3755 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 15)
+   terminal(G 26)
+   terminal(D 5)
+   terminal(B 52)
+  )
+  device(16 D$sky130_fd_pr__nfet_01v8__model$1
+   location(4965 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 20)
+   terminal(G 26)
+   terminal(D 6)
+   terminal(B 52)
+  )
+  device(17 D$sky130_fd_pr__nfet_01v8__model$7
+   location(3755 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 5)
+   terminal(G 31)
+   terminal(D 49)
+   terminal(B 52)
+  )
+  device(18 D$sky130_fd_pr__nfet_01v8__model$2
+   location(4965 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 6)
+   terminal(G 31)
+   terminal(D 37)
+   terminal(B 52)
+  )
+  device(19 D$sky130_fd_pr__nfet_01v8__model$8
+   location(4145 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 49)
+   terminal(G 35)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(20 D$sky130_fd_pr__nfet_01v8__model$9
+   location(4575 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 37)
+   terminal(G 39)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(21 D$sky130_fd_pr__nfet_01v8__model$4
+   location(6325 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 18)
+   terminal(G 20)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(22 D$sky130_fd_pr__nfet_01v8__model$5
+   location(6755 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 22)
+   terminal(D 24)
+   terminal(B 52)
+  )
+  device(23 D$sky130_fd_pr__nfet_01v8__model$6
+   location(5935 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 18)
+   terminal(G 26)
+   terminal(D 7)
+   terminal(B 52)
+  )
+  device(24 D$sky130_fd_pr__nfet_01v8__model$1
+   location(7145 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 24)
+   terminal(G 26)
+   terminal(D 8)
+   terminal(B 52)
+  )
+  device(25 D$sky130_fd_pr__nfet_01v8__model$7
+   location(5935 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 7)
+   terminal(G 31)
+   terminal(D 39)
+   terminal(B 52)
+  )
+  device(26 D$sky130_fd_pr__nfet_01v8__model$2
+   location(7145 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 8)
+   terminal(G 31)
+   terminal(D 40)
+   terminal(B 52)
+  )
+  device(27 D$sky130_fd_pr__nfet_01v8__model$8
+   location(6325 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 39)
+   terminal(G 37)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(28 D$sky130_fd_pr__nfet_01v8__model$9
+   location(6755 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 40)
+   terminal(G 42)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(29 D$sky130_fd_pr__nfet_01v8__model$10
+   location(8505 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 22)
+   terminal(G 24)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(30 D$sky130_fd_pr__nfet_01v8__model$6
+   location(8115 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 22)
+   terminal(G 26)
+   terminal(D 9)
+   terminal(B 52)
+  )
+  device(31 D$sky130_fd_pr__nfet_01v8__model$7
+   location(8115 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 9)
+   terminal(G 31)
+   terminal(D 42)
+   terminal(B 52)
+  )
+  device(32 D$sky130_fd_pr__nfet_01v8__model$11
+   location(8505 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 42)
+   terminal(G 40)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(33 D$sky130_fd_pr__pfet_01v8__model
+   location(215 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 10)
+   terminal(D 12)
+   terminal(B 1)
+  )
+  device(34 D$sky130_fd_pr__pfet_01v8__model$1
+   location(1965 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 10)
+   terminal(G 12)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(35 D$sky130_fd_pr__pfet_01v8__model$2
+   location(2395 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 15)
+   terminal(D 16)
+   terminal(B 1)
+  )
+  device(36 D$sky130_fd_pr__pfet_01v8__model$1
+   location(4145 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 15)
+   terminal(G 16)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(37 D$sky130_fd_pr__pfet_01v8__model$2
+   location(4575 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 18)
+   terminal(D 20)
+   terminal(B 1)
+  )
+  device(38 D$sky130_fd_pr__pfet_01v8__model$1
+   location(6325 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 18)
+   terminal(G 20)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(39 D$sky130_fd_pr__pfet_01v8__model$2
+   location(6755 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 22)
+   terminal(D 24)
+   terminal(B 1)
+  )
+  device(40 D$sky130_fd_pr__pfet_01v8__model$3
+   location(8505 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 22)
+   terminal(G 24)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(41 D$sky130_fd_pr__pfet_01v8__model
+   location(215 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 34)
+   terminal(D 32)
+   terminal(B 1)
+  )
+  device(42 D$sky130_fd_pr__pfet_01v8__model$1
+   location(1965 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 34)
+   terminal(G 32)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(43 D$sky130_fd_pr__pfet_01v8__model$2
+   location(2395 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 49)
+   terminal(D 35)
+   terminal(B 1)
+  )
+  device(44 D$sky130_fd_pr__pfet_01v8__model$1
+   location(4145 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 49)
+   terminal(G 35)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(45 D$sky130_fd_pr__pfet_01v8__model$2
+   location(4575 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 39)
+   terminal(D 37)
+   terminal(B 1)
+  )
+  device(46 D$sky130_fd_pr__pfet_01v8__model$1
+   location(6325 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 39)
+   terminal(G 37)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(47 D$sky130_fd_pr__pfet_01v8__model$2
+   location(6755 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 42)
+   terminal(D 40)
+   terminal(B 1)
+  )
+  device(48 D$sky130_fd_pr__pfet_01v8__model$3
+   location(8505 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 42)
+   terminal(G 40)
+   terminal(D 1)
+   terminal(B 1)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(SKY130_FD_PR__PFET_01V8__MODEL MOS4)
+ class(SKY130_FD_PR__NFET_01V8__MODEL MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TARRAY_2X4
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+  net(9 name('BL[2]'))
+  net(10 name('BL_N[2]'))
+  net(11 name('BL[3]'))
+  net(12 name('BL_N[3]'))
+  net(13 name(INST0X0.INST0X0.INST0X0.BIT_N))
+  net(14 name(INST0X0.INST0X0.INST0X0.BIT))
+  net(15 name(INST0X0.INST0X0.INST1X0.BIT_N))
+  net(16 name(INST0X0.INST0X0.INST1X0.BIT))
+  net(17 name(INST0X0.INST0X1.INST0X0.BIT_N))
+  net(18 name(INST0X0.INST0X1.INST0X0.BIT))
+  net(19 name(INST0X0.INST0X1.INST1X0.BIT_N))
+  net(20 name(INST0X0.INST0X1.INST1X0.BIT))
+  net(21 name(INST0X1.INST0X0.INST0X0.BIT_N))
+  net(22 name(INST0X1.INST0X0.INST0X0.BIT))
+  net(23 name(INST0X1.INST0X0.INST1X0.BIT_N))
+  net(24 name(INST0X1.INST0X0.INST1X0.BIT))
+  net(25 name(INST0X1.INST0X1.INST0X0.BIT_N))
+  net(26 name(INST0X1.INST0X1.INST0X0.BIT))
+  net(27 name(INST0X1.INST0X1.INST1X0.BIT_N))
+  net(28 name(INST0X1.INST0X1.INST1X0.BIT))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+  pin(9 name('BL[2]'))
+  pin(10 name('BL_N[2]'))
+  pin(11 name('BL[3]'))
+  pin(12 name('BL_N[3]'))
+
+  # Devices and their connections
+  device(1 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 14)
+   terminal(G 13)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(2 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 14)
+   terminal(D 13)
+   terminal(B 2)
+  )
+  device(3 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 14)
+   terminal(G 13)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(4 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 14)
+   terminal(D 13)
+   terminal(B 1)
+  )
+  device(5 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 14)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(6 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 13)
+   terminal(G 3)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(7 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 16)
+   terminal(G 15)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(8 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 16)
+   terminal(D 15)
+   terminal(B 2)
+  )
+  device(9 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 16)
+   terminal(G 15)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(10 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 16)
+   terminal(D 15)
+   terminal(B 1)
+  )
+  device(11 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 16)
+   terminal(G 4)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(12 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 15)
+   terminal(G 4)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(13 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 18)
+   terminal(G 17)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(14 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 18)
+   terminal(D 17)
+   terminal(B 2)
+  )
+  device(15 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 18)
+   terminal(G 17)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(16 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 18)
+   terminal(D 17)
+   terminal(B 1)
+  )
+  device(17 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 18)
+   terminal(G 3)
+   terminal(D 7)
+   terminal(B 1)
+  )
+  device(18 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 17)
+   terminal(G 3)
+   terminal(D 8)
+   terminal(B 1)
+  )
+  device(19 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 20)
+   terminal(G 19)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(20 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 20)
+   terminal(D 19)
+   terminal(B 2)
+  )
+  device(21 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 20)
+   terminal(G 19)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(22 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 20)
+   terminal(D 19)
+   terminal(B 1)
+  )
+  device(23 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 20)
+   terminal(G 4)
+   terminal(D 7)
+   terminal(B 1)
+  )
+  device(24 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 19)
+   terminal(G 4)
+   terminal(D 8)
+   terminal(B 1)
+  )
+  device(25 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 22)
+   terminal(G 21)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(26 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 22)
+   terminal(D 21)
+   terminal(B 2)
+  )
+  device(27 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 22)
+   terminal(G 21)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(28 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 22)
+   terminal(D 21)
+   terminal(B 1)
+  )
+  device(29 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 22)
+   terminal(G 3)
+   terminal(D 9)
+   terminal(B 1)
+  )
+  device(30 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 21)
+   terminal(G 3)
+   terminal(D 10)
+   terminal(B 1)
+  )
+  device(31 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 24)
+   terminal(G 23)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(32 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 24)
+   terminal(D 23)
+   terminal(B 2)
+  )
+  device(33 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 24)
+   terminal(G 23)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(34 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 24)
+   terminal(D 23)
+   terminal(B 1)
+  )
+  device(35 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 24)
+   terminal(G 4)
+   terminal(D 9)
+   terminal(B 1)
+  )
+  device(36 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 23)
+   terminal(G 4)
+   terminal(D 10)
+   terminal(B 1)
+  )
+  device(37 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 26)
+   terminal(G 25)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(38 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 26)
+   terminal(D 25)
+   terminal(B 2)
+  )
+  device(39 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 26)
+   terminal(G 25)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(40 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 26)
+   terminal(D 25)
+   terminal(B 1)
+  )
+  device(41 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 26)
+   terminal(G 3)
+   terminal(D 11)
+   terminal(B 1)
+  )
+  device(42 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 25)
+   terminal(G 3)
+   terminal(D 12)
+   terminal(B 1)
+  )
+  device(43 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 28)
+   terminal(G 27)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(44 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 28)
+   terminal(D 27)
+   terminal(B 2)
+  )
+  device(45 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 28)
+   terminal(G 27)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(46 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 28)
+   terminal(D 27)
+   terminal(B 1)
+  )
+  device(47 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 28)
+   terminal(G 4)
+   terminal(D 11)
+   terminal(B 1)
+  )
+  device(48 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 27)
+   terminal(G 4)
+   terminal(D 12)
+   terminal(B 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(SP6TArray_2X4 SP6TARRAY_2X4 match
+  xref(
+   net(10 14 warning)
+   net(12 13 warning)
+   net(34 16 match)
+   net(32 15 match)
+   net(16 18 match)
+   net(15 17 match)
+   net(35 20 match)
+   net(49 19 match)
+   net(20 22 match)
+   net(18 21 match)
+   net(37 24 match)
+   net(39 23 match)
+   net(24 26 match)
+   net(22 25 match)
+   net(40 28 match)
+   net(42 27 match)
+   net(2 6 match)
+   net(4 7 match)
+   net(6 9 match)
+   net(8 11 match)
+   net(3 5 match)
+   net(5 8 match)
+   net(7 10 match)
+   net(9 12 match)
+   net(1 2 match)
+   net(52 1 match)
+   net(26 3 match)
+   net(31 4 match)
+   pin(() 4 match)
+   pin(() 6 match)
+   pin(() 8 match)
+   pin(() 10 match)
+   pin(() 5 match)
+   pin(() 7 match)
+   pin(() 9 match)
+   pin(() 11 match)
+   pin(() 1 match)
+   pin(() 0 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   device(5 3 match)
+   device(1 4 match)
+   device(7 5 match)
+   device(2 6 match)
+   device(11 9 match)
+   device(4 10 match)
+   device(9 11 match)
+   device(3 12 match)
+   device(6 15 match)
+   device(13 16 match)
+   device(8 17 match)
+   device(15 18 match)
+   device(12 21 match)
+   device(19 22 match)
+   device(10 23 match)
+   device(17 24 match)
+   device(14 27 match)
+   device(21 28 match)
+   device(16 29 match)
+   device(23 30 match)
+   device(20 33 match)
+   device(27 34 match)
+   device(18 35 match)
+   device(25 36 match)
+   device(22 39 match)
+   device(29 40 match)
+   device(24 41 match)
+   device(30 42 match)
+   device(28 45 match)
+   device(32 46 match)
+   device(26 47 match)
+   device(31 48 match)
+   device(34 1 match)
+   device(33 2 match)
+   device(42 7 match)
+   device(41 8 match)
+   device(35 13 match)
+   device(36 14 match)
+   device(43 19 match)
+   device(44 20 match)
+   device(37 25 match)
+   device(38 26 match)
+   device(45 31 match)
+   device(46 32 match)
+   device(39 37 match)
+   device(40 38 match)
+   device(47 43 match)
+   device(48 44 match)
+  )
+ )
+)
diff --git a/testdata/lvs/test_22b.lvsdb.2 b/testdata/lvs/test_22b.lvsdb.2
new file mode 100644
index 000000000..03b56d2fd
--- /dev/null
+++ b/testdata/lvs/test_22b.lvsdb.2
@@ -0,0 +1,2590 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(SP6TArray_2X4)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l1)
+ layer(l2)
+ layer(l3)
+ layer(l4)
+ layer(l5 '64/20')
+ layer(l6)
+ layer(l7 '66/20')
+ layer(l8)
+ layer(l9 '67/20')
+ layer(l10)
+ layer(l11 '68/20')
+ layer(l12 '68/16')
+ layer(l13 '69/20')
+ layer(l14 '69/16')
+ layer(l15)
+ layer(l16)
+ layer(l17)
+ layer(l18)
+ layer(l19)
+ layer(l20)
+ layer(l21 '66/44')
+ layer(l22 '66/20')
+ layer(l23 '67/44')
+ layer(l24 '68/44')
+ layer(l25)
+ layer(l26)
+ layer(l27)
+
+ # Mask layer connectivity
+ connect(l1 l1)
+ connect(l2 l2 l3 l4 l6 l21)
+ connect(l3 l2 l3)
+ connect(l4 l2 l4 l5)
+ connect(l5 l4 l5)
+ connect(l6 l2 l6)
+ connect(l7 l7 l8)
+ connect(l8 l7 l8)
+ connect(l9 l9 l10 l21 l23)
+ connect(l10 l9 l10)
+ connect(l11 l11 l12 l23 l24)
+ connect(l12 l11 l12)
+ connect(l13 l13 l14 l24 l25)
+ connect(l14 l13 l14)
+ connect(l15 l15 l16 l25 l26)
+ connect(l16 l15 l16)
+ connect(l17 l17 l18 l26 l27)
+ connect(l18 l17 l18)
+ connect(l19 l19 l20 l27)
+ connect(l20 l19 l20)
+ connect(l21 l2 l9 l21 l22)
+ connect(l22 l21 l22)
+ connect(l23 l9 l11 l23)
+ connect(l24 l11 l13 l24)
+ connect(l25 l13 l15 l25)
+ connect(l26 l15 l17 l26)
+ connect(l27 l17 l19 l27)
+
+ # Global nets and connectivity
+ global(l1 vss)
+ global(l6 vss)
+
+ # Device class section
+ class(active_res RES)
+ class(poly_res RES)
+ class(sky130_fd_pr__diode_pw2nd_05v5 DIODE)
+ class(sky130_fd_pr__diode_pd2nw_05v5 DIODE)
+ class(sky130_fd_pr__nfet_01v8__model MOS4)
+ class(sky130_fd_pr__nfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__nfet_g5v0d10v5__model MOS4)
+ class(sky130_fd_pr__pfet_01v8__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_hvt__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__pfet_g5v0d10v5__model MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$sky130_fd_pr__nfet_01v8__model sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   polygon(l2 (75 -210) (0 420) (105 0) (0 340) (420 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-315 -835) (0 420) (105 0) (0 340) (420 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   rect(l2 (-210 75) (420 280))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$2 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -355) (420 280))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$4 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -210) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (280 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$5 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-355 -210) (280 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   polygon(l2 (75 -210) (0 420) (105 0) (0 340) (420 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$6 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-210 -835) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   rect(l2 (-210 75) (420 280))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$7 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -355) (420 280))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$8 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (280 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$9 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-355 -210) (280 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$10 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -210) (0 760) (420 0) (0 -340) (105 0) (0 -420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$11 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$1 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (280 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$2 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-355 -210) (280 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$3 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TArray_2X4
+
+  # Circuit boundary
+  rect((-385 -305) (9490 6160))
+
+  # Nets with their geometries
+  net(1 name(vdd)
+   rect(l2 (-205 -125) (9130 250))
+   rect(l2 (-9050 270) (265 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l2 (-9050 4610) (9130 250))
+   rect(l2 (-9050 -940) (265 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (280 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l4 (-9050 -5280) (9130 250))
+   rect(l4 (-9130 5300) (9130 250))
+   rect(l5 (-7130 -5980) (2950 1300))
+   rect(l5 (-5130 -1300) (2950 1300))
+   rect(l5 (1410 -1300) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l5 (-9490 3560) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l5 (-770 -1300) (2950 1300))
+   rect(l9 (-9270 -5940) (2510 170))
+   rect(l9 (-330 -170) (2510 170))
+   rect(l9 (-330 -170) (2510 170))
+   rect(l9 (-330 -170) (2510 170))
+   rect(l9 (-8970 0) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l9 (-8970 4695) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (1930 0) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (1930 0) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (1930 0) (2510 170))
+   rect(l9 (-2430 -855) (170 685))
+   rect(l9 (-170 -685) (170 685))
+   rect(l9 (2010 -685) (170 685))
+   rect(l11 (-8935 -5625) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-8980 5230) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l13 (-9010 -5840) (4680 260))
+   rect(l13 (-4680 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (9040 260))
+   rect(l13 (-6860 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (4680 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-9040 5290) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (9040 260))
+   rect(l13 (-9040 -260) (4680 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (4680 260))
+   rect(l13 (-4680 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l14 (-9040 -5810) (4680 260))
+   rect(l14 (-4680 -260) (2500 260))
+   rect(l14 (-2500 -260) (9040 260))
+   rect(l14 (-9040 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (4680 260))
+   rect(l14 (-4680 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l14 (-4520 5420) (4680 260))
+   rect(l14 (-4680 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (9040 260))
+   rect(l14 (-6860 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (4680 260))
+   rect(l14 (-4680 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l21 (-4445 -5635) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-8890 435) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-8890 4775) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 435) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -775) (170 170))
+   rect(l21 (-170 435) (170 170))
+   rect(l23 (-8890 -5720) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-8890 5380) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-8880 -5710) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-8870 5400) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+  )
+  net(2 name('bl[0]')
+   rect(l2 (395 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(3 name('bl_n[0]')
+   rect(l2 (1365 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -290) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(4 name('bl[1]')
+   rect(l2 (2575 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(5 name('bl_n[1]')
+   rect(l2 (3545 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -290) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -290) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(6 name('bl[2]')
+   rect(l2 (4755 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(7 name('bl_n[2]')
+   rect(l2 (5725 2635) (420 280))
+   polygon(l9 (-295 -305) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   polygon(l9 (-170 0) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l11 (-140 -2610) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-145 -85) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+  )
+  net(8 name('bl[3]')
+   rect(l2 (6935 2635) (420 280))
+   polygon(l9 (-295 -305) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   polygon(l9 (-170 0) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l11 (-260 -2610) (230 2920))
+   rect(l11 (-230 -2920) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -5550) (230 5550))
+   rect(l11 (-230 -2920) (230 2920))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -5550) (230 2920))
+   rect(l12 (-230 -2920) (230 5550))
+   rect(l12 (-230 -5550) (230 5550))
+   rect(l12 (-230 -2920) (230 2920))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l21 (-25 -85) (170 170))
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+   rect(l9 (-170 -330) (170 1170))
+   rect(l9 (-170 -1170) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l9 (-170 -2010) (170 1170))
+   rect(l11 (-8935 -325) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l11 (-260 -320) (260 320))
+   rect(l13 (-9010 -290) (9040 260))
+   rect(l13 (-9040 -260) (4680 260))
+   rect(l13 (-4680 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (4680 260))
+   rect(l13 (-4680 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-320 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l13 (-2500 -260) (2500 260))
+   rect(l14 (-9040 -260) (9040 260))
+   rect(l14 (-9040 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (4680 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-320 -260) (2500 260))
+   rect(l14 (-2500 -260) (4680 260))
+   rect(l14 (-4680 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l14 (2020 -130) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l14 (-2500 -260) (2500 260))
+   rect(l21 (-8965 -1055) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -1010) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (-8890 670) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -170) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l23 (-8890 -1010) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l23 (-170 -170) (170 170))
+   rect(l24 (-8880 -160) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l24 (-150 -150) (150 150))
+  )
+
+  # Devices and their connections
+  device(1 D$sky130_fd_pr__nfet_01v8__model
+   location(215 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 10)
+   terminal(D 12)
+   terminal(B 52)
+  )
+  device(2 D$sky130_fd_pr__nfet_01v8__model$1
+   location(605 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 12)
+   terminal(G 26)
+   terminal(D 2)
+   terminal(B 52)
+  )
+  device(3 D$sky130_fd_pr__nfet_01v8__model$2
+   location(605 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 2)
+   terminal(G 31)
+   terminal(D 32)
+   terminal(B 52)
+  )
+  device(4 D$sky130_fd_pr__nfet_01v8__model$3
+   location(215 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 32)
+   terminal(G 34)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(5 D$sky130_fd_pr__nfet_01v8__model$4
+   location(1965 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 10)
+   terminal(G 12)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(6 D$sky130_fd_pr__nfet_01v8__model$5
+   location(2395 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 15)
+   terminal(D 16)
+   terminal(B 52)
+  )
+  device(7 D$sky130_fd_pr__nfet_01v8__model$6
+   location(1575 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 10)
+   terminal(G 26)
+   terminal(D 3)
+   terminal(B 52)
+  )
+  device(8 D$sky130_fd_pr__nfet_01v8__model$1
+   location(2785 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 16)
+   terminal(G 26)
+   terminal(D 4)
+   terminal(B 52)
+  )
+  device(9 D$sky130_fd_pr__nfet_01v8__model$7
+   location(1575 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 3)
+   terminal(G 31)
+   terminal(D 34)
+   terminal(B 52)
+  )
+  device(10 D$sky130_fd_pr__nfet_01v8__model$2
+   location(2785 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 4)
+   terminal(G 31)
+   terminal(D 35)
+   terminal(B 52)
+  )
+  device(11 D$sky130_fd_pr__nfet_01v8__model$8
+   location(1965 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 34)
+   terminal(G 32)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(12 D$sky130_fd_pr__nfet_01v8__model$9
+   location(2395 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 35)
+   terminal(G 49)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(13 D$sky130_fd_pr__nfet_01v8__model$4
+   location(4145 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 15)
+   terminal(G 16)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(14 D$sky130_fd_pr__nfet_01v8__model$5
+   location(4575 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 18)
+   terminal(D 20)
+   terminal(B 52)
+  )
+  device(15 D$sky130_fd_pr__nfet_01v8__model$6
+   location(3755 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 15)
+   terminal(G 26)
+   terminal(D 5)
+   terminal(B 52)
+  )
+  device(16 D$sky130_fd_pr__nfet_01v8__model$1
+   location(4965 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 20)
+   terminal(G 26)
+   terminal(D 6)
+   terminal(B 52)
+  )
+  device(17 D$sky130_fd_pr__nfet_01v8__model$7
+   location(3755 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 5)
+   terminal(G 31)
+   terminal(D 49)
+   terminal(B 52)
+  )
+  device(18 D$sky130_fd_pr__nfet_01v8__model$2
+   location(4965 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 6)
+   terminal(G 31)
+   terminal(D 37)
+   terminal(B 52)
+  )
+  device(19 D$sky130_fd_pr__nfet_01v8__model$8
+   location(4145 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 49)
+   terminal(G 35)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(20 D$sky130_fd_pr__nfet_01v8__model$9
+   location(4575 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 37)
+   terminal(G 39)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(21 D$sky130_fd_pr__nfet_01v8__model$4
+   location(6325 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 18)
+   terminal(G 20)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(22 D$sky130_fd_pr__nfet_01v8__model$5
+   location(6755 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 52)
+   terminal(G 22)
+   terminal(D 24)
+   terminal(B 52)
+  )
+  device(23 D$sky130_fd_pr__nfet_01v8__model$6
+   location(5935 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 18)
+   terminal(G 26)
+   terminal(D 7)
+   terminal(B 52)
+  )
+  device(24 D$sky130_fd_pr__nfet_01v8__model$1
+   location(7145 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 24)
+   terminal(G 26)
+   terminal(D 8)
+   terminal(B 52)
+  )
+  device(25 D$sky130_fd_pr__nfet_01v8__model$7
+   location(5935 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 7)
+   terminal(G 31)
+   terminal(D 39)
+   terminal(B 52)
+  )
+  device(26 D$sky130_fd_pr__nfet_01v8__model$2
+   location(7145 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 8)
+   terminal(G 31)
+   terminal(D 40)
+   terminal(B 52)
+  )
+  device(27 D$sky130_fd_pr__nfet_01v8__model$8
+   location(6325 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 39)
+   terminal(G 37)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(28 D$sky130_fd_pr__nfet_01v8__model$9
+   location(6755 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 40)
+   terminal(G 42)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(29 D$sky130_fd_pr__nfet_01v8__model$10
+   location(8505 1935)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 22)
+   terminal(G 24)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(30 D$sky130_fd_pr__nfet_01v8__model$6
+   location(8115 2560)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.0588)
+   param(PS 1.285)
+   param(PD 0.7)
+   terminal(S 22)
+   terminal(G 26)
+   terminal(D 9)
+   terminal(B 52)
+  )
+  device(31 D$sky130_fd_pr__nfet_01v8__model$7
+   location(8115 2990)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.18165)
+   param(PS 0.7)
+   param(PD 1.285)
+   terminal(S 9)
+   terminal(G 31)
+   terminal(D 42)
+   terminal(B 52)
+  )
+  device(32 D$sky130_fd_pr__nfet_01v8__model$11
+   location(8505 3615)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 42)
+   terminal(G 40)
+   terminal(D 52)
+   terminal(B 52)
+  )
+  device(33 D$sky130_fd_pr__pfet_01v8__model
+   location(215 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 10)
+   terminal(D 12)
+   terminal(B 1)
+  )
+  device(34 D$sky130_fd_pr__pfet_01v8__model$1
+   location(1965 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 10)
+   terminal(G 12)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(35 D$sky130_fd_pr__pfet_01v8__model$2
+   location(2395 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 15)
+   terminal(D 16)
+   terminal(B 1)
+  )
+  device(36 D$sky130_fd_pr__pfet_01v8__model$1
+   location(4145 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 15)
+   terminal(G 16)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(37 D$sky130_fd_pr__pfet_01v8__model$2
+   location(4575 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 18)
+   terminal(D 20)
+   terminal(B 1)
+  )
+  device(38 D$sky130_fd_pr__pfet_01v8__model$1
+   location(6325 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 18)
+   terminal(G 20)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(39 D$sky130_fd_pr__pfet_01v8__model$2
+   location(6755 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 22)
+   terminal(D 24)
+   terminal(B 1)
+  )
+  device(40 D$sky130_fd_pr__pfet_01v8__model$3
+   location(8505 605)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 22)
+   terminal(G 24)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(41 D$sky130_fd_pr__pfet_01v8__model
+   location(215 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 34)
+   terminal(D 32)
+   terminal(B 1)
+  )
+  device(42 D$sky130_fd_pr__pfet_01v8__model$1
+   location(1965 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 34)
+   terminal(G 32)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(43 D$sky130_fd_pr__pfet_01v8__model$2
+   location(2395 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 49)
+   terminal(D 35)
+   terminal(B 1)
+  )
+  device(44 D$sky130_fd_pr__pfet_01v8__model$1
+   location(4145 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 49)
+   terminal(G 35)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(45 D$sky130_fd_pr__pfet_01v8__model$2
+   location(4575 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 39)
+   terminal(D 37)
+   terminal(B 1)
+  )
+  device(46 D$sky130_fd_pr__pfet_01v8__model$1
+   location(6325 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.0588)
+   param(PS 1.73)
+   param(PD 0.7)
+   terminal(S 39)
+   terminal(G 37)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(47 D$sky130_fd_pr__pfet_01v8__model$2
+   location(6755 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.0588)
+   param(AD 0.1869)
+   param(PS 0.7)
+   param(PD 1.73)
+   terminal(S 1)
+   terminal(G 42)
+   terminal(D 40)
+   terminal(B 1)
+  )
+  device(48 D$sky130_fd_pr__pfet_01v8__model$3
+   location(8505 4945)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 42)
+   terminal(G 40)
+   terminal(D 1)
+   terminal(B 1)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(SKY130_FD_PR__PFET_01V8__MODEL MOS4)
+ class(SKY130_FD_PR__NFET_01V8__MODEL MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TARRAY_2X4
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+  net(9 name('BL[2]'))
+  net(10 name('BL_N[2]'))
+  net(11 name('BL[3]'))
+  net(12 name('BL_N[3]'))
+  net(13 name(INST0X0.INST0X0.INST0X0.BIT_N))
+  net(14 name(INST0X0.INST0X0.INST0X0.BIT))
+  net(15 name(INST0X0.INST0X0.INST1X0.BIT_N))
+  net(16 name(INST0X0.INST0X0.INST1X0.BIT))
+  net(17 name(INST0X0.INST0X1.INST0X0.BIT_N))
+  net(18 name(INST0X0.INST0X1.INST0X0.BIT))
+  net(19 name(INST0X0.INST0X1.INST1X0.BIT_N))
+  net(20 name(INST0X0.INST0X1.INST1X0.BIT))
+  net(21 name(INST0X1.INST0X0.INST0X0.BIT_N))
+  net(22 name(INST0X1.INST0X0.INST0X0.BIT))
+  net(23 name(INST0X1.INST0X0.INST1X0.BIT_N))
+  net(24 name(INST0X1.INST0X0.INST1X0.BIT))
+  net(25 name(INST0X1.INST0X1.INST0X0.BIT_N))
+  net(26 name(INST0X1.INST0X1.INST0X0.BIT))
+  net(27 name(INST0X1.INST0X1.INST1X0.BIT_N))
+  net(28 name(INST0X1.INST0X1.INST1X0.BIT))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+  pin(9 name('BL[2]'))
+  pin(10 name('BL_N[2]'))
+  pin(11 name('BL[3]'))
+  pin(12 name('BL_N[3]'))
+
+  # Devices and their connections
+  device(1 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 14)
+   terminal(G 13)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(2 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 14)
+   terminal(D 13)
+   terminal(B 2)
+  )
+  device(3 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 14)
+   terminal(G 13)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(4 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 14)
+   terminal(D 13)
+   terminal(B 1)
+  )
+  device(5 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 14)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(6 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 13)
+   terminal(G 3)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(7 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 16)
+   terminal(G 15)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(8 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 16)
+   terminal(D 15)
+   terminal(B 2)
+  )
+  device(9 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 16)
+   terminal(G 15)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(10 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 16)
+   terminal(D 15)
+   terminal(B 1)
+  )
+  device(11 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 16)
+   terminal(G 4)
+   terminal(D 5)
+   terminal(B 1)
+  )
+  device(12 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X0.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 15)
+   terminal(G 4)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(13 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 18)
+   terminal(G 17)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(14 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 18)
+   terminal(D 17)
+   terminal(B 2)
+  )
+  device(15 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 18)
+   terminal(G 17)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(16 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 18)
+   terminal(D 17)
+   terminal(B 1)
+  )
+  device(17 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 18)
+   terminal(G 3)
+   terminal(D 7)
+   terminal(B 1)
+  )
+  device(18 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 17)
+   terminal(G 3)
+   terminal(D 8)
+   terminal(B 1)
+  )
+  device(19 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 20)
+   terminal(G 19)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(20 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 20)
+   terminal(D 19)
+   terminal(B 2)
+  )
+  device(21 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 20)
+   terminal(G 19)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(22 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 20)
+   terminal(D 19)
+   terminal(B 1)
+  )
+  device(23 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 20)
+   terminal(G 4)
+   terminal(D 7)
+   terminal(B 1)
+  )
+  device(24 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X0.INST0X1.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 19)
+   terminal(G 4)
+   terminal(D 8)
+   terminal(B 1)
+  )
+  device(25 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 22)
+   terminal(G 21)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(26 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 22)
+   terminal(D 21)
+   terminal(B 2)
+  )
+  device(27 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 22)
+   terminal(G 21)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(28 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 22)
+   terminal(D 21)
+   terminal(B 1)
+  )
+  device(29 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 22)
+   terminal(G 3)
+   terminal(D 9)
+   terminal(B 1)
+  )
+  device(30 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 21)
+   terminal(G 3)
+   terminal(D 10)
+   terminal(B 1)
+  )
+  device(31 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 24)
+   terminal(G 23)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(32 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 24)
+   terminal(D 23)
+   terminal(B 2)
+  )
+  device(33 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 24)
+   terminal(G 23)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(34 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 24)
+   terminal(D 23)
+   terminal(B 1)
+  )
+  device(35 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 24)
+   terminal(G 4)
+   terminal(D 9)
+   terminal(B 1)
+  )
+  device(36 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X0.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 23)
+   terminal(G 4)
+   terminal(D 10)
+   terminal(B 1)
+  )
+  device(37 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 26)
+   terminal(G 25)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(38 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 26)
+   terminal(D 25)
+   terminal(B 2)
+  )
+  device(39 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 26)
+   terminal(G 25)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(40 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 26)
+   terminal(D 25)
+   terminal(B 1)
+  )
+  device(41 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 26)
+   terminal(G 3)
+   terminal(D 11)
+   terminal(B 1)
+  )
+  device(42 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST0X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 25)
+   terminal(G 3)
+   terminal(D 12)
+   terminal(B 1)
+  )
+  device(43 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 28)
+   terminal(G 27)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(44 SKY130_FD_PR__PFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 28)
+   terminal(D 27)
+   terminal(B 2)
+  )
+  device(45 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 28)
+   terminal(G 27)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(46 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 28)
+   terminal(D 27)
+   terminal(B 1)
+  )
+  device(47 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 28)
+   terminal(G 4)
+   terminal(D 11)
+   terminal(B 1)
+  )
+  device(48 SKY130_FD_PR__NFET_01V8__MODEL
+   name(INST0X1.INST0X1.INST1X0.PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 27)
+   terminal(G 4)
+   terminal(D 12)
+   terminal(B 1)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(SP6TArray_2X4 SP6TARRAY_2X4 match
+  xref(
+   net(12 14 match)
+   net(10 13 match)
+   net(32 16 match)
+   net(34 15 match)
+   net(16 18 match)
+   net(15 17 match)
+   net(35 20 match)
+   net(49 19 match)
+   net(20 22 match)
+   net(18 21 match)
+   net(37 24 match)
+   net(39 23 match)
+   net(24 26 match)
+   net(22 25 match)
+   net(40 28 match)
+   net(42 27 match)
+   net(2 5 match)
+   net(4 7 match)
+   net(6 9 match)
+   net(8 11 match)
+   net(3 6 match)
+   net(5 8 match)
+   net(7 10 match)
+   net(9 12 match)
+   net(1 2 match)
+   net(52 1 match)
+   net(26 3 match)
+   net(31 4 match)
+   pin(() 4 match)
+   pin(() 6 match)
+   pin(() 8 match)
+   pin(() 10 match)
+   pin(() 5 match)
+   pin(() 7 match)
+   pin(() 9 match)
+   pin(() 11 match)
+   pin(() 1 match)
+   pin(() 0 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   device(1 3 match)
+   device(5 4 match)
+   device(2 5 match)
+   device(7 6 match)
+   device(4 9 match)
+   device(11 10 match)
+   device(3 11 match)
+   device(9 12 match)
+   device(6 15 match)
+   device(13 16 match)
+   device(8 17 match)
+   device(15 18 match)
+   device(12 21 match)
+   device(19 22 match)
+   device(10 23 match)
+   device(17 24 match)
+   device(14 27 match)
+   device(21 28 match)
+   device(16 29 match)
+   device(23 30 match)
+   device(20 33 match)
+   device(27 34 match)
+   device(18 35 match)
+   device(25 36 match)
+   device(22 39 match)
+   device(29 40 match)
+   device(24 41 match)
+   device(30 42 match)
+   device(28 45 match)
+   device(32 46 match)
+   device(26 47 match)
+   device(31 48 match)
+   device(33 1 match)
+   device(34 2 match)
+   device(41 7 match)
+   device(42 8 match)
+   device(35 13 match)
+   device(36 14 match)
+   device(43 19 match)
+   device(44 20 match)
+   device(37 25 match)
+   device(38 26 match)
+   device(45 31 match)
+   device(46 32 match)
+   device(39 37 match)
+   device(40 38 match)
+   device(47 43 match)
+   device(48 44 match)
+  )
+ )
+)
diff --git a/testdata/lvs/test_22c.lvsdb.2 b/testdata/lvs/test_22c.lvsdb.2
new file mode 100644
index 000000000..4e459b3fe
--- /dev/null
+++ b/testdata/lvs/test_22c.lvsdb.2
@@ -0,0 +1,952 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(SP6TArray_2X4)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l5 '64/20')
+ layer(l3)
+ layer(l8)
+ layer(l7 '66/20')
+ layer(l10)
+ layer(l9 '67/20')
+ layer(l12 '68/16')
+ layer(l11 '68/20')
+ layer(l14 '69/16')
+ layer(l13 '69/20')
+ layer(l16)
+ layer(l15)
+ layer(l18)
+ layer(l17)
+ layer(l20)
+ layer(l19)
+ layer(l21 '66/44')
+ layer(l23 '67/44')
+ layer(l24 '68/44')
+ layer(l25)
+ layer(l26)
+ layer(l27)
+ layer(l22)
+ layer(l2)
+ layer(l4)
+ layer(l6)
+ layer(l1)
+
+ # Mask layer connectivity
+ connect(l5 l5 l4)
+ connect(l3 l3 l2)
+ connect(l8 l8 l7)
+ connect(l7 l8 l7)
+ connect(l10 l10 l9)
+ connect(l9 l10 l9 l21 l23)
+ connect(l12 l12 l11)
+ connect(l11 l12 l11 l23 l24)
+ connect(l14 l14 l13)
+ connect(l13 l14 l13 l24 l25)
+ connect(l16 l16 l15)
+ connect(l15 l16 l15 l25 l26)
+ connect(l18 l18 l17)
+ connect(l17 l18 l17 l26 l27)
+ connect(l20 l20 l19)
+ connect(l19 l20 l19 l27)
+ connect(l21 l9 l21 l22 l2)
+ connect(l23 l9 l11 l23)
+ connect(l24 l11 l13 l24)
+ connect(l25 l13 l15 l25)
+ connect(l26 l15 l17 l26)
+ connect(l27 l17 l19 l27)
+ connect(l22 l21 l22)
+ connect(l2 l3 l21 l2 l4 l6)
+ connect(l4 l5 l2 l4)
+ connect(l6 l2 l6)
+ connect(l1 l1)
+
+ # Global nets and connectivity
+ global(l6 vss)
+ global(l1 vss)
+
+ # Device class section
+ class(active_res RES)
+ class(poly_res RES)
+ class(sky130_fd_pr__diode_pw2nd_05v5 DIODE)
+ class(sky130_fd_pr__diode_pd2nw_05v5 DIODE)
+ class(sky130_fd_pr__nfet_01v8__model MOS4)
+ class(sky130_fd_pr__nfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__nfet_g5v0d10v5__model MOS4)
+ class(sky130_fd_pr__pfet_01v8__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_hvt__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__pfet_g5v0d10v5__model MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$sky130_fd_pr__nfet_01v8__model sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$2 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$1 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCell
+
+  # Circuit boundary
+  rect((-385 -485) (2950 3565))
+
+  # Nets with their geometries
+  net(1
+   rect(l7 (1890 500) (150 2010))
+   rect(l7 (-1100 -1320) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+  )
+  net(2
+   rect(l7 (1240 1550) (330 270))
+   rect(l7 (-1280 -150) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+  )
+  net(3
+   polygon(l9 (525 760) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-5 -1010) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (950 -960) (150 2010))
+   rect(l22 (-1100 -1320) (950 150))
+   polygon(l2 (-1495 -1050) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+  )
+  net(4
+   polygon(l9 (1485 760) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-335 -650) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (-1280 -150) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   polygon(l2 (1075 -2220) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+  )
+  net(5 name(vdd)
+   rect(l5 (-385 1780) (2950 1300))
+   rect(l9 (-2650 -1075) (170 685))
+   rect(l9 (-250 0) (2510 170))
+   rect(l9 (-250 -855) (170 685))
+   rect(l11 (-2395 -75) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l23 (-2350 435) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-2460 -200) (2590 250))
+   rect(l2 (-2510 -940) (265 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l4 (-2510 270) (2590 250))
+  )
+  net(6 name(wl)
+   rect(l9 (1005 140) (170 500))
+   polygon(l11 (-200 -230) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   rect(l14 (-1205 320) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+   rect(l21 (-1175 -770) (170 170))
+   rect(l23 (-170 80) (170 170))
+   rect(l24 (-160 145) (150 150))
+   polygon(l22 (-900 -795) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(7 name(bl)
+   polygon(l9 (520 -165) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l12 (-260 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-140 -2860) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l2 (-235 -210) (420 265))
+  )
+  net(8 name(bl_n)
+   polygon(l9 (1490 -165) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l12 (-140 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-260 -2860) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l2 (-355 -210) (420 265))
+  )
+  net(9
+   polygon(l7 (265 140) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(10 name(vss)
+   rect(l9 (-85 -165) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l11 (-2395 -1165) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -1010) (170 170))
+   rect(l23 (-2350 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-215 555) (265 420))
+   rect(l2 (-2430 -1410) (250 720))
+   rect(l2 (-250 270) (265 420))
+   rect(l2 (1915 -1410) (250 720))
+   rect(l6 (-2430 -720) (250 720))
+   rect(l6 (1930 -720) (250 720))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(vdd))
+  pin(6 name(wl))
+  pin(7 name(bl))
+  pin(8 name(bl_n))
+  pin(10 name(vss))
+
+  # Devices and their connections
+  device(1 D$sky130_fd_pr__nfet_01v8__model
+   location(605 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 10)
+  )
+  device(2 D$sky130_fd_pr__nfet_01v8__model$1
+   location(215 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 3)
+   terminal(G 4)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(3 D$sky130_fd_pr__nfet_01v8__model$2
+   location(1575 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 4)
+   terminal(B 10)
+  )
+  device(4 D$sky130_fd_pr__nfet_01v8__model$3
+   location(1965 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(5 D$sky130_fd_pr__pfet_01v8__model
+   location(1965 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(6 D$sky130_fd_pr__pfet_01v8__model$1
+   location(215 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 5)
+   terminal(G 4)
+   terminal(D 3)
+   terminal(B 5)
+  )
+
+ )
+ circuit(SP6TArray_2X1
+
+  # Circuit boundary
+  rect((-385 -305) (2950 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name(vdd)
+   rect(l14 (-160 -130) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l14 (-1250 5420) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -5680) (2500 260))
+   rect(l13 (-2500 5290) (2500 260))
+  )
+  net(4 name('wl[0]')
+   rect(l14 (0 1785) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(5 name('wl[1]')
+   rect(l14 (0 3505) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(6 name(vss)
+   rect(l14 (-160 2645) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name(vdd))
+  pin(4 name('wl[0]'))
+  pin(5 name('wl[1]'))
+  pin(6 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCell location(0 2775)
+   pin(0 3)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+  circuit(2 SP6TCell mirror location(0 2775)
+   pin(0 3)
+   pin(1 4)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TArray_2X2
+
+  # Circuit boundary
+  rect((-385 -305) (5130 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name(vdd)
+   rect(l14 (-160 5420) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l14 (-2340 -5680) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 5420) (4680 260))
+   rect(l13 (-4680 -5810) (4680 260))
+  )
+  net(6 name('wl[0]')
+   rect(l14 (0 1785) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(7 name('wl[1]')
+   rect(l14 (0 3505) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(8 name(vss)
+   rect(l14 (-160 2645) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 -130) (4680 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name('bl[1]'))
+  pin(4 name('bl_n[1]'))
+  pin(5 name(vdd))
+  pin(6 name('wl[0]'))
+  pin(7 name('wl[1]'))
+  pin(8 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X1 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+  circuit(2 SP6TArray_2X1 location(2180 0)
+   pin(0 3)
+   pin(1 4)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TArray_2X4
+
+  # Circuit boundary
+  rect((-385 -305) (9490 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name('bl[2]')
+   rect(l12 (4790 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(6 name('bl_n[2]')
+   rect(l12 (5880 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(7 name('bl[3]')
+   rect(l12 (6970 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(8 name('bl_n[3]')
+   rect(l12 (8060 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(9 name(vdd)
+   rect(l14 (-160 -130) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l14 (-4520 5420) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -5680) (9040 260))
+   rect(l13 (-9040 5290) (9040 260))
+  )
+  net(10 name('wl[0]')
+   rect(l14 (0 1785) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(11 name('wl[1]')
+   rect(l14 (0 3505) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(12 name(vss)
+   rect(l14 (-160 2645) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -130) (9040 260))
+  )
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X2 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+  circuit(2 SP6TArray_2X2 location(4360 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 8)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(SKY130_FD_PR__PFET_01V8__MODEL MOS4)
+ class(SKY130_FD_PR__NFET_01V8__MODEL MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCELL
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(VSS))
+  net(3 name(WL))
+  net(4 name(BL))
+  net(5 name(BL_N))
+  net(6 name(BIT_N))
+  net(7 name(BIT))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(VSS))
+  pin(3 name(WL))
+  pin(4 name(BL))
+  pin(5 name(BL_N))
+
+  # Devices and their connections
+  device(1 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(2 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(3 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(4 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 2)
+  )
+  device(5 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 3)
+   terminal(D 4)
+   terminal(B 2)
+  )
+  device(6 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 2)
+  )
+
+ )
+ circuit(SP6TARRAY_2X1
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCELL name(INST0X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 3)
+   pin(3 5)
+   pin(4 6)
+  )
+  circuit(2 SP6TCELL name(INST1X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 4)
+   pin(3 5)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TARRAY_2X2
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X1 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+  )
+  circuit(2 SP6TARRAY_2X1 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TARRAY_2X4
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+  net(9 name('BL[2]'))
+  net(10 name('BL_N[2]'))
+  net(11 name('BL[3]'))
+  net(12 name('BL_N[3]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+  pin(9 name('BL[2]'))
+  pin(10 name('BL_N[2]'))
+  pin(11 name('BL[3]'))
+  pin(12 name('BL_N[3]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X2 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+   pin(6 7)
+   pin(7 8)
+  )
+  circuit(2 SP6TARRAY_2X2 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(SP6TArray_2X1 SP6TARRAY_2X1 match
+  xref(
+   net(1 5 match)
+   net(2 6 match)
+   net(3 2 match)
+   net(6 1 match)
+   net(4 3 warning)
+   net(5 4 warning)
+   pin(0 4 match)
+   pin(1 5 match)
+   pin(2 1 match)
+   pin(5 0 match)
+   pin(3 2 match)
+   pin(4 3 match)
+   circuit(2 1 match)
+   circuit(1 2 match)
+  )
+ )
+ circuit(SP6TArray_2X2 SP6TARRAY_2X2 match
+  xref(
+   net(1 5 match)
+   net(3 7 match)
+   net(2 6 warning)
+   net(4 8 warning)
+   net(5 2 match)
+   net(8 1 match)
+   net(6 3 match)
+   net(7 4 match)
+   pin(0 4 match)
+   pin(2 6 match)
+   pin(1 5 match)
+   pin(3 7 match)
+   pin(4 1 match)
+   pin(7 0 match)
+   pin(5 2 match)
+   pin(6 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TArray_2X4 SP6TARRAY_2X4 match
+  xref(
+   net(1 5 match)
+   net(3 7 warning)
+   net(5 9 match)
+   net(7 11 warning)
+   net(2 6 match)
+   net(4 8 match)
+   net(6 10 match)
+   net(8 12 match)
+   net(9 2 match)
+   net(12 1 match)
+   net(10 3 match)
+   net(11 4 match)
+   pin(() 4 match)
+   pin(() 6 match)
+   pin(() 8 match)
+   pin(() 10 match)
+   pin(() 5 match)
+   pin(() 7 match)
+   pin(() 9 match)
+   pin(() 11 match)
+   pin(() 1 match)
+   pin(() 0 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TCell SP6TCELL match
+  xref(
+   net(3 7 warning)
+   net(4 6 warning)
+   net(7 4 match)
+   net(8 5 match)
+   net(5 1 match)
+   net(10 2 match)
+   net(6 3 match)
+   pin(2 3 match)
+   pin(3 4 match)
+   pin(0 0 match)
+   pin(4 1 match)
+   pin(1 2 match)
+   device(2 3 match)
+   device(4 4 match)
+   device(1 5 match)
+   device(3 6 match)
+   device(6 1 match)
+   device(5 2 match)
+  )
+ )
+)
diff --git a/testdata/lvs/test_22d.lvsdb.2 b/testdata/lvs/test_22d.lvsdb.2
new file mode 100644
index 000000000..253f1dbb1
--- /dev/null
+++ b/testdata/lvs/test_22d.lvsdb.2
@@ -0,0 +1,952 @@
+#%lvsdb-klayout
+
+# Layout
+layout(
+ top(SP6TArray_2X4)
+ unit(0.001)
+
+ # Layer section
+ # This section lists the mask layers (drawing or derived) and their connections.
+
+ # Mask layers
+ layer(l5 '64/20')
+ layer(l3)
+ layer(l8)
+ layer(l7 '66/20')
+ layer(l10)
+ layer(l9 '67/20')
+ layer(l12 '68/16')
+ layer(l11 '68/20')
+ layer(l14 '69/16')
+ layer(l13 '69/20')
+ layer(l16)
+ layer(l15)
+ layer(l18)
+ layer(l17)
+ layer(l20)
+ layer(l19)
+ layer(l21 '66/44')
+ layer(l23 '67/44')
+ layer(l24 '68/44')
+ layer(l25)
+ layer(l26)
+ layer(l27)
+ layer(l22)
+ layer(l2)
+ layer(l4)
+ layer(l6)
+ layer(l1)
+
+ # Mask layer connectivity
+ connect(l5 l5 l4)
+ connect(l3 l3 l2)
+ connect(l8 l8 l7)
+ connect(l7 l8 l7)
+ connect(l10 l10 l9)
+ connect(l9 l10 l9 l21 l23)
+ connect(l12 l12 l11)
+ connect(l11 l12 l11 l23 l24)
+ connect(l14 l14 l13)
+ connect(l13 l14 l13 l24 l25)
+ connect(l16 l16 l15)
+ connect(l15 l16 l15 l25 l26)
+ connect(l18 l18 l17)
+ connect(l17 l18 l17 l26 l27)
+ connect(l20 l20 l19)
+ connect(l19 l20 l19 l27)
+ connect(l21 l9 l21 l22 l2)
+ connect(l23 l9 l11 l23)
+ connect(l24 l11 l13 l24)
+ connect(l25 l13 l15 l25)
+ connect(l26 l15 l17 l26)
+ connect(l27 l17 l19 l27)
+ connect(l22 l21 l22)
+ connect(l2 l3 l21 l2 l4 l6)
+ connect(l4 l5 l2 l4)
+ connect(l6 l2 l6)
+ connect(l1 l1)
+
+ # Global nets and connectivity
+ global(l6 vss)
+ global(l1 vss)
+
+ # Device class section
+ class(active_res RES)
+ class(poly_res RES)
+ class(sky130_fd_pr__diode_pw2nd_05v5 DIODE)
+ class(sky130_fd_pr__diode_pd2nw_05v5 DIODE)
+ class(sky130_fd_pr__nfet_01v8__model MOS4)
+ class(sky130_fd_pr__nfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__nfet_g5v0d10v5__model MOS4)
+ class(sky130_fd_pr__pfet_01v8__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_hvt__model MOS4)
+ class(sky130_fd_pr__pfet_01v8_lvt__model MOS4)
+ class(sky130_fd_pr__pfet_g5v0d10v5__model MOS4)
+
+ # Device abstracts section
+ # Device abstracts list the pin shapes of the devices.
+ device(D$sky130_fd_pr__nfet_01v8__model sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$2 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   rect(l2 (-210 -340) (420 265))
+  )
+  terminal(G
+   rect(l22 (-210 -75) (420 150))
+  )
+  terminal(D
+   polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(B
+   rect(l1 (-210 -75) (420 150))
+  )
+ )
+ device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model
+  terminal(S
+   polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l1 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-520 -210) (445 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (265 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+ device(D$sky130_fd_pr__pfet_01v8__model$1 sky130_fd_pr__pfet_01v8__model
+  terminal(S
+   rect(l2 (-340 -210) (265 420))
+  )
+  terminal(G
+   rect(l22 (-75 -210) (150 420))
+  )
+  terminal(D
+   rect(l2 (75 -210) (445 420))
+  )
+  terminal(B
+   rect(l5 (-75 -210) (150 420))
+  )
+ )
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCell
+
+  # Circuit boundary
+  rect((-385 -485) (2950 3565))
+
+  # Nets with their geometries
+  net(1
+   rect(l7 (1890 500) (150 2010))
+   rect(l7 (-1100 -1320) (950 150))
+   rect(l7 (-1280 -150) (330 270))
+  )
+  net(2
+   rect(l7 (1240 1550) (330 270))
+   rect(l7 (-1280 -150) (950 150))
+   rect(l7 (-1100 -1320) (150 2010))
+  )
+  net(3
+   polygon(l9 (525 760) (0 1570) (170 0) (0 -920) (245 0) (0 -170) (-245 0) (0 -480))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-5 -1010) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (950 -960) (150 2010))
+   rect(l22 (-1100 -1320) (950 150))
+   polygon(l2 (-1495 -1050) (0 340) (-105 0) (0 420) (525 0) (0 -760))
+   rect(l2 (-525 1670) (445 420))
+  )
+  net(4
+   polygon(l9 (1485 760) (0 840) (-245 0) (0 170) (245 0) (0 560) (170 0) (0 -1570))
+   rect(l21 (-170 80) (170 170))
+   rect(l21 (-170 1070) (170 170))
+   rect(l21 (-335 -650) (170 170))
+   rect(l22 (-250 -220) (330 270))
+   rect(l22 (-1280 -150) (950 150))
+   rect(l22 (-1100 -1320) (150 2010))
+   polygon(l2 (1075 -2220) (0 760) (525 0) (0 -420) (-105 0) (0 -340))
+   rect(l2 (-340 1670) (445 420))
+  )
+  net(5 name(vdd)
+   rect(l5 (-385 1780) (2950 1300))
+   rect(l9 (-2650 -1075) (170 685))
+   rect(l9 (-250 0) (2510 170))
+   rect(l9 (-250 -855) (170 685))
+   rect(l11 (-2395 -75) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l21 (2010 435) (170 170))
+   rect(l21 (-170 -775) (170 170))
+   rect(l23 (-2350 435) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-2460 -200) (2590 250))
+   rect(l2 (-2510 -940) (265 420))
+   rect(l2 (1900 -420) (265 420))
+   rect(l4 (-2510 270) (2590 250))
+  )
+  net(6 name(wl)
+   rect(l9 (1005 140) (170 500))
+   polygon(l11 (-200 -230) (0 290) (-15 0) (0 320) (260 0) (0 -320) (-15 0) (0 -290))
+   rect(l14 (-1205 320) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+   rect(l21 (-1175 -770) (170 170))
+   rect(l23 (-170 80) (170 170))
+   rect(l24 (-160 145) (150 150))
+   polygon(l22 (-900 -795) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(7 name(bl)
+   polygon(l9 (520 -165) (0 80) (-60 0) (0 170) (60 0) (0 80) (170 0) (0 -330))
+   rect(l12 (-260 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-140 -2860) (170 170))
+   rect(l23 (-230 -170) (170 170))
+   rect(l2 (-235 -210) (420 265))
+  )
+  net(8 name(bl_n)
+   polygon(l9 (1490 -165) (0 330) (170 0) (0 -80) (60 0) (0 -170) (-60 0) (0 -80))
+   rect(l12 (-140 20) (230 2920))
+   rect(l12 (-115 -1460) (0 0))
+   rect(l11 (-115 -1460) (230 2920))
+   rect(l21 (-260 -2860) (170 170))
+   rect(l23 (-110 -170) (170 170))
+   rect(l2 (-355 -210) (420 265))
+  )
+  net(9
+   polygon(l7 (265 140) (0 150) (690 0) (0 180) (270 0) (0 -180) (690 0) (0 -150))
+  )
+  net(10 name(vss)
+   rect(l9 (-85 -165) (170 1170))
+   rect(l9 (2010 -1170) (170 1170))
+   rect(l11 (-2395 -1165) (260 320))
+   rect(l11 (1920 -320) (260 320))
+   rect(l14 (-2470 -290) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+   rect(l21 (-2425 -215) (170 170))
+   rect(l21 (-170 670) (170 170))
+   rect(l21 (2010 -170) (170 170))
+   rect(l21 (-170 -1010) (170 170))
+   rect(l23 (-2350 -170) (170 170))
+   rect(l23 (2010 -170) (170 170))
+   rect(l24 (-2340 -160) (150 150))
+   rect(l24 (2030 -150) (150 150))
+   rect(l2 (-215 555) (265 420))
+   rect(l2 (-2430 -1410) (250 720))
+   rect(l2 (-250 270) (265 420))
+   rect(l2 (1915 -1410) (250 720))
+   rect(l6 (-2430 -720) (250 720))
+   rect(l6 (1930 -720) (250 720))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(5 name(vdd))
+  pin(6 name(wl))
+  pin(7 name(bl))
+  pin(8 name(bl_n))
+  pin(10 name(vss))
+
+  # Devices and their connections
+  device(1 D$sky130_fd_pr__nfet_01v8__model
+   location(605 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 3)
+   terminal(B 10)
+  )
+  device(2 D$sky130_fd_pr__nfet_01v8__model$1
+   location(215 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 3)
+   terminal(G 4)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(3 D$sky130_fd_pr__nfet_01v8__model$2
+   location(1575 215)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.18165)
+   param(PS 1.37)
+   param(PD 1.285)
+   terminal(S 8)
+   terminal(G 6)
+   terminal(D 4)
+   terminal(B 10)
+  )
+  device(4 D$sky130_fd_pr__nfet_01v8__model$3
+   location(1965 840)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.18165)
+   param(AD 0.1113)
+   param(PS 1.285)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 10)
+   terminal(B 10)
+  )
+  device(5 D$sky130_fd_pr__pfet_01v8__model
+   location(1965 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1869)
+   param(AD 0.1113)
+   param(PS 1.73)
+   param(PD 1.37)
+   terminal(S 4)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 5)
+  )
+  device(6 D$sky130_fd_pr__pfet_01v8__model$1
+   location(215 2170)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0.1113)
+   param(AD 0.1869)
+   param(PS 1.37)
+   param(PD 1.73)
+   terminal(S 5)
+   terminal(G 4)
+   terminal(D 3)
+   terminal(B 5)
+  )
+
+ )
+ circuit(SP6TArray_2X1
+
+  # Circuit boundary
+  rect((-385 -305) (2950 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name(vdd)
+   rect(l14 (-160 -130) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l14 (-1250 5420) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -5680) (2500 260))
+   rect(l13 (-2500 5290) (2500 260))
+  )
+  net(4 name('wl[0]')
+   rect(l14 (0 1785) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(5 name('wl[1]')
+   rect(l14 (0 3505) (2180 260))
+   rect(l14 (-1090 -130) (0 0))
+   rect(l13 (-1090 -130) (2180 260))
+  )
+  net(6 name(vss)
+   rect(l14 (-160 2645) (2500 260))
+   rect(l14 (-1250 -130) (0 0))
+   rect(l13 (-1250 -130) (2500 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name(vdd))
+  pin(4 name('wl[0]'))
+  pin(5 name('wl[1]'))
+  pin(6 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCell location(0 2775)
+   pin(0 3)
+   pin(1 5)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+  circuit(2 SP6TCell mirror location(0 2775)
+   pin(0 3)
+   pin(1 4)
+   pin(2 1)
+   pin(3 2)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TArray_2X2
+
+  # Circuit boundary
+  rect((-385 -305) (5130 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name(vdd)
+   rect(l14 (-160 5420) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l14 (-2340 -5680) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 5420) (4680 260))
+   rect(l13 (-4680 -5810) (4680 260))
+  )
+  net(6 name('wl[0]')
+   rect(l14 (0 1785) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(7 name('wl[1]')
+   rect(l14 (0 3505) (4360 260))
+   rect(l14 (-2180 -130) (0 0))
+   rect(l13 (-2180 -130) (4360 260))
+  )
+  net(8 name(vss)
+   rect(l14 (-160 2645) (4680 260))
+   rect(l14 (-2340 -130) (0 0))
+   rect(l13 (-2340 -130) (4680 260))
+  )
+
+  # Outgoing pins and their connections to nets
+  pin(1 name('bl[0]'))
+  pin(2 name('bl_n[0]'))
+  pin(3 name('bl[1]'))
+  pin(4 name('bl_n[1]'))
+  pin(5 name(vdd))
+  pin(6 name('wl[0]'))
+  pin(7 name('wl[1]'))
+  pin(8 name(vss))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X1 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+  circuit(2 SP6TArray_2X1 location(2180 0)
+   pin(0 3)
+   pin(1 4)
+   pin(2 5)
+   pin(3 6)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TArray_2X4
+
+  # Circuit boundary
+  rect((-385 -305) (9490 6160))
+
+  # Nets with their geometries
+  net(1 name('bl[0]')
+   rect(l12 (430 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(2 name('bl_n[0]')
+   rect(l12 (1520 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(3 name('bl[1]')
+   rect(l12 (2610 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(4 name('bl_n[1]')
+   rect(l12 (3700 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(5 name('bl[2]')
+   rect(l12 (4790 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(6 name('bl_n[2]')
+   rect(l12 (5880 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(7 name('bl[3]')
+   rect(l12 (6970 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(8 name('bl_n[3]')
+   rect(l12 (8060 0) (230 5550))
+   rect(l12 (-115 -2775) (0 0))
+   rect(l11 (-115 -2775) (230 5550))
+  )
+  net(9 name(vdd)
+   rect(l14 (-160 -130) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l14 (-4520 5420) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -5680) (9040 260))
+   rect(l13 (-9040 5290) (9040 260))
+  )
+  net(10 name('wl[0]')
+   rect(l14 (0 1785) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(11 name('wl[1]')
+   rect(l14 (0 3505) (8720 260))
+   rect(l14 (-4360 -130) (0 0))
+   rect(l13 (-4360 -130) (8720 260))
+  )
+  net(12 name(vss)
+   rect(l14 (-160 2645) (9040 260))
+   rect(l14 (-4520 -130) (0 0))
+   rect(l13 (-4520 -130) (9040 260))
+  )
+
+  # Subcircuits and their connections
+  circuit(1 SP6TArray_2X2 location(0 0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+  circuit(2 SP6TArray_2X2 location(4360 0)
+   pin(0 5)
+   pin(1 6)
+   pin(2 7)
+   pin(3 8)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Reference netlist
+reference(
+
+ # Device class section
+ class(SKY130_FD_PR__PFET_01V8__MODEL MOS4)
+ class(SKY130_FD_PR__NFET_01V8__MODEL MOS4)
+
+ # Circuit section
+ # Circuits are the hierarchical building blocks of the netlist.
+ circuit(SP6TCELL
+
+  # Nets
+  net(1 name(VDD))
+  net(2 name(VSS))
+  net(3 name(WL))
+  net(4 name(BL))
+  net(5 name(BL_N))
+  net(6 name(BIT_N))
+  net(7 name(BIT))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VDD))
+  pin(2 name(VSS))
+  pin(3 name(WL))
+  pin(4 name(BL))
+  pin(5 name(BL_N))
+
+  # Devices and their connections
+  device(1 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 1)
+   terminal(B 1)
+  )
+  device(2 SKY130_FD_PR__PFET_01V8__MODEL
+   name(PU2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 1)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 1)
+  )
+  device(3 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 6)
+   terminal(D 2)
+   terminal(B 2)
+  )
+  device(4 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PD2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 2)
+   terminal(G 7)
+   terminal(D 6)
+   terminal(B 2)
+  )
+  device(5 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG1)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 7)
+   terminal(G 3)
+   terminal(D 4)
+   terminal(B 2)
+  )
+  device(6 SKY130_FD_PR__NFET_01V8__MODEL
+   name(PG2)
+   param(L 0.15)
+   param(W 0.42)
+   param(AS 0)
+   param(AD 0)
+   param(PS 0)
+   param(PD 0)
+   terminal(S 6)
+   terminal(G 3)
+   terminal(D 5)
+   terminal(B 2)
+  )
+
+ )
+ circuit(SP6TARRAY_2X1
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TCELL name(INST0X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 3)
+   pin(3 5)
+   pin(4 6)
+  )
+  circuit(2 SP6TCELL name(INST1X0)
+   pin(0 2)
+   pin(1 1)
+   pin(2 4)
+   pin(3 5)
+   pin(4 6)
+  )
+
+ )
+ circuit(SP6TARRAY_2X2
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X1 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+  )
+  circuit(2 SP6TARRAY_2X1 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 7)
+   pin(5 8)
+  )
+
+ )
+ circuit(SP6TARRAY_2X4
+
+  # Nets
+  net(1 name(VSS))
+  net(2 name(VDD))
+  net(3 name('WL[0]'))
+  net(4 name('WL[1]'))
+  net(5 name('BL[0]'))
+  net(6 name('BL_N[0]'))
+  net(7 name('BL[1]'))
+  net(8 name('BL_N[1]'))
+  net(9 name('BL[2]'))
+  net(10 name('BL_N[2]'))
+  net(11 name('BL[3]'))
+  net(12 name('BL_N[3]'))
+
+  # Outgoing pins and their connections to nets
+  pin(1 name(VSS))
+  pin(2 name(VDD))
+  pin(3 name('WL[0]'))
+  pin(4 name('WL[1]'))
+  pin(5 name('BL[0]'))
+  pin(6 name('BL_N[0]'))
+  pin(7 name('BL[1]'))
+  pin(8 name('BL_N[1]'))
+  pin(9 name('BL[2]'))
+  pin(10 name('BL_N[2]'))
+  pin(11 name('BL[3]'))
+  pin(12 name('BL_N[3]'))
+
+  # Subcircuits and their connections
+  circuit(1 SP6TARRAY_2X2 name(INST0X0)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 5)
+   pin(5 6)
+   pin(6 7)
+   pin(7 8)
+  )
+  circuit(2 SP6TARRAY_2X2 name(INST0X1)
+   pin(0 1)
+   pin(1 2)
+   pin(2 3)
+   pin(3 4)
+   pin(4 9)
+   pin(5 10)
+   pin(6 11)
+   pin(7 12)
+  )
+
+ )
+)
+
+# Cross reference
+xref(
+ circuit(SP6TArray_2X1 SP6TARRAY_2X1 match
+  xref(
+   net(1 5 match)
+   net(2 6 match)
+   net(3 2 match)
+   net(6 1 match)
+   net(4 3 match)
+   net(5 4 match)
+   pin(0 4 match)
+   pin(1 5 match)
+   pin(2 1 match)
+   pin(5 0 match)
+   pin(3 2 match)
+   pin(4 3 match)
+   circuit(2 1 match)
+   circuit(1 2 match)
+  )
+ )
+ circuit(SP6TArray_2X2 SP6TARRAY_2X2 match
+  xref(
+   net(1 5 match)
+   net(3 7 match)
+   net(2 6 match)
+   net(4 8 match)
+   net(5 2 match)
+   net(8 1 match)
+   net(6 3 match)
+   net(7 4 match)
+   pin(0 4 match)
+   pin(2 6 match)
+   pin(1 5 match)
+   pin(3 7 match)
+   pin(4 1 match)
+   pin(7 0 match)
+   pin(5 2 match)
+   pin(6 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TArray_2X4 SP6TARRAY_2X4 match
+  xref(
+   net(1 5 match)
+   net(3 7 match)
+   net(5 9 match)
+   net(7 11 match)
+   net(2 6 match)
+   net(4 8 match)
+   net(6 10 match)
+   net(8 12 match)
+   net(9 2 match)
+   net(12 1 match)
+   net(10 3 match)
+   net(11 4 match)
+   pin(() 4 match)
+   pin(() 6 match)
+   pin(() 8 match)
+   pin(() 10 match)
+   pin(() 5 match)
+   pin(() 7 match)
+   pin(() 9 match)
+   pin(() 11 match)
+   pin(() 1 match)
+   pin(() 0 match)
+   pin(() 2 match)
+   pin(() 3 match)
+   circuit(1 1 match)
+   circuit(2 2 match)
+  )
+ )
+ circuit(SP6TCell SP6TCELL match
+  xref(
+   net(3 7 match)
+   net(4 6 match)
+   net(7 4 match)
+   net(8 5 match)
+   net(5 1 match)
+   net(10 2 match)
+   net(6 3 match)
+   pin(2 3 match)
+   pin(3 4 match)
+   pin(0 0 match)
+   pin(4 1 match)
+   pin(1 2 match)
+   device(2 3 match)
+   device(4 4 match)
+   device(1 5 match)
+   device(3 6 match)
+   device(6 1 match)
+   device(5 2 match)
+  )
+ )
+)