From 4acc4b96e21162f4da77c1c98ba5dd3341c78df4 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Mon, 9 Dec 2019 21:37:02 +0100 Subject: [PATCH 01/21] First attempt to fix the issue Problem was caching which did not take into account the array nature of instances. This fix also moves the cache one level below so it is effective also when instance tree traversal happens. This might speed up things too. Needs testing. --- src/db/db/dbHierNetworkProcessor.cc | 172 +++++++++++------- src/db/db/dbHierNetworkProcessor.h | 19 +- .../unit_tests/dbHierNetworkProcessorTests.cc | 5 + 3 files changed, 129 insertions(+), 67 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 1728f32d6..fdf8a492e 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1177,37 +1177,21 @@ public: */ void add (const db::Instance *i1, unsigned int /*p1*/, const db::Instance *i2, unsigned int /*p2*/) { - db::ICplxTrans t1 = i1->complex_trans (); - db::ICplxTrans t2 = i2->complex_trans (); - db::ICplxTrans t21 = t1.inverted () * t2; + std::list > ic; - InstanceToInstanceInteraction ii_key (i1->cell_index (), i2->cell_index (), t21); - - instance_interaction_cache_type::iterator ii = mp_instance_interaction_cache->find (ii_key); - if (ii != mp_instance_interaction_cache->end ()) { - - db::ICplxTrans ic_trans = t1 * ii->second.first.inverted (); - connect_clusters (ii->second.second, &ic_trans, i1->prop_id (), i2->prop_id ()); - - } else { - - std::list > &ic = mp_instance_interaction_cache->insert (std::make_pair (ii_key, std::make_pair (t1, cluster_instance_pair_list_type ()))).first->second.second; - - std::vector p; - db::ICplxTrans t; - add_pair (box_type::world (), *i1, p, t, *i2, p, t, ic); + std::vector p; + db::ICplxTrans t; + add_pair (box_type::world (), *i1, p, t, *i2, p, t, ic); #if 1 - // For debugging: ensures the instance properties are configured properly (important for cache consistency) - for (cluster_instance_pair_list_type::const_iterator i = ic.begin (); i != ic.end (); ++i) { - tl_assert (i->first.inst_prop_id () == i1->prop_id ()); - tl_assert (i->second.inst_prop_id () == i2->prop_id ()); - } + // For debugging: ensures the instance properties are configured properly (important for cache consistency) + for (cluster_instance_pair_list_type::const_iterator i = ic.begin (); i != ic.end (); ++i) { + tl_assert (i->first.inst_prop_id () == i1->prop_id ()); + tl_assert (i->second.inst_prop_id () == i2->prop_id ()); + } #endif - connect_clusters (ic); - - } + connect_clusters (ic); } /** @@ -1280,7 +1264,7 @@ private: : public InstanceToInstanceInteraction { InteractionKeyForClustersType (db::cell_index_type _ci1, db::cell_index_type _ci2, const db::ICplxTrans &_t21, const box_type &_box) - : InstanceToInstanceInteraction (_ci1, _ci2, _t21), box (_box) + : InstanceToInstanceInteraction (_ci1, 0, _ci2, 0, _t21), box (_box) { } bool operator== (const InteractionKeyForClustersType &other) const @@ -1326,7 +1310,7 @@ private: * @param p2 The instantiation path to the child cell (not including i2) * @param t2 The accumulated transformation of the path, not including i2 */ - void add_pair (const box_type &common, const db::Instance &i1, const std::vector &p1, const db::ICplxTrans &t1, const db::Instance &i2, const std::vector &p2, const db::ICplxTrans &t2, std::list > &interacting_clusters) + void add_pair (const box_type &common, const db::Instance &i1, const std::vector &p1, const db::ICplxTrans &t1, const db::Instance &i2, const std::vector &p2, const db::ICplxTrans &t2, std::list > &interacting_clusters_out) { if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { return; @@ -1344,63 +1328,125 @@ private: return; } - db::ICplxTrans t1i = t1.inverted (); - db::ICplxTrans t2i = t2.inverted (); + db::ICplxTrans tt2 = t2 * i2.complex_trans (); + db::ICplxTrans tt1 = t1 * i1.complex_trans (); - for (db::CellInstArray::iterator ii1 = i1.begin_touching (common_all.transformed (t1i), mp_layout); ! ii1.at_end (); ++ii1) { + db::ICplxTrans tt21 = tt1.inverted () * tt2; + InstanceToInstanceInteraction ii_key (i1.cell_index (), i1.cell_inst ().delegate (), i2.cell_index (), i2.cell_inst ().delegate (), tt21); - db::ICplxTrans tt1 = t1 * i1.complex_trans (*ii1); - box_type ib1 = bb1.transformed (tt1); + instance_interaction_cache_type::iterator ii = mp_instance_interaction_cache->find (ii_key); + if (ii != mp_instance_interaction_cache->end ()) { + // take from cache if possible + db::ICplxTrans ic_trans = tt1 * ii->second.first.inverted (); + for (cluster_instance_pair_list_type::const_iterator ic = ii->second.second.begin (); ic != ii->second.second.end (); ++ic) { + interacting_clusters_out.push_back (*ic); + interacting_clusters_out.back ().first.transform (ic_trans); + interacting_clusters_out.back ().second.transform (ic_trans); + } + return; + } + std::list > &interacting_clusters = mp_instance_interaction_cache->insert (std::make_pair (ii_key, std::make_pair (tt1, cluster_instance_pair_list_type ()))).first->second.second; + + if (i1.size () == 1 && i2.size () == 1) { + + // single-to-single instance interactions + + // TODO: can't we just add the new item to the path and remove it later? std::vector pp1; pp1.reserve (p1.size () + 1); pp1.insert (pp1.end (), p1.begin (), p1.end ()); - pp1.push_back (ClusterInstElement (i1.cell_index (), i1.complex_trans (*ii1), i1.prop_id ())); + pp1.push_back (ClusterInstElement (i1.cell_index (), i1.complex_trans (), i1.prop_id ())); - for (db::CellInstArray::iterator ii2 = i2.begin_touching (ib1.transformed (t2i), mp_layout); ! ii2.at_end (); ++ii2) { + // skip interactions between identical instances (duplicate instance removal) + if (i1.cell_index () != i2.cell_index () || tt1 != tt2) { - db::ICplxTrans tt2 = t2 * i2.complex_trans (*ii2); - if (i1.cell_index () == i2.cell_index () && tt1 == tt2) { - // skip interactions between identical instances (duplicate instance removal) - continue; + std::vector pp2; + pp2.reserve (p2.size () + 1); + pp2.insert (pp2.end (), p2.begin (), p2.end ()); + pp2.push_back (ClusterInstElement (i2.cell_index (), i2.complex_trans (), i2.prop_id ())); + + add_single_pair (common_all, i1.cell_index (), pp1, tt1, i2.cell_index (), pp2, tt2, interacting_clusters); + + // dive into cell of i2 + const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); + for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common_all.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { + add_pair (common_all, i1, p1, t1, *jj2, pp2, tt2, interacting_clusters); } - box_type ib2 = bb2.transformed (tt2); + } - box_type common12 = ib1 & ib2 & common; + // dive into cell of i1 + const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); + for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common_all.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { + add_pair (common_all, *jj1, pp1, tt1, i2, p2, t2, interacting_clusters); + } - if (! common12.empty ()) { + } else { - std::vector pp2; - pp2.reserve (p2.size () + 1); - pp2.insert (pp2.end (), p2.begin (), p2.end ()); - pp2.push_back (ClusterInstElement (i2.cell_index (), i2.complex_trans (*ii2), i2.prop_id ())); + // array interactions - add_single_pair (common12, i1.cell_index (), pp1, tt1, i2.cell_index (), pp2, tt2, interacting_clusters); + db::ICplxTrans t1i = t1.inverted (); + db::ICplxTrans t2i = t2.inverted (); - // dive into cell of ii2 - const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); - for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common12.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - add_pair (common12, i1, p1, t1, *jj2, pp2, tt2, interacting_clusters); + for (db::CellInstArray::iterator ii1 = i1.begin_touching (common_all.transformed (t1i), mp_layout); ! ii1.at_end (); ++ii1) { + + db::ICplxTrans tt1 = t1 * i1.complex_trans (*ii1); + box_type ib1 = bb1.transformed (tt1); + + std::vector pp1; + pp1.reserve (p1.size () + 1); + pp1.insert (pp1.end (), p1.begin (), p1.end ()); + pp1.push_back (ClusterInstElement (i1.cell_index (), i1.complex_trans (*ii1), i1.prop_id ())); + + for (db::CellInstArray::iterator ii2 = i2.begin_touching (ib1.transformed (t2i), mp_layout); ! ii2.at_end (); ++ii2) { + + db::ICplxTrans tt2 = t2 * i2.complex_trans (*ii2); + if (i1.cell_index () == i2.cell_index () && tt1 == tt2) { + // skip interactions between identical instances (duplicate instance removal) + continue; + } + + box_type ib2 = bb2.transformed (tt2); + + box_type common12 = ib1 & ib2 & common; + + if (! common12.empty ()) { + + std::vector pp2; + pp2.reserve (p2.size () + 1); + pp2.insert (pp2.end (), p2.begin (), p2.end ()); + pp2.push_back (ClusterInstElement (i2.cell_index (), i2.complex_trans (*ii2), i2.prop_id ())); + + add_single_pair (common12, i1.cell_index (), pp1, tt1, i2.cell_index (), pp2, tt2, interacting_clusters); + + // dive into cell of ii2 + const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); + for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common12.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { + add_pair (common12, i1, p1, t1, *jj2, pp2, tt2, interacting_clusters); + } + + } + + } + + box_type common1 = ib1 & b2 & common; + + if (! common1.empty ()) { + + // dive into cell of ii1 + const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); + for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common1.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { + add_pair (common1, *jj1, pp1, tt1, i2, p2, t2, interacting_clusters); } } } - box_type common1 = ib1 & b2 & common; - - if (! common1.empty ()) { - - // dive into cell of ii1 - const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); - for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common1.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { - add_pair (common1, *jj1, pp1, tt1, i2, p2, t2, interacting_clusters); - } - - } - } + + interacting_clusters_out.insert (interacting_clusters_out.end (), interacting_clusters.begin (), interacting_clusters.end ()); } /** diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index a47e93bd8..3c90dafdb 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -739,13 +739,15 @@ typedef std::list > cluster_instance */ struct InstanceToInstanceInteraction { - InstanceToInstanceInteraction (db::cell_index_type _ci1, db::cell_index_type _ci2, const db::ICplxTrans &_t21) - : ci1 (_ci1), ci2 (_ci2), t21 (_t21) + InstanceToInstanceInteraction (db::cell_index_type _ci1, const db::ArrayBase *_array1, db::cell_index_type _ci2, const db::ArrayBase *_array2, const db::ICplxTrans &_t21) + : ci1 (_ci1), ci2 (_ci2), array1 (_array1), array2 (_array2), t21 (_t21) { } bool operator== (const InstanceToInstanceInteraction &other) const { - return ci1 == other.ci1 && ci2 == other.ci2 && t21.equal (other.t21); + static const db::array_base_ptr_cmp_f arr_less; + return ci1 == other.ci1 && ci2 == other.ci2 && t21.equal (other.t21) && + (array1 == 0) == (array2 == 0) && array1 != 0 && ! arr_less (array1, array2) && ! arr_less (array2, array1); } bool operator< (const InstanceToInstanceInteraction &other) const @@ -759,10 +761,19 @@ struct InstanceToInstanceInteraction if (! t21.equal (other.t21)) { return t21.less (other.t21); } - return false; + if ((array1 == 0) != (array2 == 0)) { + return (array1 == 0) < (array2 == 0); + } + if (array1 != 0) { + static const db::array_base_ptr_cmp_f arr_less; + return arr_less (array1, array2); + } else { + return false; + } } db::cell_index_type ci1, ci2; + const db::ArrayBase *array1, *array2; db::ICplxTrans t21; }; diff --git a/src/db/unit_tests/dbHierNetworkProcessorTests.cc b/src/db/unit_tests/dbHierNetworkProcessorTests.cc index 22575f670..07ca63197 100644 --- a/src/db/unit_tests/dbHierNetworkProcessorTests.cc +++ b/src/db/unit_tests/dbHierNetworkProcessorTests.cc @@ -1270,3 +1270,8 @@ TEST(117_HierClusters) run_hc_test_with_backannotation (_this, "hc_test_l17.gds", "hc_test_au17b.gds"); } +TEST(118_HierClustersMeanderArrays) +{ + run_hc_test (_this, "meander.gds.gz", "meander_au1.gds"); + run_hc_test_with_backannotation (_this, "meander.gds.gz", "meander_au2.gds"); +} From 07a85e3ec3f4b39534de07f2ab352a3c1c9fd254 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Mon, 9 Dec 2019 21:40:24 +0100 Subject: [PATCH 02/21] Added test data. --- testdata/algo/meander_au1.gds | Bin 0 -> 3408 bytes testdata/algo/meander_au2.gds | Bin 0 -> 3058 bytes 2 files changed, 0 insertions(+), 0 deletions(-) create mode 100644 testdata/algo/meander_au1.gds create mode 100644 testdata/algo/meander_au2.gds diff --git a/testdata/algo/meander_au1.gds b/testdata/algo/meander_au1.gds new file mode 100644 index 0000000000000000000000000000000000000000..b541cf80b38e2a90e77d4da397dc5fc886faa1a0 GIT binary patch literal 3408 zcmb7{PiS0K7{$N5_vX%7t9F(1jGr&_x$+47gCx#cTv!2^a+GQ|o`WG7HB(IAS)H*WP;P%E1rs-}vj$d%f4c|Mv88 zYt^f-kqt_Wc%l(Vjf{aoOymS+NUW zb$e!I{xE+<=}WGMdMF6561~HNIrS2;LH+QOHW0B<_r?;q&t?65N8Td5>eGwz5}EboO3WhR?fR5W!i6^O5c`qXK)syo$=*)ak*U3* z^*-v!e(Z^i`Y*kTu1oX|`${O$gJi!G(-qnO`fR)((sg7)?~y0Hv3Kp)K}GDXEGM(Q zLxOklPe*-3oUOH1)LTUF+9y5r7NK-~O7GgcU3rW2`l=tjNM`j`D?;h|6mRb@<@ywF^<+Qx%zU_oy%Xe?BHl&(+NB>Slwy-9fGFZL@UD}R4gSt7lM`Xq1m rW?vHbuD|k}*hu}It^-rN)sy|$m+#rvYZZ~9zE0O|=8gYUio*T{nbrWe literal 0 HcmV?d00001 diff --git a/testdata/algo/meander_au2.gds b/testdata/algo/meander_au2.gds new file mode 100644 index 0000000000000000000000000000000000000000..6c2d9f251d92d2b0c14e03ac51f5f3076574771e GIT binary patch literal 3058 zcmbuBPiRzU6vc1ed-KhkiCS$f1R10vZKqHavS?FUZ0jG4s5A>LX?GQs;KGf9Su_wz z7vn;(i$btM3tc$q#)XSPa3O*WE?jhDz=eWc%to*aA#SwioHut~rpY&(4kW+4ymQYz z=bOo7ELf7vT4OA!KC=y0vv=(S%U1tvc@mBs+H1Bot?c>w;-`o2UwiS{{?6_{e*6BI zH7fDB5W>*|metI{#>B=fY)TA2@8I|Rt<>zp&DPiq?rfUvdRlP7-n_ZHXtrRMZNXR7 zM()T%IQGp9bmMS-oBP7HF^q3$RQBG&9zODS63eikyXx2H%_h56=@#^B?HYJ+BJEF9 zzwK#a+~!2T9-hEfZ2Iq3_o#20GP~TeaIz!%^%{@G;k4m)Tl(><1^s%>+&a6xvF{xF zso3q;Ydre9J#)IHS!C{K@ay&FV!i#8lkF=*r#|el`uR!D_l8c{uQibmzmh)YYln}k zUkP?^#*$CwY(W1#xO)Cn|CRWE=fA-I+M|})5AA~3Q@e=$PUNY*UQ!;>b>Mn= z;YV`*=6p%|o|rBCN&5BmF~9tIQ)eUM?@f9q=iP_I!}T#g^@VQGoBilR!nb~;Q_^){ z%&&f~t9cQ9>%A5A716hTWm$bi>~Ve6@BKEmnbk?=p}&*!^mDonjQQnBkxxXv{6djW zM85o^BA*Cf*GK(+&$T}%IX}}YN&ov3>Mzo-uaEgvZ?#$1MD)~tC+C^Z={hjxr+v8Z zdj~m~3%<3jQzczD!Y@3S)_xKFs$b5lpNRh9pIP-6k<<0DeAUw}`H7gXPRwaur2nO* z!k>hn>tlZ5$0pL_eT76n?RPQ{^Eq7y#{9Go_kFMOFbDI%xB9qK(sd*J!mb>5k&k4K z;}a#B^UtXwH|aVsmT%xgKb&9XNv|Z%PySBs>+g;EWiMOWD?(psEGeIee3dgDfK=@5g-qtL$sbPvrbB-C~}ke`mQQl&&9{4|Cd!zS*@o^%c=mIi0Q}WBEJ> z$#V)TC3&9A=Y)^)kMK+H Yn1i`^?!T^-gs*ZrUFUxIES+WcFSfAL@c;k- literal 0 HcmV?d00001 From 75cb21bbd1b6cce490f5bea98b95552d0c0f0214 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Tue, 10 Dec 2019 23:55:14 +0100 Subject: [PATCH 03/21] WIP: refactoring, first steps. --- src/db/db/dbHierNetworkProcessor.cc | 289 ++++++++++++++++++++++++++-- src/db/db/dbHierNetworkProcessor.h | 3 + src/db/db/dbNetlistExtractor.cc | 1 + 3 files changed, 277 insertions(+), 16 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index fdf8a492e..743e504f5 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1177,19 +1177,16 @@ public: */ void add (const db::Instance *i1, unsigned int /*p1*/, const db::Instance *i2, unsigned int /*p2*/) { - std::list > ic; - - std::vector p; db::ICplxTrans t; - add_pair (box_type::world (), *i1, p, t, *i2, p, t, ic); -#if 1 - // For debugging: ensures the instance properties are configured properly (important for cache consistency) - for (cluster_instance_pair_list_type::const_iterator i = ic.begin (); i != ic.end (); ++i) { - tl_assert (i->first.inst_prop_id () == i1->prop_id ()); - tl_assert (i->second.inst_prop_id () == i2->prop_id ()); + std::list > ic; + consider_instance_pair (box_type::world (), *i1, t, *i2, t, ic); + + // connect_clusters requires propagated cluster ID's + for (std::list >::const_iterator i = ic.begin (); i != ic.end (); ++i) { + ensure_cluster_inst_propagated (i->first, mp_cell->cell_index ()); + ensure_cluster_inst_propagated (i->second, mp_cell->cell_index ()); } -#endif connect_clusters (ic); } @@ -1310,6 +1307,7 @@ private: * @param p2 The instantiation path to the child cell (not including i2) * @param t2 The accumulated transformation of the path, not including i2 */ +#if 1 // @@@ void add_pair (const box_type &common, const db::Instance &i1, const std::vector &p1, const db::ICplxTrans &t1, const db::Instance &i2, const std::vector &p2, const db::ICplxTrans &t2, std::list > &interacting_clusters_out) { if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { @@ -1334,21 +1332,25 @@ private: db::ICplxTrans tt21 = tt1.inverted () * tt2; InstanceToInstanceInteraction ii_key (i1.cell_index (), i1.cell_inst ().delegate (), i2.cell_index (), i2.cell_inst ().delegate (), tt21); +#if 0 // @@@ instance_interaction_cache_type::iterator ii = mp_instance_interaction_cache->find (ii_key); if (ii != mp_instance_interaction_cache->end ()) { // take from cache if possible - db::ICplxTrans ic_trans = tt1 * ii->second.first.inverted (); + --> problem: cluster pairs need to be relative to the initial cell, hence we can't cache the target cluster. only the source one!!! for (cluster_instance_pair_list_type::const_iterator ic = ii->second.second.begin (); ic != ii->second.second.end (); ++ic) { - interacting_clusters_out.push_back (*ic); - interacting_clusters_out.back ().first.transform (ic_trans); - interacting_clusters_out.back ().second.transform (ic_trans); + interacting_clusters_out.push_back (std::pair ()); + interacting_clusters_out.back ().first = make_path (ic->first.id (), p1); + interacting_clusters_out.back ().second = make_path (ic->second.id (), p2); } return; } - std::list > &interacting_clusters = mp_instance_interaction_cache->insert (std::make_pair (ii_key, std::make_pair (tt1, cluster_instance_pair_list_type ()))).first->second.second; - if (i1.size () == 1 && i2.size () == 1) { +#endif + + std::list > interacting_clusters; // @@@ + + if (false /*@@@*/&& i1.size () == 1 && i2.size () == 1) { // single-to-single instance interactions @@ -1448,6 +1450,124 @@ private: interacting_clusters_out.insert (interacting_clusters_out.end (), interacting_clusters.begin (), interacting_clusters.end ()); } +#endif + + /** + * @brief Investigate a pair of instances + * + * @param common The common box of both instances + * @param i1 The first instance to investigate + * @param ci1 The parent cell index of i1 + * @param p1 The parent instances property ID of i1 space + * @param t1 The parent instances culmulated transformation + * @param i2 The second instance to investiage + * @param ci2 The parent cell index of i2 + * @param p2 The parent instances property ID of i2 space + * @param t2 The parent instances culmulated transformation + * @param interacting_clusters_out Receives the cluster interaction descriptors + * + * "interacting_clusters_out" will be cluster interactions in the parent instance space of i1 and i2 respectively. + * Cluster ID will be valid in the parent cells containing i1 and i2 and the cluster instances property ID will be set to p1 and p2 + * respectively. + */ + void consider_instance_pair (const box_type &common, + const db::Instance &i1, const db::ICplxTrans &t1, + const db::Instance &i2, const db::ICplxTrans &t2, + std::list > &interacting_clusters_out) + { + if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { + return; + } + + box_type bb1 = (*mp_cbc) (i1.cell_index ()); + box_type b1 = i1.cell_inst ().bbox (*mp_cbc).transformed (t1); + + box_type bb2 = (*mp_cbc) (i2.cell_index ()); + box_type b2 = i2.cell_inst ().bbox (*mp_cbc).transformed (t2); + + box_type common_all = common & b1 & b2; + + if (common_all.empty ()) { + return; + } + + db::ICplxTrans tt2 = t2 * i2.complex_trans (); + db::ICplxTrans tt1 = t1 * i1.complex_trans (); + + db::ICplxTrans tt21 = tt1.inverted () * tt2; + + // array interactions + + db::ICplxTrans t1i = t1.inverted (); + db::ICplxTrans t2i = t2.inverted (); + + std::list > ii_interactions; + + for (db::CellInstArray::iterator ii1 = i1.begin_touching (common_all.transformed (t1i), mp_layout); ! ii1.at_end (); ++ii1) { + + db::ICplxTrans i1t = i1.complex_trans (*ii1); + db::ICplxTrans tt1 = t1 * i1t; + box_type ib1 = bb1.transformed (tt1); + + for (db::CellInstArray::iterator ii2 = i2.begin_touching (ib1.transformed (t2i), mp_layout); ! ii2.at_end (); ++ii2) { + + db::ICplxTrans i2t = i2.complex_trans (*ii2); + db::ICplxTrans tt2 = t2 * i2t; + if (i1.cell_index () == i2.cell_index () && tt1 == tt2) { + // skip interactions between identical instances (duplicate instance removal) + continue; + } + + box_type ib2 = bb2.transformed (tt2); + + box_type common12 = ib1 & ib2 & common; + if (! common12.empty ()) { + + const std::vector > &i2i_interactions = compute_instance_interactions (common12, i1.cell_index (), tt1, i2.cell_index (), tt2); + + for (std::vector >::const_iterator ii = i2i_interactions.begin (); ii != i2i_interactions.end (); ++ii) { + ClusterInstance k1 (ii->first, i1.cell_index (), i1t, i1.prop_id ()); + ClusterInstance k2 (ii->second, i2.cell_index (), i2t, i2.prop_id ()); + interacting_clusters_out.push_back (std::make_pair (k1, k2)); + } + + // dive into cell of ii2 + const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); + for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common12.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { + + consider_instance_pair (common12, i1, t1, *jj2, tt2, ii_interactions); + + for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { + propagate_cluster_inst (i->second, i2.cell_index (), i2t, i2.prop_id ()); + } + interacting_clusters_out.splice (interacting_clusters_out.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); + + } + + } + + } + + box_type common1 = ib1 & b2 & common; + if (! common1.empty ()) { + + // dive into cell of ii1 + const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); + for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common1.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { + + consider_instance_pair (common1, *jj1, tt1, i2, t2, ii_interactions); + + for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { + propagate_cluster_inst (i->first, i1.cell_index (), i1t, i1.prop_id ()); + } + interacting_clusters_out.splice (interacting_clusters_out.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); + + } + + } + + } + } /** * @brief Handles the cluster interactions between two specific instances @@ -1529,6 +1649,62 @@ private: } } + const std::vector > & + compute_instance_interactions (const box_type &common, + db::cell_index_type ci1, const db::ICplxTrans &t1, + db::cell_index_type ci2, const db::ICplxTrans &t2) + { + if (is_breakout_cell (mp_breakout_cells, ci1) || is_breakout_cell (mp_breakout_cells, ci2)) { + static const std::vector > empty; + return empty; + } + + db::ICplxTrans t1i = t1.inverted (); + db::ICplxTrans t2i = t2.inverted (); + db::ICplxTrans t21 = t1i * t2; + + box_type common2 = common.transformed (t2i); + + InteractionKeyForClustersType ikey (ci1, ci2, t21, common2); + + typename std::map > >::const_iterator ici = m_interaction_cache_for_clusters.find (ikey); + if (ici != m_interaction_cache_for_clusters.end ()) { + + return ici->second; + + } else { + + const db::Cell &cell2 = mp_layout->cell (ci2); + + const db::local_clusters &cl1 = mp_tree->clusters_per_cell (ci1); + const db::local_clusters &cl2 = mp_tree->clusters_per_cell (ci2); + + std::vector > &new_interactions = m_interaction_cache_for_clusters [ikey]; + db::ICplxTrans t12 = t2i * t1; + + for (typename db::local_clusters::touching_iterator i = cl1.begin_touching (common2.transformed (t21)); ! i.at_end (); ++i) { + + // skip the test, if this cluster doesn't interact with the whole cell2 + if (! i->interacts (cell2, t21, *mp_conn)) { + continue; + } + + box_type bc2 = (common2 & i->bbox ().transformed (t12)); + for (typename db::local_clusters::touching_iterator j = cl2.begin_touching (bc2); ! j.at_end (); ++j) { + + if (i->interacts (*j, t21, *mp_conn)) { + new_interactions.push_back (std::make_pair (i->id (), j->id ())); + } + + } + + } + + return new_interactions; + + } + } + /** * @brief Single instance treatment */ @@ -1763,6 +1939,19 @@ private: return mp_tree->make_path (*mp_layout, *mp_cell, id, path); } + // @@@ + void propagate_cluster_inst (ClusterInstance &ci, db::cell_index_type pci, const db::ICplxTrans &trans, db::properties_id_type prop_id) const + { + size_t id_new = mp_tree->propagate_cluster_inst (*mp_layout, ci, pci); + ci = db::ClusterInstance (id_new, pci, trans, prop_id); + } + + // @@@ + void ensure_cluster_inst_propagated (const ClusterInstance &ci, db::cell_index_type pci) const + { + mp_tree->propagate_cluster_inst (*mp_layout, ci, pci); + } + /** * @brief Establishes connections between the cluster instances listed in the argument */ @@ -1773,6 +1962,7 @@ private: ClusterInstance k1 = ic->first; ClusterInstance k2 = ic->second; + // @@@ if (ic_trans) { k1.transform (*ic_trans); k1.set_inst_prop_id (prop_id1); @@ -1839,6 +2029,73 @@ private: } +template +size_t +hier_clusters::propagate_cluster_inst (const db::Layout &layout, const ClusterInstance &ci, db::cell_index_type pci) +{ + connected_clusters &target_cc = clusters_per_cell (pci); + size_t parent_cluster = target_cc.find_cluster_with_connection (ci); + + size_t id_new = 0; + + if (parent_cluster > 0) { + + // taken parent + id_new = parent_cluster; + + } else { + + size_t id = ci.id (); + + // if we're attaching to a child which is root yet, we need to promote the + // cluster to the parent in all places + connected_clusters &child_cc = clusters_per_cell (ci.inst_cell_index ()); + tl_assert (child_cc.is_root (id)); + + std::set > seen; // to avoid duplicate connections + + const db::Cell &child_cell = layout.cell (ci.inst_cell_index ()); + for (db::Cell::parent_inst_iterator pi = child_cell.begin_parent_insts (); ! pi.at_end (); ++pi) { + + db::Instance child_inst = pi->child_inst (); + + connected_clusters &parent_cc = clusters_per_cell (pi->parent_cell_index ()); + for (db::CellInstArray::iterator pii = child_inst.begin (); ! pii.at_end (); ++pii) { + + ClusterInstance ci2 (id, child_inst.cell_index (), child_inst.complex_trans (*pii), child_inst.prop_id ()); + if (seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { + + size_t id_dummy; + + const typename db::local_cluster::global_nets &gn = child_cc.cluster_by_id (id).get_global_nets (); + if (gn.empty ()) { + id_dummy = parent_cc.insert_dummy (); + } else { + local_cluster *lc = parent_cc.insert (); + lc->set_global_nets (gn); + id_dummy = lc->id (); + } + + parent_cc.add_connection (id_dummy, ci2); + seen.insert (std::make_pair (pi->parent_cell_index (), ci2)); + + if (pci == pi->parent_cell_index () && ci == ci2) { + id_new = id_dummy; + } + + } + + } + + } + + child_cc.reset_root (id); + + } + + return id_new; +} + template ClusterInstance hier_clusters::make_path (const db::Layout &layout, const db::Cell &cell, size_t id, const std::vector &path) diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 3c90dafdb..94c310bbc 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -1007,6 +1007,9 @@ public: */ ClusterInstance make_path (const db::Layout &layout, const db::Cell &cell, size_t id, const std::vector &path); + // @@@ + size_t propagate_cluster_inst (const db::Layout &layout, const ClusterInstance &ci, db::cell_index_type pci); + private: void build_local_cluster (const db::Layout &layout, const db::Cell &cell, db::ShapeIterator::flags_type shape_flags, const db::Connectivity &conn, const tl::equivalence_clusters *attr_equivalence); void build_hier_connections (cell_clusters_box_converter &cbc, const db::Layout &layout, const db::Cell &cell, const db::Connectivity &conn, const std::set *breakout_cells, instance_interaction_cache_type &instance_interaction_cache); diff --git a/src/db/db/dbNetlistExtractor.cc b/src/db/db/dbNetlistExtractor.cc index 481dda8cb..7dcebd9d7 100644 --- a/src/db/db/dbNetlistExtractor.cc +++ b/src/db/db/dbNetlistExtractor.cc @@ -159,6 +159,7 @@ NetlistExtractor::extract_nets (const db::DeepShapeStore &dss, unsigned int layo // Make sure we create one subcircuit for each instance of cells which do have circuits // associated. for (db::Cell::const_iterator inst = cell.begin (); ! inst.at_end (); ++inst) { + // @@@ ARRAY EXPANSION!!! make_subcircuit (circuit, inst->cell_index (), inst->complex_trans (), subcircuits, circuits); } From 406bc226bb76a37e079eeee9201d52c0b360cd69 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Wed, 11 Dec 2019 00:39:46 +0100 Subject: [PATCH 04/21] WIP: refactoring --- src/db/db/dbHierNetworkProcessor.cc | 52 ++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 12 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 743e504f5..c6b7006d6 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1457,13 +1457,9 @@ private: * * @param common The common box of both instances * @param i1 The first instance to investigate - * @param ci1 The parent cell index of i1 - * @param p1 The parent instances property ID of i1 space - * @param t1 The parent instances culmulated transformation + * @param t1 The parent instances' culmulated transformation * @param i2 The second instance to investiage - * @param ci2 The parent cell index of i2 - * @param p2 The parent instances property ID of i2 space - * @param t2 The parent instances culmulated transformation + * @param t2 The parent instances' culmulated transformation * @param interacting_clusters_out Receives the cluster interaction descriptors * * "interacting_clusters_out" will be cluster interactions in the parent instance space of i1 and i2 respectively. @@ -1473,7 +1469,7 @@ private: void consider_instance_pair (const box_type &common, const db::Instance &i1, const db::ICplxTrans &t1, const db::Instance &i2, const db::ICplxTrans &t2, - std::list > &interacting_clusters_out) + std::list > &interacting_clusters) { if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { return; @@ -1491,10 +1487,31 @@ private: return; } - db::ICplxTrans tt2 = t2 * i2.complex_trans (); - db::ICplxTrans tt1 = t1 * i1.complex_trans (); + db::ICplxTrans i1t = i1.complex_trans (); + db::ICplxTrans tt1 = t1 * i1t; + + db::ICplxTrans i2t = i2.complex_trans (); + db::ICplxTrans tt2 = t2 * i2t; db::ICplxTrans tt21 = tt1.inverted () * tt2; + InstanceToInstanceInteraction ii_key (i1.cell_index (), i1.cell_inst ().delegate (), i2.cell_index (), i2.cell_inst ().delegate (), tt21); + + instance_interaction_cache_type::iterator ii = mp_instance_interaction_cache->find (ii_key); + if (ii != mp_instance_interaction_cache->end ()) { + + // use cached interactions + interacting_clusters = ii->second.second; + for (std::list >::iterator i = interacting_clusters.begin (); i != interacting_clusters.end (); ++i) { + // translate the property IDs + i->first.set_inst_prop_id (i1.prop_id ()); + i->first.transform (i1t); + i->second.set_inst_prop_id (i2.prop_id ()); + i->second.transform (i2t); + } + + return; + + } // array interactions @@ -1528,7 +1545,7 @@ private: for (std::vector >::const_iterator ii = i2i_interactions.begin (); ii != i2i_interactions.end (); ++ii) { ClusterInstance k1 (ii->first, i1.cell_index (), i1t, i1.prop_id ()); ClusterInstance k2 (ii->second, i2.cell_index (), i2t, i2.prop_id ()); - interacting_clusters_out.push_back (std::make_pair (k1, k2)); + interacting_clusters.push_back (std::make_pair (k1, k2)); } // dive into cell of ii2 @@ -1540,7 +1557,7 @@ private: for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { propagate_cluster_inst (i->second, i2.cell_index (), i2t, i2.prop_id ()); } - interacting_clusters_out.splice (interacting_clusters_out.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); + interacting_clusters.splice (interacting_clusters.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); } @@ -1560,13 +1577,24 @@ private: for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { propagate_cluster_inst (i->first, i1.cell_index (), i1t, i1.prop_id ()); } - interacting_clusters_out.splice (interacting_clusters_out.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); + interacting_clusters.splice (interacting_clusters.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); } } } + + std::pair &cached = (*mp_instance_interaction_cache) [ii_key]; + cached.first = i1.complex_trans (); // @@@ remove or twofold transformation + cached.second = interacting_clusters; + + // normalize transformations in cache + db::ICplxTrans i1ti = i1t.inverted (), i2ti = i2t.inverted (); + for (std::list >::iterator i = cached.second.begin (); i != cached.second.end (); ++i) { + i->first.transform (i1ti); + i->second.transform (i2ti); + } } /** From fee54728457dad823601e9189f36f3df6503de4c Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Wed, 11 Dec 2019 01:28:56 +0100 Subject: [PATCH 05/21] WIP: further refactoring. --- src/db/db/dbHierNetworkProcessor.cc | 80 ++++++++++++++++++----------- src/db/db/dbHierNetworkProcessor.h | 2 +- 2 files changed, 52 insertions(+), 30 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index c6b7006d6..9829b59bf 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1779,13 +1779,32 @@ private: // dive into cell of ii2 - this is a self-interaction of a cell with parts of itself // as these self-interactions are expected to be the same always (regular array), we can skip this test the next times. if (first) { + for (db::Cell::touching_iterator jj2 = cell.begin_touching (common.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - std::vector p; + db::ICplxTrans t; - add_pair (common, i, p, t, *jj2, pp2, tt2, interacting_clusters); + + // @@@ add_pair (common, i, p, t, *jj2, pp2, tt2, interacting_clusters); // @@@ consider_interactions + std::list > ii_interactions; + consider_instance_pair (common, i, t, *jj2, tt2, ii_interactions); // @@@ + + for (std::list >::iterator ii = ii_interactions.begin (); ii != ii_interactions.end (); ++ii) { + propagate_cluster_inst (ii->second, i.cell_index (), tt2, i.prop_id ()); + } + interacting_clusters.splice (interacting_clusters.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); + } + } + // @@@ + // connect_clusters requires propagated cluster ID's + for (std::list >::const_iterator i = interacting_clusters.begin (); i != interacting_clusters.end (); ++i) { + ensure_cluster_inst_propagated (i->first, mp_cell->cell_index ()); + ensure_cluster_inst_propagated (i->second, mp_cell->cell_index ()); + } + // @@@ + connect_clusters (interacting_clusters); any = true; @@ -1970,14 +1989,15 @@ private: // @@@ void propagate_cluster_inst (ClusterInstance &ci, db::cell_index_type pci, const db::ICplxTrans &trans, db::properties_id_type prop_id) const { - size_t id_new = mp_tree->propagate_cluster_inst (*mp_layout, ci, pci); + size_t id_new = mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ci, pci); + tl_assert (id_new != 0); ci = db::ClusterInstance (id_new, pci, trans, prop_id); } // @@@ void ensure_cluster_inst_propagated (const ClusterInstance &ci, db::cell_index_type pci) const { - mp_tree->propagate_cluster_inst (*mp_layout, ci, pci); + mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ci, pci); } /** @@ -2059,7 +2079,7 @@ private: template size_t -hier_clusters::propagate_cluster_inst (const db::Layout &layout, const ClusterInstance &ci, db::cell_index_type pci) +hier_clusters::propagate_cluster_inst (const db::Layout &layout, const db::Cell &cell, const ClusterInstance &ci, db::cell_index_type pci) { connected_clusters &target_cc = clusters_per_cell (pci); size_t parent_cluster = target_cc.find_cluster_with_connection (ci); @@ -2078,46 +2098,48 @@ hier_clusters::propagate_cluster_inst (const db::Layout &layout, const Cluste // if we're attaching to a child which is root yet, we need to promote the // cluster to the parent in all places connected_clusters &child_cc = clusters_per_cell (ci.inst_cell_index ()); - tl_assert (child_cc.is_root (id)); + if (child_cc.is_root (id)) { - std::set > seen; // to avoid duplicate connections + std::set > seen; // to avoid duplicate connections - const db::Cell &child_cell = layout.cell (ci.inst_cell_index ()); - for (db::Cell::parent_inst_iterator pi = child_cell.begin_parent_insts (); ! pi.at_end (); ++pi) { + const db::Cell &child_cell = layout.cell (ci.inst_cell_index ()); + for (db::Cell::parent_inst_iterator pi = child_cell.begin_parent_insts (); ! pi.at_end (); ++pi) { - db::Instance child_inst = pi->child_inst (); + db::Instance child_inst = pi->child_inst (); - connected_clusters &parent_cc = clusters_per_cell (pi->parent_cell_index ()); - for (db::CellInstArray::iterator pii = child_inst.begin (); ! pii.at_end (); ++pii) { + connected_clusters &parent_cc = clusters_per_cell (pi->parent_cell_index ()); + for (db::CellInstArray::iterator pii = child_inst.begin (); ! pii.at_end (); ++pii) { - ClusterInstance ci2 (id, child_inst.cell_index (), child_inst.complex_trans (*pii), child_inst.prop_id ()); - if (seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { + ClusterInstance ci2 (id, child_inst.cell_index (), child_inst.complex_trans (*pii), child_inst.prop_id ()); + if ((cell.cell_index () != pi->parent_cell_index () || ci != ci2) && seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { - size_t id_dummy; + size_t id_dummy; - const typename db::local_cluster::global_nets &gn = child_cc.cluster_by_id (id).get_global_nets (); - if (gn.empty ()) { - id_dummy = parent_cc.insert_dummy (); - } else { - local_cluster *lc = parent_cc.insert (); - lc->set_global_nets (gn); - id_dummy = lc->id (); - } + const typename db::local_cluster::global_nets &gn = child_cc.cluster_by_id (id).get_global_nets (); + if (gn.empty ()) { + id_dummy = parent_cc.insert_dummy (); + } else { + local_cluster *lc = parent_cc.insert (); + lc->set_global_nets (gn); + id_dummy = lc->id (); + } - parent_cc.add_connection (id_dummy, ci2); - seen.insert (std::make_pair (pi->parent_cell_index (), ci2)); + parent_cc.add_connection (id_dummy, ci2); + seen.insert (std::make_pair (pi->parent_cell_index (), ci2)); + + if (pci == pi->parent_cell_index () && ci == ci2) { + id_new = id_dummy; + } - if (pci == pi->parent_cell_index () && ci == ci2) { - id_new = id_dummy; } } } - } + child_cc.reset_root (id); - child_cc.reset_root (id); + } } diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 94c310bbc..f4237c512 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -1008,7 +1008,7 @@ public: ClusterInstance make_path (const db::Layout &layout, const db::Cell &cell, size_t id, const std::vector &path); // @@@ - size_t propagate_cluster_inst (const db::Layout &layout, const ClusterInstance &ci, db::cell_index_type pci); + size_t propagate_cluster_inst (const db::Layout &layout, const Cell &cell, const ClusterInstance &ci, db::cell_index_type pci); private: void build_local_cluster (const db::Layout &layout, const db::Cell &cell, db::ShapeIterator::flags_type shape_flags, const db::Connectivity &conn, const tl::equivalence_clusters *attr_equivalence); From e11aaf4ac202359d4d0d38d9614860cf82776436 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Wed, 11 Dec 2019 23:35:19 +0100 Subject: [PATCH 06/21] WIP: Continued rework. --- src/db/db/dbHierNetworkProcessor.cc | 81 +++++++++++++++++------------ 1 file changed, 49 insertions(+), 32 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 9829b59bf..89315b124 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1154,13 +1154,12 @@ public: struct ClusterInstanceInteraction { - ClusterInstanceInteraction (size_t _cluster_id, size_t _other_cluster_id, const std::vector &_other_path) - : cluster_id (_cluster_id), other_cluster_id (_other_cluster_id), other_path (_other_path) + ClusterInstanceInteraction (size_t _cluster_id, const ClusterInstance &_other_ci) + : cluster_id (_cluster_id), other_ci (_other_ci) { } size_t cluster_id; - size_t other_cluster_id; - std::vector other_path; + ClusterInstance other_ci; }; /** @@ -1182,11 +1181,13 @@ public: std::list > ic; consider_instance_pair (box_type::world (), *i1, t, *i2, t, ic); + // @@@ move to connect_clusters // connect_clusters requires propagated cluster ID's for (std::list >::const_iterator i = ic.begin (); i != ic.end (); ++i) { ensure_cluster_inst_propagated (i->first, mp_cell->cell_index ()); ensure_cluster_inst_propagated (i->second, mp_cell->cell_index ()); } + // @@@ connect_clusters (ic); } @@ -1204,9 +1205,16 @@ public: */ void add (const local_cluster *c1, unsigned int /*p1*/, const db::Instance *i2, unsigned int /*p2*/) { - std::vector p; + std::list ic; + db::ICplxTrans t; - add_pair (*c1, *i2, p, t); + consider_cluster_instance_pair (*c1, *i2, t, ic); + + for (typename std::list::const_iterator i = ic.begin (); i != ic.end (); ++i) { + ensure_cluster_inst_propagated (i->other_ci, mp_cell->cell_index ()); + } + + m_ci_interactions.splice (m_ci_interactions.end (), ic, ic.begin (), ic.end ()); } /** @@ -1219,9 +1227,7 @@ public: { for (typename std::list::const_iterator ii = m_ci_interactions.begin (); ii != m_ci_interactions.end (); ++ii) { - ClusterInstance other_key = make_path (ii->other_cluster_id, ii->other_path); - - id_type other = mp_cell_clusters->find_cluster_with_connection (other_key); + id_type other = mp_cell_clusters->find_cluster_with_connection (ii->other_ci); if (other > 0) { // we found a child cluster that connects two clusters on our own level: @@ -1230,7 +1236,7 @@ public: mark_to_join (other, ii->cluster_id); } else { - mp_cell_clusters->add_connection (ii->cluster_id, other_key); + mp_cell_clusters->add_connection (ii->cluster_id, ii->other_ci); } } @@ -1297,6 +1303,7 @@ private: std::map > > m_interaction_cache_for_clusters; instance_interaction_cache_type *mp_instance_interaction_cache; +#if 0 // @@@ /** * @brief Handles the cluster interactions between two instances or instance arrays * @param common The region under investigation (seen from the top level) @@ -1307,7 +1314,6 @@ private: * @param p2 The instantiation path to the child cell (not including i2) * @param t2 The accumulated transformation of the path, not including i2 */ -#if 1 // @@@ void add_pair (const box_type &common, const db::Instance &i1, const std::vector &p1, const db::ICplxTrans &t1, const db::Instance &i2, const std::vector &p2, const db::ICplxTrans &t2, std::list > &interacting_clusters_out) { if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { @@ -1520,6 +1526,7 @@ private: std::list > ii_interactions; + // @@@ optimize for single inst? for (db::CellInstArray::iterator ii1 = i1.begin_touching (common_all.transformed (t1i), mp_layout); ! ii1.at_end (); ++ii1) { db::ICplxTrans i1t = i1.complex_trans (*ii1); @@ -1607,6 +1614,7 @@ private: * @param p2 The instantiation path to the child cell (last element is the instance to ci2) * @param t2 The accumulated transformation of the path p2 */ + // @@@ remove void add_single_pair (const box_type &common, db::cell_index_type ci1, const std::vector &p1, const db::ICplxTrans &t1, db::cell_index_type ci2, const std::vector &p2, const db::ICplxTrans &t2, @@ -1774,6 +1782,7 @@ private: cluster_instance_pair_list_type interacting_clusters; box_type common = (ib & ib2); + // @@@ replace: add_single_pair (common, i.cell_index (), pp, tt, i.cell_index (), pp2, tt2, interacting_clusters); // dive into cell of ii2 - this is a self-interaction of a cell with parts of itself @@ -1784,9 +1793,8 @@ private: db::ICplxTrans t; - // @@@ add_pair (common, i, p, t, *jj2, pp2, tt2, interacting_clusters); // @@@ consider_interactions std::list > ii_interactions; - consider_instance_pair (common, i, t, *jj2, tt2, ii_interactions); // @@@ + consider_instance_pair (common, i, t, *jj2, tt2, ii_interactions); for (std::list >::iterator ii = ii_interactions.begin (); ii != ii_interactions.end (); ++ii) { propagate_cluster_inst (ii->second, i.cell_index (), tt2, i.prop_id ()); @@ -1797,7 +1805,7 @@ private: } - // @@@ + // @@@ move to connect_clusters: // connect_clusters requires propagated cluster ID's for (std::list >::const_iterator i = interacting_clusters.begin (); i != interacting_clusters.end (); ++i) { ensure_cluster_inst_propagated (i->first, mp_cell->cell_index ()); @@ -1827,46 +1835,55 @@ private: * @brief Handles a local clusters vs. the clusters of a specific child instance or instance array * @param c1 The local cluster * @param i2 The index of the child cell - * @param p2 The instantiation path to the child cell (not including i2) * @param t2 The accumulated transformation of the path, not including i2 + * @param interactions_out Delivers the interactions */ - void add_pair (const local_cluster &c1, const db::Instance &i2, const std::vector &p2, const db::ICplxTrans &t2) + void consider_cluster_instance_pair (const local_cluster &c1, const db::Instance &i2, const db::ICplxTrans &t2, std::list &interactions_out) { if (is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { return; } - box_type b1 = c1.bbox (); - box_type bb2 = (*mp_cbc) (i2.cell_index ()); const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); + box_type b1 = c1.bbox (); box_type b2 = i2.cell_inst ().bbox (*mp_cbc).transformed (t2); if (! b1.touches (b2)) { return; } - std::vector pp2; - pp2.reserve (p2.size () + 1); - pp2.insert (pp2.end (), p2.begin (), p2.end ()); - pp2.push_back (ClusterInstElement ()); + std::vector > c2i_interactions; for (db::CellInstArray::iterator ii2 = i2.begin_touching ((b1 & b2).transformed (t2.inverted ()), mp_layout); ! ii2.at_end (); ++ii2) { - db::ICplxTrans tt2 = t2 * i2.complex_trans (*ii2); + db::ICplxTrans i2t = i2.complex_trans (*ii2); + db::ICplxTrans tt2 = t2 * i2t; box_type ib2 = bb2.transformed (tt2); if (b1.touches (ib2) && c1.interacts (cell2, tt2, *mp_conn)) { - pp2.back () = ClusterInstElement (i2.cell_index (), i2.complex_trans (*ii2), i2.prop_id ()); + c2i_interactions.clear (); + compute_cluster_instance_interactions (c1, i2.cell_index (), tt2, c2i_interactions); - add_single_pair (c1, i2.cell_index (), pp2, tt2); + for (std::vector >::const_iterator ii = c2i_interactions.begin (); ii != c2i_interactions.end (); ++ii) { + ClusterInstance k (ii->second, i2.cell_index (), i2t, i2.prop_id ()); + interactions_out.push_back (ClusterInstanceInteraction (ii->first, k)); + } // dive into cell of ii2 for (db::Cell::touching_iterator jj2 = cell2.begin_touching ((b1 & ib2).transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - add_pair (c1, *jj2, pp2, tt2); + + std::list ci_interactions; + consider_cluster_instance_pair (c1, *jj2, tt2, ci_interactions); + + for (typename std::list::iterator ii = ci_interactions.begin (); ii != ci_interactions.end (); ++ii) { + propagate_cluster_inst (ii->other_ci, i2.cell_index (), i2t, i2.prop_id ()); + } + interactions_out.splice (interactions_out.end (), ci_interactions, ci_interactions.begin (), ci_interactions.end ()); + } } @@ -1881,22 +1898,21 @@ private: * @param p2 The instantiation path to the child cell (last element is the instance to ci2) * @param t2 The accumulated transformation of the path */ - void add_single_pair (const local_cluster &c1, - db::cell_index_type ci2, const std::vector &p2, const db::ICplxTrans &t2) + void + compute_cluster_instance_interactions (const local_cluster &c1, + db::cell_index_type ci2, const db::ICplxTrans &t2, + std::vector > &interactions) { if (is_breakout_cell (mp_breakout_cells, ci2)) { return; } - // NOTE: make_path may disturb the iteration (because of modification), hence - // we first collect and then process the interactions. - const db::local_clusters &cl2 = mp_tree->clusters_per_cell (ci2); for (typename db::local_clusters::touching_iterator j = cl2.begin_touching (c1.bbox ().transformed (t2.inverted ())); ! j.at_end (); ++j) { if (c1.interacts (*j, t2, *mp_conn)) { - m_ci_interactions.push_back (ClusterInstanceInteraction (c1.id (), j->id (), p2)); + interactions.push_back (std::make_pair (c1.id (), j->id ())); } } @@ -1981,6 +1997,7 @@ private: * Cluster connections can only cross one level of hierarchy. This method * creates necessary dummy entries for the given path. */ + // @@@ remove ClusterInstance make_path (id_type id, const std::vector &path) const { return mp_tree->make_path (*mp_layout, *mp_cell, id, path); From 1f5ec9d3e940c791f045e9a17eed9289c57b8adb Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Thu, 12 Dec 2019 00:20:15 +0100 Subject: [PATCH 07/21] Bugfix: don't mess with the hier cluster structure while determining the interactions ... --- src/db/db/dbHierNetworkProcessor.cc | 8 ++++---- src/db/db/dbHierNetworkProcessor.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 89315b124..fd299da08 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1210,10 +1210,6 @@ public: db::ICplxTrans t; consider_cluster_instance_pair (*c1, *i2, t, ic); - for (typename std::list::const_iterator i = ic.begin (); i != ic.end (); ++i) { - ensure_cluster_inst_propagated (i->other_ci, mp_cell->cell_index ()); - } - m_ci_interactions.splice (m_ci_interactions.end (), ic, ic.begin (), ic.end ()); } @@ -1225,6 +1221,10 @@ public: */ void finish_cluster_to_instance_interactions () { + for (typename std::list::const_iterator ii = m_ci_interactions.begin (); ii != m_ci_interactions.end (); ++ii) { + ensure_cluster_inst_propagated (ii->other_ci, mp_cell->cell_index ()); + } + for (typename std::list::const_iterator ii = m_ci_interactions.begin (); ii != m_ci_interactions.end (); ++ii) { id_type other = mp_cell_clusters->find_cluster_with_connection (ii->other_ci); diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index f4237c512..322563013 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -201,7 +201,7 @@ private: * of a given connectivity. The shapes will still be organised in layers. */ template -class DB_PUBLIC local_cluster +class DB_PUBLIC_TEMPLATE local_cluster { public: typedef size_t id_type; @@ -395,7 +395,7 @@ private: * @brief A box converter for the local_cluster class */ template -struct DB_PUBLIC local_cluster_box_convert +struct DB_PUBLIC_TEMPLATE local_cluster_box_convert { typedef typename local_cluster::box_type box_type; typedef typename db::simple_bbox_tag complexity; @@ -414,7 +414,7 @@ struct DB_PUBLIC local_cluster_box_convert * the clusters from a cell's shapes. */ template -class DB_PUBLIC local_clusters +class DB_PUBLIC_TEMPLATE local_clusters { public: typedef typename local_cluster::id_type id_type; @@ -786,7 +786,7 @@ template class connected_clusters; * @brief An iterator delivering all clusters of a connected_clusters set */ template -class DB_PUBLIC connected_clusters_iterator +class DB_PUBLIC_TEMPLATE connected_clusters_iterator { public: typedef typename local_cluster::id_type value_type; @@ -834,7 +834,7 @@ private: * "half connected" clusters. */ template -class DB_PUBLIC connected_clusters +class DB_PUBLIC_TEMPLATE connected_clusters : public local_clusters { public: @@ -947,7 +947,7 @@ template class cell_clusters_box_converter; * Hierarchical clusters */ template -class DB_PUBLIC hier_clusters +class DB_PUBLIC_TEMPLATE hier_clusters : public tl::Object { public: @@ -1029,7 +1029,7 @@ private: * This iterator applies to one layer. */ template -class DB_PUBLIC recursive_cluster_shape_iterator +class DB_PUBLIC_TEMPLATE recursive_cluster_shape_iterator { public: typedef T value_type; @@ -1132,7 +1132,7 @@ private: * This iterator will deliver the child clusters of a specific cluster. */ template -class DB_PUBLIC recursive_cluster_iterator +class DB_PUBLIC_TEMPLATE recursive_cluster_iterator { public: /** From 1e5d02b1bc1d1b084c8aab0ab0e3a41409dd87e9 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sat, 14 Dec 2019 18:58:22 +0100 Subject: [PATCH 08/21] WIP: refactoring of cell instance interactions for net extraction. --- src/db/db/dbHierNetworkProcessor.cc | 101 +++++++++++----------------- src/db/db/dbHierNetworkProcessor.h | 2 +- 2 files changed, 41 insertions(+), 62 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index fd299da08..f809dec86 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1179,15 +1179,7 @@ public: db::ICplxTrans t; std::list > ic; - consider_instance_pair (box_type::world (), *i1, t, *i2, t, ic); - - // @@@ move to connect_clusters - // connect_clusters requires propagated cluster ID's - for (std::list >::const_iterator i = ic.begin (); i != ic.end (); ++i) { - ensure_cluster_inst_propagated (i->first, mp_cell->cell_index ()); - ensure_cluster_inst_propagated (i->second, mp_cell->cell_index ()); - } - // @@@ + consider_instance_pair (box_type::world (), *i1, t, db::CellInstArray::iterator (), *i2, t, db::CellInstArray::iterator (), ic); connect_clusters (ic); } @@ -1222,7 +1214,7 @@ public: void finish_cluster_to_instance_interactions () { for (typename std::list::const_iterator ii = m_ci_interactions.begin (); ii != m_ci_interactions.end (); ++ii) { - ensure_cluster_inst_propagated (ii->other_ci, mp_cell->cell_index ()); + mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ii->other_ci, mp_cell->cell_index (), false); } for (typename std::list::const_iterator ii = m_ci_interactions.begin (); ii != m_ci_interactions.end (); ++ii) { @@ -1464,8 +1456,10 @@ private: * @param common The common box of both instances * @param i1 The first instance to investigate * @param t1 The parent instances' culmulated transformation + * @param i1element selects a specific instance from i1 (unless == db::CellInstArray::iterator()) * @param i2 The second instance to investiage * @param t2 The parent instances' culmulated transformation + * @param i2element selects a specific instance from i2 (unless == db::CellInstArray::iterator()) * @param interacting_clusters_out Receives the cluster interaction descriptors * * "interacting_clusters_out" will be cluster interactions in the parent instance space of i1 and i2 respectively. @@ -1473,8 +1467,8 @@ private: * respectively. */ void consider_instance_pair (const box_type &common, - const db::Instance &i1, const db::ICplxTrans &t1, - const db::Instance &i2, const db::ICplxTrans &t2, + const db::Instance &i1, const db::ICplxTrans &t1, const db::CellInstArray::iterator &i1element, + const db::Instance &i2, const db::ICplxTrans &t2, const db::CellInstArray::iterator &i2element, std::list > &interacting_clusters) { if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { @@ -1527,13 +1521,13 @@ private: std::list > ii_interactions; // @@@ optimize for single inst? - for (db::CellInstArray::iterator ii1 = i1.begin_touching (common_all.transformed (t1i), mp_layout); ! ii1.at_end (); ++ii1) { + for (db::CellInstArray::iterator ii1 = i1element.at_end () ? i1.begin_touching (common_all.transformed (t1i), mp_layout) : i1element; ! ii1.at_end (); ++ii1) { db::ICplxTrans i1t = i1.complex_trans (*ii1); db::ICplxTrans tt1 = t1 * i1t; box_type ib1 = bb1.transformed (tt1); - for (db::CellInstArray::iterator ii2 = i2.begin_touching (ib1.transformed (t2i), mp_layout); ! ii2.at_end (); ++ii2) { + for (db::CellInstArray::iterator ii2 = i2element.at_end () ? i2.begin_touching (ib1.transformed (t2i), mp_layout) : i2element; ! ii2.at_end (); ++ii2) { db::ICplxTrans i2t = i2.complex_trans (*ii2); db::ICplxTrans tt2 = t2 * i2t; @@ -1559,7 +1553,7 @@ private: const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common12.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - consider_instance_pair (common12, i1, t1, *jj2, tt2, ii_interactions); + consider_instance_pair (common12, i1, t1, ii1, *jj2, tt2, db::CellInstArray::iterator (), ii_interactions); for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { propagate_cluster_inst (i->second, i2.cell_index (), i2t, i2.prop_id ()); @@ -1570,6 +1564,10 @@ private: } + if (! i2element.at_end ()) { + break; + } + } box_type common1 = ib1 & b2 & common; @@ -1579,7 +1577,7 @@ private: const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common1.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { - consider_instance_pair (common1, *jj1, tt1, i2, t2, ii_interactions); + consider_instance_pair (common1, *jj1, tt1, db::CellInstArray::iterator (), i2, t2, i2element, ii_interactions); for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { propagate_cluster_inst (i->first, i1.cell_index (), i1t, i1.prop_id ()); @@ -1590,6 +1588,10 @@ private: } + if (! i1element.at_end ()) { + break; + } + } std::pair &cached = (*mp_instance_interaction_cache) [ii_key]; @@ -1762,7 +1764,6 @@ private: pp.push_back (ClusterInstElement (i.cell_index (), i.complex_trans (*ii), i.prop_id ())); bool any = false; - bool first = true; for (db::CellInstArray::iterator ii2 = i.begin_touching (ib, mp_layout); ! ii2.at_end (); ++ii2) { @@ -1782,37 +1783,27 @@ private: cluster_instance_pair_list_type interacting_clusters; box_type common = (ib & ib2); - // @@@ replace: - add_single_pair (common, i.cell_index (), pp, tt, i.cell_index (), pp2, tt2, interacting_clusters); + const std::vector > &i2i_interactions = compute_instance_interactions (common, i.cell_index (), tt, i.cell_index (), tt2); + for (std::vector >::const_iterator ii = i2i_interactions.begin (); ii != i2i_interactions.end (); ++ii) { + ClusterInstance k1 (ii->first, i.cell_index (), tt, i.prop_id ()); + ClusterInstance k2 (ii->second, i.cell_index (), tt2, i.prop_id ()); + interacting_clusters.push_back (std::make_pair (k1, k2)); + } - // dive into cell of ii2 - this is a self-interaction of a cell with parts of itself - // as these self-interactions are expected to be the same always (regular array), we can skip this test the next times. - if (first) { + for (db::Cell::touching_iterator jj2 = cell.begin_touching (common.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - for (db::Cell::touching_iterator jj2 = cell.begin_touching (common.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { + db::ICplxTrans t; - db::ICplxTrans t; - - std::list > ii_interactions; - consider_instance_pair (common, i, t, *jj2, tt2, ii_interactions); - - for (std::list >::iterator ii = ii_interactions.begin (); ii != ii_interactions.end (); ++ii) { - propagate_cluster_inst (ii->second, i.cell_index (), tt2, i.prop_id ()); - } - interacting_clusters.splice (interacting_clusters.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); + std::list > ii_interactions; + consider_instance_pair (common, i, t, ii, *jj2, tt2, db::CellInstArray::iterator (), ii_interactions); + for (std::list >::iterator ii = ii_interactions.begin (); ii != ii_interactions.end (); ++ii) { + propagate_cluster_inst (ii->second, i.cell_index (), tt2, i.prop_id ()); } + interacting_clusters.splice (interacting_clusters.end (), ii_interactions, ii_interactions.begin (), ii_interactions.end ()); } - // @@@ move to connect_clusters: - // connect_clusters requires propagated cluster ID's - for (std::list >::const_iterator i = interacting_clusters.begin (); i != interacting_clusters.end (); ++i) { - ensure_cluster_inst_propagated (i->first, mp_cell->cell_index ()); - ensure_cluster_inst_propagated (i->second, mp_cell->cell_index ()); - } - // @@@ - connect_clusters (interacting_clusters); any = true; @@ -1821,8 +1812,6 @@ private: } - first = false; - // we don't expect more to happen on the next instance if (! any) { break; @@ -2006,34 +1995,24 @@ private: // @@@ void propagate_cluster_inst (ClusterInstance &ci, db::cell_index_type pci, const db::ICplxTrans &trans, db::properties_id_type prop_id) const { - size_t id_new = mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ci, pci); + size_t id_new = mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ci, pci, true); tl_assert (id_new != 0); ci = db::ClusterInstance (id_new, pci, trans, prop_id); } - // @@@ - void ensure_cluster_inst_propagated (const ClusterInstance &ci, db::cell_index_type pci) const - { - mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ci, pci); - } - /** * @brief Establishes connections between the cluster instances listed in the argument */ - void connect_clusters (const cluster_instance_pair_list_type &interacting_clusters, const db::ICplxTrans *ic_trans = 0, db::properties_id_type prop_id1 = 0, db::properties_id_type prop_id2 = 0) + void connect_clusters (const cluster_instance_pair_list_type &interacting_clusters) { for (cluster_instance_pair_list_type::const_iterator ic = interacting_clusters.begin (); ic != interacting_clusters.end (); ++ic) { - ClusterInstance k1 = ic->first; - ClusterInstance k2 = ic->second; + const ClusterInstance &k1 = ic->first; + const ClusterInstance &k2 = ic->second; - // @@@ - if (ic_trans) { - k1.transform (*ic_trans); - k1.set_inst_prop_id (prop_id1); - k2.transform (*ic_trans); - k2.set_inst_prop_id (prop_id2); - } + // Note: "with_self" is false as we're going to create a connected cluster anyway + mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, k1, mp_cell->cell_index (), false); + mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, k2, mp_cell->cell_index (), false); id_type x1 = mp_cell_clusters->find_cluster_with_connection (k1); id_type x2 = mp_cell_clusters->find_cluster_with_connection (k2); @@ -2096,7 +2075,7 @@ private: template size_t -hier_clusters::propagate_cluster_inst (const db::Layout &layout, const db::Cell &cell, const ClusterInstance &ci, db::cell_index_type pci) +hier_clusters::propagate_cluster_inst (const db::Layout &layout, const db::Cell &cell, const ClusterInstance &ci, db::cell_index_type pci, bool with_self) { connected_clusters &target_cc = clusters_per_cell (pci); size_t parent_cluster = target_cc.find_cluster_with_connection (ci); @@ -2128,7 +2107,7 @@ hier_clusters::propagate_cluster_inst (const db::Layout &layout, const db::Ce for (db::CellInstArray::iterator pii = child_inst.begin (); ! pii.at_end (); ++pii) { ClusterInstance ci2 (id, child_inst.cell_index (), child_inst.complex_trans (*pii), child_inst.prop_id ()); - if ((cell.cell_index () != pi->parent_cell_index () || ci != ci2) && seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { + if ((with_self || cell.cell_index () != pi->parent_cell_index () || ci != ci2) && seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { size_t id_dummy; diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 322563013..87448e883 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -1008,7 +1008,7 @@ public: ClusterInstance make_path (const db::Layout &layout, const db::Cell &cell, size_t id, const std::vector &path); // @@@ - size_t propagate_cluster_inst (const db::Layout &layout, const Cell &cell, const ClusterInstance &ci, db::cell_index_type pci); + size_t propagate_cluster_inst (const db::Layout &layout, const Cell &cell, const ClusterInstance &ci, db::cell_index_type pci, bool with_self); private: void build_local_cluster (const db::Layout &layout, const db::Cell &cell, db::ShapeIterator::flags_type shape_flags, const db::Connectivity &conn, const tl::equivalence_clusters *attr_equivalence); From da1ac3661f8214e124a93dbb411d2d3a70d9951d Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 00:16:47 +0100 Subject: [PATCH 09/21] WIP: bugfix of refactoriung, update test data. --- src/db/db/dbHierNetworkProcessor.cc | 4 +- src/db/db/dbHierNetworkProcessor.h | 38 ++++++++++++++---- src/db/unit_tests/dbLayoutToNetlistTests.cc | 12 +++--- .../algo/device_extract_au1_rebuild_nr.gds | Bin 9458 -> 9458 bytes .../algo/device_extract_au1_rebuild_pf.gds | Bin 49364 -> 49364 bytes .../algo/device_extract_au1_rebuild_pr.gds | Bin 29092 -> 29092 bytes .../algo/device_extract_au1_with_rec_nets.gds | Bin 50630 -> 50630 bytes .../algo/device_extract_au2_with_rec_nets.gds | Bin 38234 -> 38230 bytes .../algo/device_extract_au3_with_rec_nets.gds | Bin 46966 -> 46966 bytes .../algo/device_extract_au4_with_rec_nets.gds | Bin 49526 -> 49526 bytes .../device_extract_au5_flattened_circuits.gds | Bin 114198 -> 114198 bytes .../algo/device_extract_au5_with_rec_nets.gds | Bin 70670 -> 70670 bytes 12 files changed, 38 insertions(+), 16 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index f809dec86..1d9d5b253 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1518,8 +1518,6 @@ private: db::ICplxTrans t1i = t1.inverted (); db::ICplxTrans t2i = t2.inverted (); - std::list > ii_interactions; - // @@@ optimize for single inst? for (db::CellInstArray::iterator ii1 = i1element.at_end () ? i1.begin_touching (common_all.transformed (t1i), mp_layout) : i1element; ! ii1.at_end (); ++ii1) { @@ -1553,6 +1551,7 @@ private: const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common12.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { + std::list > ii_interactions; consider_instance_pair (common12, i1, t1, ii1, *jj2, tt2, db::CellInstArray::iterator (), ii_interactions); for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { @@ -1577,6 +1576,7 @@ private: const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common1.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { + std::list > ii_interactions; consider_instance_pair (common1, *jj1, tt1, db::CellInstArray::iterator (), i2, t2, i2element, ii_interactions); for (std::list >::iterator i = ii_interactions.begin (); i != ii_interactions.end (); ++i) { diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 87448e883..0f1619aaf 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -734,6 +734,30 @@ private: typedef std::list > cluster_instance_pair_list_type; +inline bool equal_array_delegates (const db::ArrayBase *a, const db::ArrayBase *b) +{ + if ((a == 0) != (b == 0)) { + return false; + } else if (a) { + static const db::array_base_ptr_cmp_f arr_less; + return ! arr_less (a, b) && ! arr_less (b, a); + } else { + return true; + } +} + +inline bool less_array_delegates (const db::ArrayBase *a, const db::ArrayBase *b) +{ + if ((a == 0) != (b == 0)) { + return (a == 0) < (b == 0); + } else if (a) { + static const db::array_base_ptr_cmp_f arr_less; + return arr_less (a, b); + } else { + return false; + } +} + /** * @brief A helper struct to describe a pair of cell instances with a specific relative transformation */ @@ -747,7 +771,8 @@ struct InstanceToInstanceInteraction { static const db::array_base_ptr_cmp_f arr_less; return ci1 == other.ci1 && ci2 == other.ci2 && t21.equal (other.t21) && - (array1 == 0) == (array2 == 0) && array1 != 0 && ! arr_less (array1, array2) && ! arr_less (array2, array1); + equal_array_delegates (array1, other.array1) && + equal_array_delegates (array2, other.array2); } bool operator< (const InstanceToInstanceInteraction &other) const @@ -761,15 +786,12 @@ struct InstanceToInstanceInteraction if (! t21.equal (other.t21)) { return t21.less (other.t21); } - if ((array1 == 0) != (array2 == 0)) { - return (array1 == 0) < (array2 == 0); - } - if (array1 != 0) { - static const db::array_base_ptr_cmp_f arr_less; - return arr_less (array1, array2); - } else { + if (less_array_delegates (array1, other.array1)) { + return true; + } else if (less_array_delegates (other.array1, array1)) { return false; } + return less_array_delegates (array2, other.array2); } db::cell_index_type ci1, ci2; diff --git a/src/db/unit_tests/dbLayoutToNetlistTests.cc b/src/db/unit_tests/dbLayoutToNetlistTests.cc index 6b7f0fd8e..40964ec67 100644 --- a/src/db/unit_tests/dbLayoutToNetlistTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistTests.cc @@ -791,7 +791,7 @@ TEST(2_Probing) EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "RINGO:VSS"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I18"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I5"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I3"); // doesn't do anything here, but we test that this does not destroy anything: l2n.netlist ()->combine_devices (); @@ -833,7 +833,7 @@ TEST(2_Probing) EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "RINGO:VSS"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I18"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I5"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I3"); } TEST(3_GlobalNetConnections) @@ -1071,7 +1071,7 @@ TEST(3_GlobalNetConnections) EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "RINGO:VSS"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I22"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I6"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I4"); // doesn't do anything here, but we test that this does not destroy anything: l2n.netlist ()->combine_devices (); @@ -1113,7 +1113,7 @@ TEST(3_GlobalNetConnections) EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "RINGO:VSS"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I22"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I6"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I4"); } TEST(4_GlobalNetDeviceExtraction) @@ -1357,7 +1357,7 @@ TEST(4_GlobalNetDeviceExtraction) EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "RINGO:VSS"); EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (2.6, 1.0))), "RINGO:$I22"); - EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I6"); + EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (6.4, 1.0))), "INV2PAIR:$I4"); // doesn't do anything here, but we test that this does not destroy anything: l2n.netlist ()->combine_devices (); @@ -1399,7 +1399,7 @@ TEST(4_GlobalNetDeviceExtraction) EXPECT_EQ (qnet_name (l2n.probe_net (*rmetal1, db::DPoint (5.3, 0.0))), "RINGO:VSS"); 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a/testdata/algo/device_extract_au4_with_rec_nets.gds b/testdata/algo/device_extract_au4_with_rec_nets.gds index 69d52a8499ca12781d3a58554969a5b79e3092df..95a6a3156e73e702ac78eae697c545accd13c4f9 100644 GIT binary patch delta 979 zcmey?#Qd#^S&4y-fr%-CL57iu{V@X%13v=;0|$czGJB$uvM6?msAwD#r*31Hn7oS- zm&_`rx!Cn=j$xK'wgf>UY_D>p7(ci3*@keYmk1DE^uaN>~JyoRfsNgHbbF^I9T z1^Ky##C!UM83j0c2F0s*nlMcMpeMFDg?A|n4o}GmJ;Ws?BL0yVhb}4Av$%Bq(Znfr zPwy;?CU&=rK;0hX>F4ebbhx20#O1Gyak_ko#eH0Em|=@ks>cbZRD(NCsS=;LS~!A2 ztz1?Yhg8IpUS=Fpzn0Hs$04<5{ahv-QgNGbNlg~miYrAQ+KMaLPX4s5iP2=T;tpXs hb_NC+R-Bn~^Rn%#OiYHxK&6tCd3Nz`{=Bo99RSeNm+Sxl delta 979 zcmey?#Qd#^S&4y-fr%-CL57iu{V@XUY_D>p7(ci3*@keYmk1DE^uaN>~JyoRfsNgHbbF^I9T z1^Ky##C!UM83j0c2F0s*nlViNpeMFDg?A|n4o}GmJ;Ws?BL0yVhb}4Av$%Bq(Znfr zPwy;?CU&=rK;0hX>F4ebbhwcr#O1Gyak_ko#eH0Em|=@ks>cbZRD(NCsS=;LS~!A2 ztz1?Yhg8IpUS=Fpzn0Hs$04<5{ahv-QgNGbNlg~miYrAQ+KMaLPX4s5iP3Db;tpXs hb_NC+R-Bn~^Rn%#OiV_GK&6tCd3Nz`{=Bo99RO_Qj8p&s diff --git a/testdata/algo/device_extract_au5_flattened_circuits.gds b/testdata/algo/device_extract_au5_flattened_circuits.gds index bb997bf82baa72ffeb1c46dda0c1f1390c6856e2..a0b32677efc3f5fad3a69ee0ef3755a68b43a826 100644 GIT binary patch delta 888 zcmbRChi%#)HYEl&1}3Hm1{p>s_Qwo74EziX3@i+W$n1$q%A!~$Hb!wXW0%=n#hlNJ zL+YQvT`n9_AEa?gJyN^NrGeEI3?gi7L4K|w@j;$`?*8#Ao`%Mg9c9Ef|1;c*%bpW9 z_i;(>amOjOAqc0`l31KlGcx8{;_$B5B3T<8QZ@HtIdDk5dv=!(htz|wcX8>u^beQR z_9N_!cRAFthpiAB8*0!_pJ2i$w*8&}<5nCtZC@b?G!DB1x6e|-E!U%sTdvLow_JfO z<6M0l_9^8u${OL23z^Rt%Z@|t*fPf3+}P!&Z`;J^ja_QH*k;BSMn=Qw{#zJTw;$NT bxSEm4(0Ka9&5V-M*KA|t-9C96V>3Gd@*s_Qwod3{nh?3>*xM$n1$q%A!~$Hb!wXW0%=n#hlNJ zL+YQvT`n9_AEa?gJyN^NrGeEI3?gi7L4K|w@j;$`?*8#Ao<@d~9c9Ef|1;c*%bpW9 z_i;(>amOjOAqc0`l31KlGcx8{;_$B5B3T<8QZ@HtIdDk5dv=!(htz|wcX8>u^beQR z_9N_!cRAFthpiAB8*0!_pJ2i$w*8&}<5nCtZC@b?G!DB1x6e|-E!U%sTdvLow_JfO z<6M0l_9^8u${OL23z^Rt%Z@|t*fPf3+}P!&Z`;J^ja_QH*k;BSMkXV}=>c09Rkk14 Z!nhjDo4A=#a{8KWjJ(??Z)0p`2LS3Uh%5jA diff --git a/testdata/algo/device_extract_au5_with_rec_nets.gds b/testdata/algo/device_extract_au5_with_rec_nets.gds index 6f30100c642a0f7f558036e3b2d19d8eedf3d2ea..365498e935aac0fa4a0a9562ec28d390db802ac7 100644 GIT binary patch delta 864 zcmeBM!P2*aMTvopfr%-CL57iu{V@X%13v=;0|x^iGJB$uvM6?msA%jG8&5?uVwc%$ z#e_?0@+#)JI5fqu%*JIN4;xOYJ?yt}=~}}njYDek9j@CrTyciGoEe8y1ivRA4ykRj zce!v#t2AXAogy3-WUfi4XGhbN7!|@ia8vJm2mNE;|}L@8gmx3Bf6q z5sy;PK(ahm`D delta 864 zcmeBM!P2*aMTvopfr%-CL57iu{V@X2AXAogy3-WUfi4XGhbN7!|@ia2rJm2mNE;|}L@8gmx3Bf6q z5sy;N;qaOD61 From 96e591cba9155620ce63eca38d7ff0cb15380b7c Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 00:23:05 +0100 Subject: [PATCH 10/21] WIP: further updates of test data. --- testdata/algo/l2n_writer_au_2b.txt | 28 +- testdata/algo/l2n_writer_au_2s.txt | 28 +- testdata/algo/lvs_test1_au.lvsdb.1 | 92 +-- testdata/algo/lvs_test1_au.lvsdb.2 | 1090 -------------------------- testdata/algo/lvs_test1b_au.lvsdb.1 | 92 +-- testdata/algo/lvs_test1b_au.lvsdb.2 | 1090 -------------------------- testdata/algo/lvs_test2_au.lvsdb.1 | 92 +-- testdata/algo/lvs_test2_au.lvsdb.2 | 1126 --------------------------- testdata/algo/lvs_test2b_au.lvsdb.1 | 92 +-- testdata/algo/lvs_test2b_au.lvsdb.2 | 1126 --------------------------- 10 files changed, 212 insertions(+), 4644 deletions(-) delete mode 100644 testdata/algo/lvs_test1_au.lvsdb.2 delete mode 100644 testdata/algo/lvs_test1b_au.lvsdb.2 delete mode 100644 testdata/algo/lvs_test2_au.lvsdb.2 delete mode 100644 testdata/algo/lvs_test2b_au.lvsdb.2 diff --git a/testdata/algo/l2n_writer_au_2b.txt b/testdata/algo/l2n_writer_au_2b.txt index 8709c5c46..c232887a5 100644 --- a/testdata/algo/l2n_writer_au_2b.txt +++ b/testdata/algo/l2n_writer_au_2b.txt @@ -270,12 +270,6 @@ circuit(INV2PAIR rect(diff_cont (-220 180) (220 220)) ) net(4 - rect(diff_cont (2390 3690) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(5 rect(diff_cont (4230 3290) (220 220)) rect(diff_cont (-220 180) (220 220)) rect(diff_cont (-220 -220) (220 220)) @@ -289,7 +283,7 @@ circuit(INV2PAIR rect(metal1 (-3000 -760) (360 760)) rect(metal1 (-360 -760) (360 760)) ) - net(6 + net(5 rect(diff_cont (4230 490) (220 220)) rect(diff_cont (-220 180) (220 220)) rect(diff_cont (-220 -220) (220 220)) @@ -303,6 +297,12 @@ circuit(INV2PAIR rect(metal1 (-3000 -760) (360 760)) rect(metal1 (-360 -760) (360 760)) ) + net(6 + rect(diff_cont (2390 3690) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -2620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + ) net(7) net(8 rect(diff_cont (5030 3690) (220 220)) @@ -315,8 +315,8 @@ circuit(INV2PAIR # Outgoing pins and their connections to nets pin(1 name(BULK)) pin(2) + pin(4) pin(5) - pin(6) pin(7) pin(8) pin(9) @@ -326,18 +326,18 @@ circuit(INV2PAIR pin(0 9) pin(1 7) pin(2 3) - pin(3 4) - pin(4 6) - pin(5 5) + pin(3 6) + pin(4 5) + pin(5 4) pin(6 1) ) circuit(2 INV2 location(4340 800) pin(0 9) - pin(1 4) + pin(1 6) pin(2 2) pin(3 8) - pin(4 6) - pin(5 5) + pin(4 5) + pin(5 4) pin(6 1) ) diff --git a/testdata/algo/l2n_writer_au_2s.txt b/testdata/algo/l2n_writer_au_2s.txt index e90dd3e1d..c12295b2d 100644 --- a/testdata/algo/l2n_writer_au_2s.txt +++ b/testdata/algo/l2n_writer_au_2s.txt @@ -238,12 +238,6 @@ X(INV2PAIR R(diff_cont (-220 180) (220 220)) ) N(4 - R(diff_cont (2390 3690) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - ) - N(5 R(diff_cont (4230 3290) (220 220)) R(diff_cont (-220 180) (220 220)) R(diff_cont (-220 -220) (220 220)) @@ -257,7 +251,7 @@ X(INV2PAIR R(metal1 (-3000 -760) (360 760)) R(metal1 (-360 -760) (360 760)) ) - N(6 + N(5 R(diff_cont (4230 490) (220 220)) R(diff_cont (-220 180) (220 220)) R(diff_cont (-220 -220) (220 220)) @@ -271,6 +265,12 @@ X(INV2PAIR R(metal1 (-3000 -760) (360 760)) R(metal1 (-360 -760) (360 760)) ) + N(6 + R(diff_cont (2390 3690) (220 220)) + R(diff_cont (-220 -620) (220 220)) + R(diff_cont (-220 -2620) (220 220)) + R(diff_cont (-220 -620) (220 220)) + ) N(7) N(8 R(diff_cont (5030 3690) (220 220)) @@ -281,8 +281,8 @@ X(INV2PAIR N(9) P(1 I(BULK)) P(2) + P(4) P(5) - P(6) P(7) P(8) P(9) @@ -290,18 +290,18 @@ X(INV2PAIR P(0 9) P(1 7) P(2 3) - P(3 4) - P(4 6) - P(5 5) + P(3 6) + P(4 5) + P(5 4) P(6 1) ) X(2 INV2 Y(4340 800) P(0 9) - P(1 4) + P(1 6) P(2 2) P(3 8) - P(4 6) - P(5 5) + P(4 5) + P(5 4) P(6 1) ) ) diff --git a/testdata/algo/lvs_test1_au.lvsdb.1 b/testdata/algo/lvs_test1_au.lvsdb.1 index b32d9f40d..add09797d 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.1 +++ b/testdata/algo/lvs_test1_au.lvsdb.1 @@ -268,24 +268,6 @@ layout( # Nets with their geometries net(1 name(BULK)) net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 rect(diff_cont (4230 3290) (220 220)) rect(diff_cont (-220 180) (220 220)) rect(diff_cont (-220 180) (220 220)) @@ -307,7 +289,7 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) - net(4 + net(3 rect(diff_cont (4230 890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -329,6 +311,24 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) + net(4 + rect(diff_cont (790 890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) net(5) net(6 rect(diff_cont (3430 890) (220 220)) @@ -363,17 +363,17 @@ layout( circuit(1 INV2 location(1700 800) pin(0 7) pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) + pin(2 4) + pin(3 3) + pin(4 2) pin(5 1) ) circuit(2 INV2 location(4340 800) pin(0 7) - pin(1 2) + pin(1 4) pin(2 6) - pin(3 4) - pin(4 3) + pin(3 3) + pin(4 2) pin(5 1) ) @@ -808,45 +808,45 @@ layout( # Subcircuits and their connections circuit(1 INV2PAIR location(19420 -800) pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 1) pin(4 10) pin(5 2) pin(6 3) ) circuit(2 INV2PAIR location(-1700 -800) pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 8) pin(4 1) pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 7) pin(4 9) pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 6) pin(4 12) pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 5) pin(4 11) pin(5 10) pin(6 3) @@ -1044,16 +1044,16 @@ xref( ) circuit(INV2PAIR INV2PAIR match xref( - net(3 2 match) - net(4 3 match) - net(2 4 match) + net(2 2 match) + net(3 3 match) + net(4 4 match) net(5 5 match) net(6 6 match) net(7 7 match) net(1 1 match) - pin(2 1 match) - pin(3 2 match) - pin(1 3 match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) pin(4 4 match) pin(5 5 match) pin(6 6 match) diff --git a/testdata/algo/lvs_test1_au.lvsdb.2 b/testdata/algo/lvs_test1_au.lvsdb.2 deleted file mode 100644 index bba5f19c4..000000000 --- a/testdata/algo/lvs_test1_au.lvsdb.2 +++ /dev/null @@ -1,1090 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(bulk '1/0') - layer(nwell '1/0') - layer(poly '3/0') - layer(poly_lbl '3/1') - layer(diff_cont '4/0') - layer(poly_cont '5/0') - layer(metal1 '6/0') - layer(metal1_lbl '6/1') - layer(via1 '7/0') - layer(metal2 '8/0') - layer(metal2_lbl '8/1') - layer(ntie) - layer(psd) - layer(ptie) - layer(nsd) - - # Mask layer connectivity - connect(nwell nwell ntie) - connect(poly poly poly_lbl poly_cont) - connect(poly_lbl poly) - connect(diff_cont diff_cont metal1 ntie psd ptie nsd) - connect(poly_cont poly poly_cont metal1) - connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) - connect(metal1_lbl metal1) - connect(via1 metal1 via1 metal2) - connect(metal2 via1 metal2 metal2_lbl) - connect(metal2_lbl metal2) - connect(ntie nwell diff_cont ntie) - connect(psd diff_cont psd) - connect(ptie diff_cont ptie) - connect(nsd diff_cont nsd) - - # Global nets and connectivity - global(bulk BULK) - global(ptie BULK) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(psd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (550 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(psd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (525 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(nsd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (550 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(nsd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (525 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Circuit boundary - rect((-1700 -2440) (3100 7820)) - - # Nets with their geometries - net(1 - rect(nwell (-1400 1800) (2800 3580)) - rect(diff_cont (-1510 -650) (220 220)) - rect(ntie (-510 -450) (800 680)) - ) - net(2 name(IN) - rect(poly (-525 -250) (250 2500)) - rect(poly (-1425 -630) (2100 360)) - rect(poly (-125 -2230) (250 2500)) - rect(poly (-1050 -3850) (250 2400)) - rect(poly (550 1200) (250 2400)) - rect(poly (-250 -6000) (250 2400)) - rect(poly (-1050 1200) (250 2400)) - rect(poly_lbl (-526 -2601) (2 2)) - rect(poly_cont (-831 -111) (220 220)) - ) - net(3 name(OUT) - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (1310 -3710) (360 2220)) - rect(metal1 (-1900 -800) (2220 360)) - rect(metal1 (-2280 -2400) (360 2840)) - rect(metal1 (-360 -3600) (360 1560)) - rect(metal1 (1240 2040) (360 1560)) - rect(metal1 (-360 -5160) (360 1560)) - rect(metal1 (-1960 2040) (360 1560)) - rect(metal1_lbl (1419 -2181) (2 2)) - rect(psd (-1851 524) (525 1750)) - rect(psd (1050 -1750) (525 1750)) - rect(nsd (-2100 -5350) (525 1750)) - rect(nsd (1050 -1750) (525 1750)) - ) - net(4 name(VSS) - rect(diff_cont (-110 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-290 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -705) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 -1450) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -775) (2800 1700)) - rect(metal2_lbl (-161 -541) (2 2)) - rect(nsd (-1516 -1186) (550 1750)) - ) - net(5 name(VDD) - rect(diff_cont (-110 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-290 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -1505) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -1575) (2800 1700)) - rect(metal2_lbl (-151 -1251) (2 2)) - rect(psd (-1526 -476) (550 1750)) - ) - net(6 name(BULK) - rect(diff_cont (-110 -2160) (220 220)) - rect(ptie (-510 -450) (800 680)) - ) - - # Outgoing pins and their connections to nets - pin(1) - pin(2 name(IN)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5 name(VDD)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 3200) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(3 D$NMOS - device(D$NMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 -400) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Circuit boundary - rect((0 -1640) (5740 7820)) - - # Nets with their geometries - net(1 name(BULK)) - net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 - rect(diff_cont (4230 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (2350 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(4 - rect(diff_cont (4230 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (2350 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(5) - net(6 - rect(diff_cont (3430 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7) - - # Outgoing pins and their connections to nets - pin(1 name(BULK)) - pin(2) - pin(3) - pin(4) - pin(5) - pin(6) - pin(7) - - # Subcircuits and their connections - circuit(1 INV2 location(1700 800) - pin(0 7) - pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) - pin(5 1) - ) - circuit(2 INV2 location(4340 800) - pin(0 7) - pin(1 2) - pin(2 6) - pin(3 4) - pin(4 3) - pin(5 1) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((-1720 -2440) (26880 7820)) - - # Nets with their geometries - net(1 name(FB) - rect(diff_cont (20210 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-22130 -2290) (360 360)) - rect(via1 (-305 -305) (250 250)) - rect(via1 (23190 -250) (250 250)) - rect(metal2 (-23765 -325) (23840 400)) - rect(metal2_lbl (-22121 -201) (2 2)) - ) - net(2 name(OSC) - rect(diff_cont (22850 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(via1 (1365 -2235) (250 250)) - rect(metal2 (-325 -325) (400 400)) - rect(metal2_lbl (-201 -201) (2 2)) - ) - net(3 name(VDD) - rect(diff_cont (7810 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (12980 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-21410 -10) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -2600) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -1181) (2 2)) - ) - net(4 name(VSS) - rect(diff_cont (7810 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (12980 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -1330) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -80) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -381) (2 2)) - ) - net(5 - rect(diff_cont (14930 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(6 - rect(diff_cont (9650 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7 - rect(diff_cont (4370 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(8 - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(9 - rect(diff_cont (1730 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(10 - rect(diff_cont (17570 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(11 - rect(diff_cont (12290 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(12 - rect(diff_cont (7010 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(FB)) - pin(2 name(OSC)) - pin(3 name(VDD)) - pin(4 name(VSS)) - - # Subcircuits and their connections - circuit(1 INV2PAIR location(19420 -800) - pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) - pin(4 10) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR location(-1700 -800) - pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) - pin(4 1) - pin(5 9) - pin(6 3) - ) - circuit(3 INV2PAIR location(3580 -800) - pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) - pin(4 9) - pin(5 12) - pin(6 3) - ) - circuit(4 INV2PAIR location(8860 -800) - pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) - pin(4 12) - pin(5 11) - pin(6 3) - ) - circuit(5 INV2PAIR location(14140 -800) - pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) - pin(4 11) - pin(5 10) - pin(6 3) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(2 NMOS - name($3) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($1) - pin(0 7) - pin(1 5) - pin(2 4) - pin(3 3) - pin(4 2) - pin(5 1) - ) - circuit(2 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) - circuit(RINGO - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('6')) - net(6 name('100')) - net(7 name('5')) - net(8 name('101')) - net(9 name('8')) - net(10 name('102')) - net(11 name('7')) - net(12 name('103')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - - # Subcircuits and their connections - circuit(1 INV2PAIR name($1) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 1) - pin(4 5) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR name($2) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 6) - pin(4 1) - pin(5 7) - pin(6 3) - ) - circuit(3 INV2PAIR name($3) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 8) - pin(4 7) - pin(5 9) - pin(6 3) - ) - circuit(4 INV2PAIR name($4) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 10) - pin(4 9) - pin(5 11) - pin(6 3) - ) - circuit(5 INV2PAIR name($5) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 12) - pin(4 11) - pin(5 5) - pin(6 3) - ) - - ) -) - -# Cross reference -xref( - circuit(INV2 INV2 match - xref( - net(1 1 match) - net(6 6 match) - net(2 2 match) - net(3 3 match) - net(5 5 match) - net(4 4 match) - pin(0 0 match) - pin(5 5 match) - pin(1 1 match) - pin(2 2 match) - pin(4 4 match) - pin(3 3 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(INV2PAIR INV2PAIR match - xref( - net(3 2 match) - net(4 3 match) - net(2 4 match) - net(5 5 match) - net(6 6 match) - net(7 7 match) - net(1 1 match) - pin(2 1 match) - pin(3 2 match) - pin(1 3 match) - pin(4 4 match) - pin(5 5 match) - pin(6 6 match) - pin(0 0 match) - circuit(1 1 match) - circuit(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(8 6 match) - net(7 8 match) - net(6 10 match) - net(5 12 match) - net(9 7 match) - net(10 5 match) - net(11 11 match) - net(12 9 match) - net(1 1 match) - net(2 2 match) - net(3 3 match) - net(4 4 match) - pin(0 0 match) - pin(1 1 match) - pin(2 2 match) - pin(3 3 match) - circuit(1 1 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - ) - ) -) diff --git a/testdata/algo/lvs_test1b_au.lvsdb.1 b/testdata/algo/lvs_test1b_au.lvsdb.1 index 556dcc6dd..460cae8e7 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.1 +++ b/testdata/algo/lvs_test1b_au.lvsdb.1 @@ -268,24 +268,6 @@ layout( # Nets with their geometries net(1 name(BULK)) net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 rect(diff_cont (4230 3290) (220 220)) rect(diff_cont (-220 180) (220 220)) rect(diff_cont (-220 180) (220 220)) @@ -307,7 +289,7 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) - net(4 + net(3 rect(diff_cont (4230 890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -329,6 +311,24 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) + net(4 + rect(diff_cont (790 890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) net(5) net(6 rect(diff_cont (3430 890) (220 220)) @@ -363,17 +363,17 @@ layout( circuit(1 INV2 location(1700 800) pin(0 7) pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) + pin(2 4) + pin(3 3) + pin(4 2) pin(5 1) ) circuit(2 INV2 location(4340 800) pin(0 7) - pin(1 2) + pin(1 4) pin(2 6) - pin(3 4) - pin(4 3) + pin(3 3) + pin(4 2) pin(5 1) ) @@ -808,45 +808,45 @@ layout( # Subcircuits and their connections circuit(1 INV2PAIR location(19420 -800) pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 1) pin(4 10) pin(5 2) pin(6 3) ) circuit(2 INV2PAIR location(-1700 -800) pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 8) pin(4 1) pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 7) pin(4 9) pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 6) pin(4 12) pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 5) pin(4 11) pin(5 10) pin(6 3) @@ -1044,16 +1044,16 @@ xref( ) circuit(INV2PAIR INV2PAIR match xref( - net(3 2 match) - net(4 3 match) - net(2 4 match) + net(2 2 match) + net(3 3 match) + net(4 4 match) net(5 5 match) net(6 6 match) net(7 7 match) net(1 1 match) - pin(2 1 match) - pin(3 2 match) - pin(1 3 match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) pin(4 4 match) pin(5 5 match) pin(6 6 match) diff --git a/testdata/algo/lvs_test1b_au.lvsdb.2 b/testdata/algo/lvs_test1b_au.lvsdb.2 deleted file mode 100644 index bef20e994..000000000 --- a/testdata/algo/lvs_test1b_au.lvsdb.2 +++ /dev/null @@ -1,1090 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(bulk '1/0') - layer(nwell '1/0') - layer(poly '3/0') - layer(poly_lbl '3/1') - layer(diff_cont '4/0') - layer(poly_cont '5/0') - layer(metal1 '6/0') - layer(metal1_lbl '6/1') - layer(via1 '7/0') - layer(metal2 '8/0') - layer(metal2_lbl '8/1') - layer(ntie) - layer(psd) - layer(ptie) - layer(nsd) - - # Mask layer connectivity - connect(nwell nwell ntie) - connect(poly poly poly_lbl poly_cont) - connect(poly_lbl poly) - connect(diff_cont diff_cont metal1 ntie psd ptie nsd) - connect(poly_cont poly poly_cont metal1) - connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) - connect(metal1_lbl metal1) - connect(via1 metal1 via1 metal2) - connect(metal2 via1 metal2 metal2_lbl) - connect(metal2_lbl metal2) - connect(ntie nwell diff_cont ntie) - connect(psd diff_cont psd) - connect(ptie diff_cont ptie) - connect(nsd diff_cont nsd) - - # Global nets and connectivity - global(bulk BULK) - global(ptie BULK) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(psd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (550 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(psd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (525 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(nsd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (550 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(nsd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (525 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Circuit boundary - rect((-1700 -2440) (3100 7820)) - - # Nets with their geometries - net(1 - rect(nwell (-1400 1800) (2800 3580)) - rect(diff_cont (-1510 -650) (220 220)) - rect(ntie (-510 -450) (800 680)) - ) - net(2 name(IN) - rect(poly (-525 -250) (250 2500)) - rect(poly (-1425 -630) (2100 360)) - rect(poly (-125 -2230) (250 2500)) - rect(poly (-1050 -3850) (250 2400)) - rect(poly (550 1200) (250 2400)) - rect(poly (-250 -6000) (250 2400)) - rect(poly (-1050 1200) (250 2400)) - rect(poly_lbl (-526 -2601) (2 2)) - rect(poly_cont (-831 -111) (220 220)) - ) - net(3 name(OUT) - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (1310 -3710) (360 2220)) - rect(metal1 (-1900 -800) (2220 360)) - rect(metal1 (-2280 -2400) (360 2840)) - rect(metal1 (-360 -3600) (360 1560)) - rect(metal1 (1240 2040) (360 1560)) - rect(metal1 (-360 -5160) (360 1560)) - rect(metal1 (-1960 2040) (360 1560)) - rect(metal1_lbl (1419 -2181) (2 2)) - rect(psd (-1851 524) (525 1750)) - rect(psd (1050 -1750) (525 1750)) - rect(nsd (-2100 -5350) (525 1750)) - rect(nsd (1050 -1750) (525 1750)) - ) - net(4 name(VSS) - rect(diff_cont (-110 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-290 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -705) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 -1450) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -775) (2800 1700)) - rect(metal2_lbl (-161 -541) (2 2)) - rect(nsd (-1516 -1186) (550 1750)) - ) - net(5 name(VDD) - rect(diff_cont (-110 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-290 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -1505) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -1575) (2800 1700)) - rect(metal2_lbl (-151 -1251) (2 2)) - rect(psd (-1526 -476) (550 1750)) - ) - net(6 name(BULK) - rect(diff_cont (-110 -2160) (220 220)) - rect(ptie (-510 -450) (800 680)) - ) - - # Outgoing pins and their connections to nets - pin(1) - pin(2 name(IN)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5 name(VDD)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 3200) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(2 D$NMOS - device(D$NMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 -400) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Circuit boundary - rect((0 -1640) (5740 7820)) - - # Nets with their geometries - net(1 name(BULK)) - net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 - rect(diff_cont (4230 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (2350 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(4 - rect(diff_cont (4230 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (2350 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(5) - net(6 - rect(diff_cont (3430 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7) - - # Outgoing pins and their connections to nets - pin(1 name(BULK)) - pin(2) - pin(3) - pin(4) - pin(5) - pin(6) - pin(7) - - # Subcircuits and their connections - circuit(1 INV2 location(1700 800) - pin(0 7) - pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) - pin(5 1) - ) - circuit(2 INV2 location(4340 800) - pin(0 7) - pin(1 2) - pin(2 6) - pin(3 4) - pin(4 3) - pin(5 1) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((-1720 -2440) (26880 7820)) - - # Nets with their geometries - net(1 name(FB) - rect(diff_cont (20210 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-22130 -2290) (360 360)) - rect(via1 (-305 -305) (250 250)) - rect(via1 (23190 -250) (250 250)) - rect(metal2 (-23765 -325) (23840 400)) - rect(metal2_lbl (-22121 -201) (2 2)) - ) - net(2 name(OSC) - rect(diff_cont (22850 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(via1 (1365 -2235) (250 250)) - rect(metal2 (-325 -325) (400 400)) - rect(metal2_lbl (-201 -201) (2 2)) - ) - net(3 name(VDD) - rect(diff_cont (7810 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (12980 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-21410 -10) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -2600) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -1181) (2 2)) - ) - net(4 name(VSS) - rect(diff_cont (7810 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (12980 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -1330) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -80) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -381) (2 2)) - ) - net(5 - rect(diff_cont (14930 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(6 - rect(diff_cont (9650 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7 - rect(diff_cont (4370 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(8 - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(9 - rect(diff_cont (1730 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(10 - rect(diff_cont (17570 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(11 - rect(diff_cont (12290 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(12 - rect(diff_cont (7010 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(FB)) - pin(2 name(OSC)) - pin(3 name(VDD)) - pin(4 name(VSS)) - - # Subcircuits and their connections - circuit(1 INV2PAIR location(19420 -800) - pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) - pin(4 10) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR location(-1700 -800) - pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) - pin(4 1) - pin(5 9) - pin(6 3) - ) - circuit(3 INV2PAIR location(3580 -800) - pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) - pin(4 9) - pin(5 12) - pin(6 3) - ) - circuit(4 INV2PAIR location(8860 -800) - pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) - pin(4 12) - pin(5 11) - pin(6 3) - ) - circuit(5 INV2PAIR location(14140 -800) - pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) - pin(4 11) - pin(5 10) - pin(6 3) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(2 NMOS - name($3) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($1) - pin(0 7) - pin(1 5) - pin(2 4) - pin(3 3) - pin(4 2) - pin(5 1) - ) - circuit(2 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) - circuit(RINGO - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('6')) - net(6 name('100')) - net(7 name('5')) - net(8 name('101')) - net(9 name('8')) - net(10 name('102')) - net(11 name('7')) - net(12 name('103')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - - # Subcircuits and their connections - circuit(1 INV2PAIR name($1) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 1) - pin(4 5) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR name($2) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 6) - pin(4 1) - pin(5 7) - pin(6 3) - ) - circuit(3 INV2PAIR name($3) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 8) - pin(4 7) - pin(5 9) - pin(6 3) - ) - circuit(4 INV2PAIR name($4) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 10) - pin(4 9) - pin(5 11) - pin(6 3) - ) - circuit(5 INV2PAIR name($5) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 12) - pin(4 11) - pin(5 5) - pin(6 3) - ) - - ) -) - -# Cross reference -xref( - circuit(INV2 INV2 match - xref( - net(1 1 match) - net(6 6 match) - net(2 2 match) - net(3 3 match) - net(5 5 match) - net(4 4 match) - pin(0 0 match) - pin(5 5 match) - pin(1 1 match) - pin(2 2 match) - pin(4 4 match) - pin(3 3 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INV2PAIR INV2PAIR match - xref( - net(3 2 match) - net(4 3 match) - net(2 4 match) - net(5 5 match) - net(6 6 match) - net(7 7 match) - net(1 1 match) - pin(2 1 match) - pin(3 2 match) - pin(1 3 match) - pin(4 4 match) - pin(5 5 match) - pin(6 6 match) - pin(0 0 match) - circuit(1 1 match) - circuit(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(8 6 match) - net(7 8 match) - net(6 10 match) - net(5 12 match) - net(9 7 match) - net(10 5 match) - net(11 11 match) - net(12 9 match) - net(1 1 match) - net(2 2 match) - net(3 3 match) - net(4 4 match) - pin(0 0 match) - pin(1 1 match) - pin(2 2 match) - pin(3 3 match) - circuit(1 1 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - ) - ) -) diff --git a/testdata/algo/lvs_test2_au.lvsdb.1 b/testdata/algo/lvs_test2_au.lvsdb.1 index b78d22e71..7c95c540f 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.1 +++ b/testdata/algo/lvs_test2_au.lvsdb.1 @@ -268,24 +268,6 @@ layout( # Nets with their geometries net(1 name(BULK)) net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 rect(diff_cont (4230 3290) (220 220)) rect(diff_cont (-220 180) (220 220)) rect(diff_cont (-220 180) (220 220)) @@ -307,7 +289,7 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) - net(4 + net(3 rect(diff_cont (4230 890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -329,6 +311,24 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) + net(4 + rect(diff_cont (790 890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) net(5) net(6 rect(diff_cont (3430 890) (220 220)) @@ -363,17 +363,17 @@ layout( circuit(1 INV2 location(1700 800) pin(0 7) pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) + pin(2 4) + pin(3 3) + pin(4 2) pin(5 1) ) circuit(2 INV2 location(4340 800) pin(0 7) - pin(1 2) + pin(1 4) pin(2 6) - pin(3 4) - pin(4 3) + pin(3 3) + pin(4 2) pin(5 1) ) @@ -808,45 +808,45 @@ layout( # Subcircuits and their connections circuit(1 INV2PAIR location(19420 -800) pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 1) pin(4 10) pin(5 2) pin(6 3) ) circuit(2 INV2PAIR location(-1700 -800) pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 8) pin(4 1) pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 7) pin(4 9) pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 6) pin(4 12) pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 5) pin(4 11) pin(5 10) pin(6 3) @@ -1070,17 +1070,17 @@ xref( ) circuit(INV2PAIR INV2PAIR nomatch xref( - net(3 2 mismatch) - net(4 3 mismatch) + net(2 2 mismatch) + net(3 3 mismatch) net(5 4 match) - net(2 5 mismatch) + net(4 5 mismatch) net(6 6 match) net(7 7 mismatch) net(1 1 mismatch) - pin(2 1 match) - pin(3 2 match) + pin(1 1 match) + pin(2 2 match) pin(4 3 match) - pin(1 4 match) + pin(3 4 match) pin(5 5 match) pin(6 6 match) pin(0 0 match) diff --git a/testdata/algo/lvs_test2_au.lvsdb.2 b/testdata/algo/lvs_test2_au.lvsdb.2 deleted file mode 100644 index 7ceccdcd8..000000000 --- a/testdata/algo/lvs_test2_au.lvsdb.2 +++ /dev/null @@ -1,1126 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(bulk '1/0') - layer(nwell '1/0') - layer(poly '3/0') - layer(poly_lbl '3/1') - layer(diff_cont '4/0') - layer(poly_cont '5/0') - layer(metal1 '6/0') - layer(metal1_lbl '6/1') - layer(via1 '7/0') - layer(metal2 '8/0') - layer(metal2_lbl '8/1') - layer(ntie) - layer(psd) - layer(ptie) - layer(nsd) - - # Mask layer connectivity - connect(nwell nwell ntie) - connect(poly poly poly_lbl poly_cont) - connect(poly_lbl poly) - connect(diff_cont diff_cont metal1 ntie psd ptie nsd) - connect(poly_cont poly poly_cont metal1) - connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) - connect(metal1_lbl metal1) - connect(via1 metal1 via1 metal2) - connect(metal2 via1 metal2 metal2_lbl) - connect(metal2_lbl metal2) - connect(ntie nwell diff_cont ntie) - connect(psd diff_cont psd) - connect(ptie diff_cont ptie) - connect(nsd diff_cont nsd) - - # Global nets and connectivity - global(bulk BULK) - global(ptie BULK) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(psd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (550 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(psd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (525 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(nsd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (550 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(nsd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (525 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Circuit boundary - rect((-1700 -2440) (3100 7820)) - - # Nets with their geometries - net(1 - rect(nwell (-1400 1800) (2800 3580)) - rect(diff_cont (-1510 -650) (220 220)) - rect(ntie (-510 -450) (800 680)) - ) - net(2 name(IN) - rect(poly (-525 -250) (250 2500)) - rect(poly (-1425 -630) (2100 360)) - rect(poly (-125 -2230) (250 2500)) - rect(poly (-1050 -3850) (250 2400)) - rect(poly (550 1200) (250 2400)) - rect(poly (-250 -6000) (250 2400)) - rect(poly (-1050 1200) (250 2400)) - rect(poly_lbl (-526 -2601) (2 2)) - rect(poly_cont (-831 -111) (220 220)) - ) - net(3 name(OUT) - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (1310 -3710) (360 2220)) - rect(metal1 (-1900 -800) (2220 360)) - rect(metal1 (-2280 -2400) (360 2840)) - rect(metal1 (-360 -3600) (360 1560)) - rect(metal1 (1240 2040) (360 1560)) - rect(metal1 (-360 -5160) (360 1560)) - rect(metal1 (-1960 2040) (360 1560)) - rect(metal1_lbl (1419 -2181) (2 2)) - rect(psd (-1851 524) (525 1750)) - rect(psd (1050 -1750) (525 1750)) - rect(nsd (-2100 -5350) (525 1750)) - rect(nsd (1050 -1750) (525 1750)) - ) - net(4 name(VSS) - rect(diff_cont (-110 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-290 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -705) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 -1450) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -775) (2800 1700)) - rect(metal2_lbl (-161 -541) (2 2)) - rect(nsd (-1516 -1186) (550 1750)) - ) - net(5 name(VDD) - rect(diff_cont (-110 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-290 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -1505) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -1575) (2800 1700)) - rect(metal2_lbl (-151 -1251) (2 2)) - rect(psd (-1526 -476) (550 1750)) - ) - net(6 name(BULK) - rect(diff_cont (-110 -2160) (220 220)) - rect(ptie (-510 -450) (800 680)) - ) - - # Outgoing pins and their connections to nets - pin(1) - pin(2 name(IN)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5 name(VDD)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 3200) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(3 D$NMOS - device(D$NMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 -400) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Circuit boundary - rect((0 -1640) (5740 7820)) - - # Nets with their geometries - net(1 name(BULK)) - net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 - rect(diff_cont (4230 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (2350 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(4 - rect(diff_cont (4230 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (2350 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(5) - net(6 - rect(diff_cont (3430 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7) - - # Outgoing pins and their connections to nets - pin(1 name(BULK)) - pin(2) - pin(3) - pin(4) - pin(5) - pin(6) - pin(7) - - # Subcircuits and their connections - circuit(1 INV2 location(1700 800) - pin(0 7) - pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) - pin(5 1) - ) - circuit(2 INV2 location(4340 800) - pin(0 7) - pin(1 2) - pin(2 6) - pin(3 4) - pin(4 3) - pin(5 1) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((-1720 -2440) (26880 7820)) - - # Nets with their geometries - net(1 name(FB) - rect(diff_cont (20210 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-22130 -2290) (360 360)) - rect(via1 (-305 -305) (250 250)) - rect(via1 (23190 -250) (250 250)) - rect(metal2 (-23765 -325) (23840 400)) - rect(metal2_lbl (-22121 -201) (2 2)) - ) - net(2 name(OSC) - rect(diff_cont (22850 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(via1 (1365 -2235) (250 250)) - rect(metal2 (-325 -325) (400 400)) - rect(metal2_lbl (-201 -201) (2 2)) - ) - net(3 name(VDD) - rect(diff_cont (7810 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (12980 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-21410 -10) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -2600) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -1181) (2 2)) - ) - net(4 name(VSS) - rect(diff_cont (7810 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (12980 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -1330) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -80) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -381) (2 2)) - ) - net(5 - rect(diff_cont (14930 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(6 - rect(diff_cont (9650 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7 - rect(diff_cont (4370 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(8 - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(9 - rect(diff_cont (1730 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(10 - rect(diff_cont (17570 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(11 - rect(diff_cont (12290 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(12 - rect(diff_cont (7010 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(FB)) - pin(2 name(OSC)) - pin(3 name(VDD)) - pin(4 name(VSS)) - - # Subcircuits and their connections - circuit(1 INV2PAIR location(19420 -800) - pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) - pin(4 10) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR location(-1700 -800) - pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) - pin(4 1) - pin(5 9) - pin(6 3) - ) - circuit(3 INV2PAIR location(3580 -800) - pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) - pin(4 9) - pin(5 12) - pin(6 3) - ) - circuit(4 INV2PAIR location(8860 -800) - pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) - pin(4 12) - pin(5 11) - pin(6 3) - ) - circuit(5 INV2PAIR location(14140 -800) - pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) - pin(4 11) - pin(5 10) - pin(6 3) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(2 NMOS - name($3) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) - circuit(RINGO - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('6')) - net(6 name('5')) - net(7 name('101')) - net(8 name('8')) - net(9 name('102')) - net(10 name('7')) - net(11 name('103')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - - # Subcircuits and their connections - circuit(1 INV2PAIR name($1) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 1) - pin(4 5) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR name($2) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 1) - pin(4 1) - pin(5 6) - pin(6 3) - ) - circuit(3 INV2PAIR name($3) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 7) - pin(4 6) - pin(5 8) - pin(6 3) - ) - circuit(4 INV2PAIR name($4) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 9) - pin(4 8) - pin(5 10) - pin(6 3) - ) - circuit(5 INV2PAIR name($5) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 11) - pin(4 10) - pin(5 5) - pin(6 3) - ) - - ) - circuit(INV2PAIRX - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(() INV2PAIRX mismatch - xref( - ) - ) - circuit(INV2 INV2 match - xref( - net(1 1 match) - net(6 6 match) - net(2 2 match) - net(3 3 match) - net(5 5 match) - net(4 4 match) - pin(0 0 match) - pin(5 5 match) - pin(1 1 match) - pin(2 2 match) - pin(4 4 match) - pin(3 3 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(INV2PAIR INV2PAIR nomatch - xref( - net(3 2 mismatch) - net(4 3 mismatch) - net(5 4 match) - net(2 5 mismatch) - net(6 6 match) - net(7 7 mismatch) - net(1 1 mismatch) - pin(2 1 match) - pin(3 2 match) - pin(4 3 match) - pin(1 4 match) - pin(5 5 match) - pin(6 6 match) - pin(0 0 match) - circuit(2 () mismatch) - circuit(1 1 mismatch) - ) - ) - circuit(RINGO RINGO nomatch - xref( - net(() 7 mismatch) - net(() 9 mismatch) - net(() 11 mismatch) - net(() 6 mismatch) - net(() 8 mismatch) - net(5 () mismatch) - net(6 () mismatch) - net(7 () mismatch) - net(9 () mismatch) - net(11 () mismatch) - net(12 () mismatch) - net(10 1 mismatch) - net(8 10 mismatch) - net(1 5 mismatch) - net(2 2 match) - net(3 3 match) - net(4 4 match) - pin(() 0 match) - pin(0 () match) - pin(1 1 match) - pin(2 2 match) - pin(3 3 match) - circuit(() 2 mismatch) - circuit(() 3 mismatch) - circuit(() 4 mismatch) - circuit(() 5 mismatch) - circuit(2 () mismatch) - circuit(3 () mismatch) - circuit(4 () mismatch) - circuit(5 () mismatch) - circuit(1 1 mismatch) - ) - ) -) diff --git a/testdata/algo/lvs_test2b_au.lvsdb.1 b/testdata/algo/lvs_test2b_au.lvsdb.1 index 74daf3f76..4fe56ed6c 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.1 +++ b/testdata/algo/lvs_test2b_au.lvsdb.1 @@ -268,24 +268,6 @@ layout( # Nets with their geometries net(1 name(BULK)) net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 rect(diff_cont (4230 3290) (220 220)) rect(diff_cont (-220 180) (220 220)) rect(diff_cont (-220 180) (220 220)) @@ -307,7 +289,7 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) - net(4 + net(3 rect(diff_cont (4230 890) (220 220)) rect(diff_cont (-220 -620) (220 220)) rect(diff_cont (-220 -620) (220 220)) @@ -329,6 +311,24 @@ layout( rect(metal1 (-3000 -1560) (360 1560)) rect(metal1 (-360 -1560) (360 1560)) ) + net(4 + rect(diff_cont (790 890) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + ) net(5) net(6 rect(diff_cont (3430 890) (220 220)) @@ -363,17 +363,17 @@ layout( circuit(1 INV2 location(1700 800) pin(0 7) pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) + pin(2 4) + pin(3 3) + pin(4 2) pin(5 1) ) circuit(2 INV2 location(4340 800) pin(0 7) - pin(1 2) + pin(1 4) pin(2 6) - pin(3 4) - pin(4 3) + pin(3 3) + pin(4 2) pin(5 1) ) @@ -808,45 +808,45 @@ layout( # Subcircuits and their connections circuit(1 INV2PAIR location(19420 -800) pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 1) pin(4 10) pin(5 2) pin(6 3) ) circuit(2 INV2PAIR location(-1700 -800) pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 8) pin(4 1) pin(5 9) pin(6 3) ) circuit(3 INV2PAIR location(3580 -800) pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 7) pin(4 9) pin(5 12) pin(6 3) ) circuit(4 INV2PAIR location(8860 -800) pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 6) pin(4 12) pin(5 11) pin(6 3) ) circuit(5 INV2PAIR location(14140 -800) pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) + pin(1 3) + pin(2 4) + pin(3 5) pin(4 11) pin(5 10) pin(6 3) @@ -1070,17 +1070,17 @@ xref( ) circuit(INV2PAIR INV2PAIR nomatch xref( - net(3 2 mismatch) - net(4 3 mismatch) + net(2 2 mismatch) + net(3 3 mismatch) net(5 4 match) - net(2 5 mismatch) + net(4 5 mismatch) net(6 6 match) net(7 7 mismatch) net(1 1 mismatch) - pin(2 1 match) - pin(3 2 match) + pin(1 1 match) + pin(2 2 match) pin(4 3 match) - pin(1 4 match) + pin(3 4 match) pin(5 5 match) pin(6 6 match) pin(0 0 match) diff --git a/testdata/algo/lvs_test2b_au.lvsdb.2 b/testdata/algo/lvs_test2b_au.lvsdb.2 deleted file mode 100644 index 92aad1228..000000000 --- a/testdata/algo/lvs_test2b_au.lvsdb.2 +++ /dev/null @@ -1,1126 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(bulk '1/0') - layer(nwell '1/0') - layer(poly '3/0') - layer(poly_lbl '3/1') - layer(diff_cont '4/0') - layer(poly_cont '5/0') - layer(metal1 '6/0') - layer(metal1_lbl '6/1') - layer(via1 '7/0') - layer(metal2 '8/0') - layer(metal2_lbl '8/1') - layer(ntie) - layer(psd) - layer(ptie) - layer(nsd) - - # Mask layer connectivity - connect(nwell nwell ntie) - connect(poly poly poly_lbl poly_cont) - connect(poly_lbl poly) - connect(diff_cont diff_cont metal1 ntie psd ptie nsd) - connect(poly_cont poly poly_cont metal1) - connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) - connect(metal1_lbl metal1) - connect(via1 metal1 via1 metal2) - connect(metal2 via1 metal2 metal2_lbl) - connect(metal2_lbl metal2) - connect(ntie nwell diff_cont ntie) - connect(psd diff_cont psd) - connect(ptie diff_cont ptie) - connect(nsd diff_cont nsd) - - # Global nets and connectivity - global(bulk BULK) - global(ptie BULK) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(psd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (550 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(psd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(psd (125 -875) (525 1750)) - ) - terminal(B - rect(nwell (-125 -875) (250 1750)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(nsd (-650 -875) (525 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (550 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(nsd (-675 -875) (550 1750)) - ) - terminal(G - rect(poly (-125 -875) (250 1750)) - ) - terminal(D - rect(nsd (125 -875) (525 1750)) - ) - terminal(B - rect(bulk (-125 -875) (250 1750)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Circuit boundary - rect((-1700 -2440) (3100 7820)) - - # Nets with their geometries - net(1 - rect(nwell (-1400 1800) (2800 3580)) - rect(diff_cont (-1510 -650) (220 220)) - rect(ntie (-510 -450) (800 680)) - ) - net(2 name(IN) - rect(poly (-525 -250) (250 2500)) - rect(poly (-1425 -630) (2100 360)) - rect(poly (-125 -2230) (250 2500)) - rect(poly (-1050 -3850) (250 2400)) - rect(poly (550 1200) (250 2400)) - rect(poly (-250 -6000) (250 2400)) - rect(poly (-1050 1200) (250 2400)) - rect(poly_lbl (-526 -2601) (2 2)) - rect(poly_cont (-831 -111) (220 220)) - ) - net(3 name(OUT) - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (1310 -3710) (360 2220)) - rect(metal1 (-1900 -800) (2220 360)) - rect(metal1 (-2280 -2400) (360 2840)) - rect(metal1 (-360 -3600) (360 1560)) - rect(metal1 (1240 2040) (360 1560)) - rect(metal1 (-360 -5160) (360 1560)) - rect(metal1 (-1960 2040) (360 1560)) - rect(metal1_lbl (1419 -2181) (2 2)) - rect(psd (-1851 524) (525 1750)) - rect(psd (1050 -1750) (525 1750)) - rect(nsd (-2100 -5350) (525 1750)) - rect(nsd (1050 -1750) (525 1750)) - ) - net(4 name(VSS) - rect(diff_cont (-110 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-290 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -705) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 -1450) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -775) (2800 1700)) - rect(metal2_lbl (-161 -541) (2 2)) - rect(nsd (-1516 -1186) (550 1750)) - ) - net(5 name(VDD) - rect(diff_cont (-110 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-290 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(via1 (-305 -1505) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(via1 (-250 150) (250 250)) - rect(metal2 (-1525 -1575) (2800 1700)) - rect(metal2_lbl (-151 -1251) (2 2)) - rect(psd (-1526 -476) (550 1750)) - ) - net(6 name(BULK) - rect(diff_cont (-110 -2160) (220 220)) - rect(ptie (-510 -450) (800 680)) - ) - - # Outgoing pins and their connections to nets - pin(1) - pin(2 name(IN)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5 name(VDD)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 3200) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(2 D$NMOS - device(D$NMOS$1 location(800 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(-400 -400) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Circuit boundary - rect((0 -1640) (5740 7820)) - - # Nets with their geometries - net(1 name(BULK)) - net(2 - rect(diff_cont (790 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 - rect(diff_cont (4230 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (2350 -1490) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(4 - rect(diff_cont (4230 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (2350 -290) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - ) - net(5) - net(6 - rect(diff_cont (3430 890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7) - - # Outgoing pins and their connections to nets - pin(1 name(BULK)) - pin(2) - pin(3) - pin(4) - pin(5) - pin(6) - pin(7) - - # Subcircuits and their connections - circuit(1 INV2 location(1700 800) - pin(0 7) - pin(1 5) - pin(2 2) - pin(3 4) - pin(4 3) - pin(5 1) - ) - circuit(2 INV2 location(4340 800) - pin(0 7) - pin(1 2) - pin(2 6) - pin(3 4) - pin(4 3) - pin(5 1) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((-1720 -2440) (26880 7820)) - - # Nets with their geometries - net(1 name(FB) - rect(diff_cont (20210 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-22130 -2290) (360 360)) - rect(via1 (-305 -305) (250 250)) - rect(via1 (23190 -250) (250 250)) - rect(metal2 (-23765 -325) (23840 400)) - rect(metal2_lbl (-22121 -201) (2 2)) - ) - net(2 name(OSC) - rect(diff_cont (22850 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(via1 (1365 -2235) (250 250)) - rect(metal2 (-325 -325) (400 400)) - rect(metal2_lbl (-201 -201) (2 2)) - ) - net(3 name(VDD) - rect(diff_cont (7810 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (12980 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (7700 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-2860 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -1420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-21410 -10) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -2600) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -1181) (2 2)) - ) - net(4 name(VSS) - rect(diff_cont (7810 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (12980 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 980) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -1330) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -80) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (12840 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (7560 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal1 (-3000 -1560) (360 1560)) - rect(metal1 (-360 -1560) (360 1560)) - rect(metal2_lbl (-21301 -381) (2 2)) - ) - net(5 - rect(diff_cont (14930 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(6 - rect(diff_cont (9650 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7 - rect(diff_cont (4370 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(8 - rect(diff_cont (-910 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(9 - rect(diff_cont (1730 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(10 - rect(diff_cont (17570 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(11 - rect(diff_cont (12290 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(12 - rect(diff_cont (7010 90) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (1380 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3820) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-1820 3380) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(FB)) - pin(2 name(OSC)) - pin(3 name(VDD)) - pin(4 name(VSS)) - - # Subcircuits and their connections - circuit(1 INV2PAIR location(19420 -800) - pin(0 4) - pin(1 1) - pin(2 3) - pin(3 4) - pin(4 10) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR location(-1700 -800) - pin(0 4) - pin(1 8) - pin(2 3) - pin(3 4) - pin(4 1) - pin(5 9) - pin(6 3) - ) - circuit(3 INV2PAIR location(3580 -800) - pin(0 4) - pin(1 7) - pin(2 3) - pin(3 4) - pin(4 9) - pin(5 12) - pin(6 3) - ) - circuit(4 INV2PAIR location(8860 -800) - pin(0 4) - pin(1 6) - pin(2 3) - pin(3 4) - pin(4 12) - pin(5 11) - pin(6 3) - ) - circuit(5 INV2PAIR location(14140 -800) - pin(0 4) - pin(1 5) - pin(2 3) - pin(3 4) - pin(4 11) - pin(5 10) - pin(6 3) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(INV2 - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 5) - terminal(B 1) - ) - device(2 NMOS - name($3) - param(L 0.25) - param(W 3.5) - param(AS 1.4) - param(AD 1.4) - param(PS 6.85) - param(PD 6.85) - terminal(S 3) - terminal(G 2) - terminal(D 4) - terminal(B 6) - ) - - ) - circuit(INV2PAIR - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) - circuit(RINGO - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('6')) - net(6 name('5')) - net(7 name('101')) - net(8 name('8')) - net(9 name('102')) - net(10 name('7')) - net(11 name('103')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - - # Subcircuits and their connections - circuit(1 INV2PAIR name($1) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 1) - pin(4 5) - pin(5 2) - pin(6 3) - ) - circuit(2 INV2PAIR name($2) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 1) - pin(4 1) - pin(5 6) - pin(6 3) - ) - circuit(3 INV2PAIR name($3) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 7) - pin(4 6) - pin(5 8) - pin(6 3) - ) - circuit(4 INV2PAIR name($4) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 9) - pin(4 8) - pin(5 10) - pin(6 3) - ) - circuit(5 INV2PAIR name($5) - pin(0 4) - pin(1 3) - pin(2 4) - pin(3 11) - pin(4 10) - pin(5 5) - pin(6 3) - ) - - ) - circuit(INV2PAIRX - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(() INV2PAIRX mismatch - xref( - ) - ) - circuit(INV2 INV2 match - xref( - net(1 1 match) - net(6 6 match) - net(2 2 match) - net(3 3 match) - net(5 5 match) - net(4 4 match) - pin(0 0 match) - pin(5 5 match) - pin(1 1 match) - pin(2 2 match) - pin(4 4 match) - pin(3 3 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INV2PAIR INV2PAIR nomatch - xref( - net(3 2 mismatch) - net(4 3 mismatch) - net(5 4 match) - net(2 5 mismatch) - net(6 6 match) - net(7 7 mismatch) - net(1 1 mismatch) - pin(2 1 match) - pin(3 2 match) - pin(4 3 match) - pin(1 4 match) - pin(5 5 match) - pin(6 6 match) - pin(0 0 match) - circuit(2 () mismatch) - circuit(1 1 mismatch) - ) - ) - circuit(RINGO RINGO nomatch - xref( - net(() 7 mismatch) - net(() 9 mismatch) - net(() 11 mismatch) - net(() 6 mismatch) - net(() 8 mismatch) - net(5 () mismatch) - net(6 () mismatch) - net(7 () mismatch) - net(9 () mismatch) - net(11 () mismatch) - net(12 () mismatch) - net(10 1 mismatch) - net(8 10 mismatch) - net(1 5 mismatch) - net(2 2 match) - net(3 3 match) - net(4 4 match) - pin(() 0 match) - pin(0 () match) - pin(1 1 match) - pin(2 2 match) - pin(3 3 match) - circuit(() 2 mismatch) - circuit(() 3 mismatch) - circuit(() 4 mismatch) - circuit(() 5 mismatch) - circuit(2 () mismatch) - circuit(3 () mismatch) - circuit(4 () mismatch) - circuit(5 () mismatch) - circuit(1 1 mismatch) - ) - ) -) From 07daed2878b51fab3f9d4756ef337727cb236bb6 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 00:24:17 +0100 Subject: [PATCH 11/21] WIP: further updates of test data. --- testdata/algo/l2n_writer_au_2.gds | Bin 13338 -> 13334 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/testdata/algo/l2n_writer_au_2.gds b/testdata/algo/l2n_writer_au_2.gds index 35478aff1ecc7976d0b904ba1589ad5600a61d8c..975f2f836c07de33c003ab841cc50b87fd5e7fd1 100644 GIT binary patch delta 1652 zcmaizze@sP7{{MG&$|>;IJv_}H1)J0$o#RDMEE26Ws)KylsG9#uC=*01o1*cLqh~@ zA>7sw)mBq~KoHb!jRg%^A{g9Pw--Lo=leYG%k!SrPwIXWiRVk?=6LCiY~&y!mBNGP zV}C#~2IVRMPZeXpQXEj&HHVy89yu30a$F|l9GQ^A3&=Tuq$9k5o4%S+pQ4D!qqq&y z79>QjBs9VK80w>15IMAfKKi#MZ34p;$KQ>KUbcrhfX*B!Pydt?pq0L=exbmU%WG~K z?kU+sF{NcUHuGA91c}IPhRaUYe(lK0ztr5n)Yjm?89eu5e~U-Pb_XbIEoJjGva&ls zHeIM_EAeivl}MJ^z9(n=-t5_v0Hp0zSkha9bPp1REl*)jVGl#;nlCye`4ZBOFKO)Q z8NU;32Wtiz#uDp5($pG0xKO>9kHpx=^aOJTGa$VgTmg13Qr5B>>92a5Ln3vtg%0JYO*SG)x delta 1658 zcmaizKS)AR7{$N$d_Ggm$WkoC|5^~FzM!QjAc`dIad9O^+I^-G`7fZ+Y%>%IS`_uaMa6c4m*50KBs(m5JfX_Do1 zB475U=G%LbWFTVujx7J)?8y-UB;>NNn6uc2-u0ooeRTJ(ey%CE0<_2O6+l|=0&)Y%cmQcCh^WoLg2Zp68fOq< yo55Qrf5UbHI~yjKm@D8=OQ9$_Y$Lp5G@1WG$efBD43bgS1W^f}Dh}41D}4iypwiI* From 87e658acf01e4fa2b2ba0b1a870bb939cddd17a3 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 00:48:11 +0100 Subject: [PATCH 12/21] WIP: finalized refactoring. --- src/db/db/dbHierNetworkProcessor.cc | 408 ++-------------------------- src/db/db/dbHierNetworkProcessor.h | 16 +- src/db/db/dbNetlistExtractor.cc | 5 +- 3 files changed, 28 insertions(+), 401 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 1d9d5b253..7af394f59 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -1189,7 +1189,7 @@ public: */ void finish (const db::Instance *i, unsigned int /*p1*/) { - add_single_inst (*i); + consider_single_inst (*i); } /** @@ -1295,161 +1295,6 @@ private: std::map > > m_interaction_cache_for_clusters; instance_interaction_cache_type *mp_instance_interaction_cache; -#if 0 // @@@ - /** - * @brief Handles the cluster interactions between two instances or instance arrays - * @param common The region under investigation (seen from the top level) - * @param i1 The index of the child cell 1 - * @param p1 The instantiation path to the child cell (not including i1) - * @param t1 The accumulated transformation of the path, not including i1 - * @param i2 The index of the child cell 2 - * @param p2 The instantiation path to the child cell (not including i2) - * @param t2 The accumulated transformation of the path, not including i2 - */ - void add_pair (const box_type &common, const db::Instance &i1, const std::vector &p1, const db::ICplxTrans &t1, const db::Instance &i2, const std::vector &p2, const db::ICplxTrans &t2, std::list > &interacting_clusters_out) - { - if (is_breakout_cell (mp_breakout_cells, i1.cell_index ()) || is_breakout_cell (mp_breakout_cells, i2.cell_index ())) { - return; - } - - box_type bb1 = (*mp_cbc) (i1.cell_index ()); - box_type b1 = i1.cell_inst ().bbox (*mp_cbc).transformed (t1); - - box_type bb2 = (*mp_cbc) (i2.cell_index ()); - box_type b2 = i2.cell_inst ().bbox (*mp_cbc).transformed (t2); - - box_type common_all = common & b1 & b2; - - if (common_all.empty ()) { - return; - } - - db::ICplxTrans tt2 = t2 * i2.complex_trans (); - db::ICplxTrans tt1 = t1 * i1.complex_trans (); - - db::ICplxTrans tt21 = tt1.inverted () * tt2; - InstanceToInstanceInteraction ii_key (i1.cell_index (), i1.cell_inst ().delegate (), i2.cell_index (), i2.cell_inst ().delegate (), tt21); - -#if 0 // @@@ - instance_interaction_cache_type::iterator ii = mp_instance_interaction_cache->find (ii_key); - if (ii != mp_instance_interaction_cache->end ()) { - // take from cache if possible - --> problem: cluster pairs need to be relative to the initial cell, hence we can't cache the target cluster. only the source one!!! - for (cluster_instance_pair_list_type::const_iterator ic = ii->second.second.begin (); ic != ii->second.second.end (); ++ic) { - interacting_clusters_out.push_back (std::pair ()); - interacting_clusters_out.back ().first = make_path (ic->first.id (), p1); - interacting_clusters_out.back ().second = make_path (ic->second.id (), p2); - } - return; - } - std::list > &interacting_clusters = mp_instance_interaction_cache->insert (std::make_pair (ii_key, std::make_pair (tt1, cluster_instance_pair_list_type ()))).first->second.second; - -#endif - - std::list > interacting_clusters; // @@@ - - if (false /*@@@*/&& i1.size () == 1 && i2.size () == 1) { - - // single-to-single instance interactions - - // TODO: can't we just add the new item to the path and remove it later? - std::vector pp1; - pp1.reserve (p1.size () + 1); - pp1.insert (pp1.end (), p1.begin (), p1.end ()); - pp1.push_back (ClusterInstElement (i1.cell_index (), i1.complex_trans (), i1.prop_id ())); - - // skip interactions between identical instances (duplicate instance removal) - if (i1.cell_index () != i2.cell_index () || tt1 != tt2) { - - std::vector pp2; - pp2.reserve (p2.size () + 1); - pp2.insert (pp2.end (), p2.begin (), p2.end ()); - pp2.push_back (ClusterInstElement (i2.cell_index (), i2.complex_trans (), i2.prop_id ())); - - add_single_pair (common_all, i1.cell_index (), pp1, tt1, i2.cell_index (), pp2, tt2, interacting_clusters); - - // dive into cell of i2 - const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); - for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common_all.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - add_pair (common_all, i1, p1, t1, *jj2, pp2, tt2, interacting_clusters); - } - - } - - // dive into cell of i1 - const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); - for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common_all.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { - add_pair (common_all, *jj1, pp1, tt1, i2, p2, t2, interacting_clusters); - } - - } else { - - // array interactions - - db::ICplxTrans t1i = t1.inverted (); - db::ICplxTrans t2i = t2.inverted (); - - for (db::CellInstArray::iterator ii1 = i1.begin_touching (common_all.transformed (t1i), mp_layout); ! ii1.at_end (); ++ii1) { - - db::ICplxTrans tt1 = t1 * i1.complex_trans (*ii1); - box_type ib1 = bb1.transformed (tt1); - - std::vector pp1; - pp1.reserve (p1.size () + 1); - pp1.insert (pp1.end (), p1.begin (), p1.end ()); - pp1.push_back (ClusterInstElement (i1.cell_index (), i1.complex_trans (*ii1), i1.prop_id ())); - - for (db::CellInstArray::iterator ii2 = i2.begin_touching (ib1.transformed (t2i), mp_layout); ! ii2.at_end (); ++ii2) { - - db::ICplxTrans tt2 = t2 * i2.complex_trans (*ii2); - if (i1.cell_index () == i2.cell_index () && tt1 == tt2) { - // skip interactions between identical instances (duplicate instance removal) - continue; - } - - box_type ib2 = bb2.transformed (tt2); - - box_type common12 = ib1 & ib2 & common; - - if (! common12.empty ()) { - - std::vector pp2; - pp2.reserve (p2.size () + 1); - pp2.insert (pp2.end (), p2.begin (), p2.end ()); - pp2.push_back (ClusterInstElement (i2.cell_index (), i2.complex_trans (*ii2), i2.prop_id ())); - - add_single_pair (common12, i1.cell_index (), pp1, tt1, i2.cell_index (), pp2, tt2, interacting_clusters); - - // dive into cell of ii2 - const db::Cell &cell2 = mp_layout->cell (i2.cell_index ()); - for (db::Cell::touching_iterator jj2 = cell2.begin_touching (common12.transformed (tt2.inverted ())); ! jj2.at_end (); ++jj2) { - add_pair (common12, i1, p1, t1, *jj2, pp2, tt2, interacting_clusters); - } - - } - - } - - box_type common1 = ib1 & b2 & common; - - if (! common1.empty ()) { - - // dive into cell of ii1 - const db::Cell &cell1 = mp_layout->cell (i1.cell_index ()); - for (db::Cell::touching_iterator jj1 = cell1.begin_touching (common1.transformed (tt1.inverted ())); ! jj1.at_end (); ++jj1) { - add_pair (common1, *jj1, pp1, tt1, i2, p2, t2, interacting_clusters); - } - - } - - } - - } - - interacting_clusters_out.insert (interacting_clusters_out.end (), interacting_clusters.begin (), interacting_clusters.end ()); - } -#endif - /** * @brief Investigate a pair of instances * @@ -1500,7 +1345,7 @@ private: if (ii != mp_instance_interaction_cache->end ()) { // use cached interactions - interacting_clusters = ii->second.second; + interacting_clusters = ii->second; for (std::list >::iterator i = interacting_clusters.begin (); i != interacting_clusters.end (); ++i) { // translate the property IDs i->first.set_inst_prop_id (i1.prop_id ()); @@ -1518,7 +1363,7 @@ private: db::ICplxTrans t1i = t1.inverted (); db::ICplxTrans t2i = t2.inverted (); - // @@@ optimize for single inst? + // TODO: optimize for single inst? for (db::CellInstArray::iterator ii1 = i1element.at_end () ? i1.begin_touching (common_all.transformed (t1i), mp_layout) : i1element; ! ii1.at_end (); ++ii1) { db::ICplxTrans i1t = i1.complex_trans (*ii1); @@ -1594,99 +1439,20 @@ private: } - std::pair &cached = (*mp_instance_interaction_cache) [ii_key]; - cached.first = i1.complex_trans (); // @@@ remove or twofold transformation - cached.second = interacting_clusters; + cluster_instance_pair_list_type &cached = (*mp_instance_interaction_cache) [ii_key]; + cached = interacting_clusters; // normalize transformations in cache db::ICplxTrans i1ti = i1t.inverted (), i2ti = i2t.inverted (); - for (std::list >::iterator i = cached.second.begin (); i != cached.second.end (); ++i) { + for (std::list >::iterator i = cached.begin (); i != cached.end (); ++i) { i->first.transform (i1ti); i->second.transform (i2ti); } } /** - * @brief Handles the cluster interactions between two specific instances - * @param common The region under investigation (seen from the top level) - * @param ci1 The cell index of the child cell 1 - * @param p1 The instantiation path to the child cell (last element is the instance to ci1) - * @param t1 The accumulated transformation of the path p1 - * @param ci2 The cell index of the child cell 2 - * @param p2 The instantiation path to the child cell (last element is the instance to ci2) - * @param t2 The accumulated transformation of the path p2 + * @brief Computes a list of interacting clusters for two instances */ - // @@@ remove - void add_single_pair (const box_type &common, - db::cell_index_type ci1, const std::vector &p1, const db::ICplxTrans &t1, - db::cell_index_type ci2, const std::vector &p2, const db::ICplxTrans &t2, - cluster_instance_pair_list_type &interacting_clusters) - { - if (is_breakout_cell (mp_breakout_cells, ci1) || is_breakout_cell (mp_breakout_cells, ci2)) { - return; - } - - db::ICplxTrans t1i = t1.inverted (); - db::ICplxTrans t2i = t2.inverted (); - db::ICplxTrans t21 = t1i * t2; - - box_type common2 = common.transformed (t2i); - - // NOTE: make_path may disturb the iteration (because of modification), hence - // we first collect and then process the interactions. - const std::vector > *interactions; - - InteractionKeyForClustersType ikey (ci1, ci2, t21, common2); - - typename std::map > >::const_iterator ici = m_interaction_cache_for_clusters.find (ikey); - if (ici != m_interaction_cache_for_clusters.end ()) { - - interactions = &ici->second; - - } else { - - const db::Cell &cell2 = mp_layout->cell (ci2); - - const db::local_clusters &cl1 = mp_tree->clusters_per_cell (ci1); - const db::local_clusters &cl2 = mp_tree->clusters_per_cell (ci2); - - std::vector > new_interactions; - db::ICplxTrans t12 = t2i * t1; - - for (typename db::local_clusters::touching_iterator i = cl1.begin_touching (common2.transformed (t21)); ! i.at_end (); ++i) { - - // skip the test, if this cluster doesn't interact with the whole cell2 - if (! i->interacts (cell2, t21, *mp_conn)) { - continue; - } - - box_type bc2 = (common2 & i->bbox ().transformed (t12)); - for (typename db::local_clusters::touching_iterator j = cl2.begin_touching (bc2); ! j.at_end (); ++j) { - - if (i->interacts (*j, t21, *mp_conn)) { - new_interactions.push_back (std::make_pair (i->id (), j->id ())); - } - - } - - } - - std::vector > &out = m_interaction_cache_for_clusters [ikey]; - out = new_interactions; - interactions = &out; - - } - - for (std::vector >::const_iterator ii = interactions->begin (); ii != interactions->end (); ++ii) { - - ClusterInstance k1 = make_path (ii->first, p1); - ClusterInstance k2 = make_path (ii->second, p2); - - interacting_clusters.push_back (std::make_pair (k1, k2)); - - } - } - const std::vector > & compute_instance_interactions (const box_type &common, db::cell_index_type ci1, const db::ICplxTrans &t1, @@ -1746,7 +1512,7 @@ private: /** * @brief Single instance treatment */ - void add_single_inst (const db::Instance &i) + void consider_single_inst (const db::Instance &i) { if (is_breakout_cell (mp_breakout_cells, i.cell_index ())) { return; @@ -1981,18 +1747,11 @@ private: } /** - * @brief Makes a valid path to a child cluster + * @brief Makes cluster connections from all parents of a cell into this cell and to the given cluster * - * Cluster connections can only cross one level of hierarchy. This method - * creates necessary dummy entries for the given path. + * After calling this method, the cluster instance in ci is guaranteed to have connections from all + * parent cells. One of these connections represents the instance ci. */ - // @@@ remove - ClusterInstance make_path (id_type id, const std::vector &path) const - { - return mp_tree->make_path (*mp_layout, *mp_cell, id, path); - } - - // @@@ void propagate_cluster_inst (ClusterInstance &ci, db::cell_index_type pci, const db::ICplxTrans &trans, db::properties_id_type prop_id) const { size_t id_new = mp_tree->propagate_cluster_inst (*mp_layout, *mp_cell, ci, pci, true); @@ -2142,134 +1901,6 @@ hier_clusters::propagate_cluster_inst (const db::Layout &layout, const db::Ce return id_new; } -template -ClusterInstance -hier_clusters::make_path (const db::Layout &layout, const db::Cell &cell, size_t id, const std::vector &path) -{ - std::vector::const_iterator p = path.end (); - tl_assert (p != path.begin ()); - - while (true) { - - --p; - - ClusterInstance ci (id, p->inst_cell_index (), p->inst_trans (), p->inst_prop_id ()); - if (p == path.begin ()) { - - // if we're attaching to a child which is root yet, we need to promote the - // cluster to the parent in all places - connected_clusters &child_cc = clusters_per_cell (p->inst_cell_index ()); - if (child_cc.is_root (id)) { - - std::set > seen; // to avoid duplicate connections - - const db::Cell &child_cell = layout.cell (p->inst_cell_index ()); - for (db::Cell::parent_inst_iterator pi = child_cell.begin_parent_insts (); ! pi.at_end (); ++pi) { - - db::Instance child_inst = pi->child_inst (); - - connected_clusters &parent_cc = clusters_per_cell (pi->parent_cell_index ()); - for (db::CellInstArray::iterator pii = child_inst.begin (); ! pii.at_end (); ++pii) { - - ClusterInstance ci2 (id, child_inst.cell_index (), child_inst.complex_trans (*pii), child_inst.prop_id ()); - if ((cell.cell_index () != pi->parent_cell_index () || ci != ci2) && seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { - - size_t id_dummy; - - const typename db::local_cluster::global_nets &gn = child_cc.cluster_by_id (id).get_global_nets (); - if (gn.empty ()) { - id_dummy = parent_cc.insert_dummy (); - } else { - local_cluster *lc = parent_cc.insert (); - lc->set_global_nets (gn); - id_dummy = lc->id (); - } - - parent_cc.add_connection (id_dummy, ci2); - seen.insert (std::make_pair (pi->parent_cell_index (), ci2)); - - } - - } - - } - - child_cc.reset_root (id); - - } - - return ci; - - } - - db::cell_index_type pci = p [-1].inst_cell_index (); - connected_clusters &target_cc = clusters_per_cell (pci); - size_t parent_cluster = target_cc.find_cluster_with_connection (ci); - - if (parent_cluster > 0) { - - // taken parent - id = parent_cluster; - - } else { - - size_t id_new = 0; - - // if we're attaching to a child which is root yet, we need to promote the - // cluster to the parent in all places - connected_clusters &child_cc = clusters_per_cell (p->inst_cell_index ()); - if (child_cc.is_root (id)) { - - std::set > seen; // to avoid duplicate connections - - const db::Cell &child_cell = layout.cell (p->inst_cell_index ()); - for (db::Cell::parent_inst_iterator pi = child_cell.begin_parent_insts (); ! pi.at_end (); ++pi) { - - db::Instance child_inst = pi->child_inst (); - - connected_clusters &parent_cc = clusters_per_cell (pi->parent_cell_index ()); - for (db::CellInstArray::iterator pii = child_inst.begin (); ! pii.at_end (); ++pii) { - - ClusterInstance ci2 (id, child_inst.cell_index (), child_inst.complex_trans (*pii), child_inst.prop_id ()); - if (seen.find (std::make_pair (pi->parent_cell_index (), ci2)) == seen.end ()) { - - size_t id_dummy; - - const typename db::local_cluster::global_nets &gn = child_cc.cluster_by_id (id).get_global_nets (); - if (gn.empty ()) { - id_dummy = parent_cc.insert_dummy (); - } else { - local_cluster *lc = parent_cc.insert (); - lc->set_global_nets (gn); - id_dummy = lc->id (); - } - - parent_cc.add_connection (id_dummy, ci2); - seen.insert (std::make_pair (pi->parent_cell_index (), ci2)); - - if (pci == pi->parent_cell_index () && ci == ci2) { - id_new = id_dummy; - } - - } - - } - - } - - child_cc.reset_root (id); - - } - - // no parent -> create vertical connector - id = id_new; - tl_assert (id != 0); - - } - - } -} - template void hier_clusters::do_build (cell_clusters_box_converter &cbc, const db::Layout &layout, const db::Cell &cell, db::ShapeIterator::flags_type shape_flags, const db::Connectivity &conn, const tl::equivalence_clusters *attr_equivalence, const std::set *breakout_cells) @@ -2562,27 +2193,26 @@ hier_clusters::build_hier_connections (cell_clusters_box_converter &cbc, c // NOTE: don't use the gc pointer - it may become invalid during make_path (will also do a local.insert) size_t gcid = gc->id (); - for (std::set::const_iterator ci = ge->second.begin (); ci != ge->second.end (); ++ci) { + for (std::set::const_iterator i = ge->second.begin (); i != ge->second.end (); ++i) { - if (! ci->has_instance ()) { + if (! i->has_instance ()) { - local.join_cluster_with (gcid, ci->id ()); - local.remove_cluster (ci->id ()); + local.join_cluster_with (gcid, i->id ()); + local.remove_cluster (i->id ()); } else { - std::vector p; - p.push_back (*ci); - ClusterInstance k = make_path (layout, cell, ci->id (), p); + // ensures the cluster is propagated so we can connect it with another + propagate_cluster_inst (layout, cell, *i, cell.cell_index (), false); - size_t other_id = local.find_cluster_with_connection (k); + size_t other_id = local.find_cluster_with_connection (*i); if (other_id == gcid) { // shouldn't happen, but duplicate instances may trigger this } else if (other_id) { local.join_cluster_with (gcid, other_id); local.remove_cluster (other_id); } else { - local.add_connection (gcid, k); + local.add_connection (gcid, *i); } } diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 0f1619aaf..a29dfcce3 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -769,7 +769,6 @@ struct InstanceToInstanceInteraction bool operator== (const InstanceToInstanceInteraction &other) const { - static const db::array_base_ptr_cmp_f arr_less; return ci1 == other.ci1 && ci2 == other.ci2 && t21.equal (other.t21) && equal_array_delegates (array1, other.array1) && equal_array_delegates (array2, other.array2); @@ -799,7 +798,7 @@ struct InstanceToInstanceInteraction db::ICplxTrans t21; }; -typedef std::map > instance_interaction_cache_type; +typedef std::map instance_interaction_cache_type; template class hier_clusters; template class connected_clusters; @@ -974,7 +973,7 @@ class DB_PUBLIC_TEMPLATE hier_clusters { public: typedef typename local_cluster::box_type box_type; - typedef std::map > instance_interaction_cache_type; + typedef std::map instance_interaction_cache_type; /** * @brief Creates an empty set of clusters @@ -1022,15 +1021,12 @@ public: void clear (); /** - * @brief Makes a valid path to a child cluster + * @brief Ensures a cluster instance is connected from all parents of the instantiated cell * - * Cluster connections can only cross one level of hierarchy. This method - * creates necessary dummy entries for the given path. + * If "with_self" is true, the specified instance "ci" is included in the connections. Otherwise + * there is not connection made for this instance. */ - ClusterInstance make_path (const db::Layout &layout, const db::Cell &cell, size_t id, const std::vector &path); - - // @@@ - size_t propagate_cluster_inst (const db::Layout &layout, const Cell &cell, const ClusterInstance &ci, db::cell_index_type pci, bool with_self); + size_t propagate_cluster_inst (const db::Layout &layout, const Cell &cell, const ClusterInstance &ci, db::cell_index_type parent_ci, bool with_self); private: void build_local_cluster (const db::Layout &layout, const db::Cell &cell, db::ShapeIterator::flags_type shape_flags, const db::Connectivity &conn, const tl::equivalence_clusters *attr_equivalence); diff --git a/src/db/db/dbNetlistExtractor.cc b/src/db/db/dbNetlistExtractor.cc index 7dcebd9d7..44f1eac29 100644 --- a/src/db/db/dbNetlistExtractor.cc +++ b/src/db/db/dbNetlistExtractor.cc @@ -159,8 +159,9 @@ NetlistExtractor::extract_nets (const db::DeepShapeStore &dss, unsigned int layo // Make sure we create one subcircuit for each instance of cells which do have circuits // associated. for (db::Cell::const_iterator inst = cell.begin (); ! inst.at_end (); ++inst) { - // @@@ ARRAY EXPANSION!!! - make_subcircuit (circuit, inst->cell_index (), inst->complex_trans (), subcircuits, circuits); + for (db::CellInstArray::iterator ii = inst->begin (); ! ii.at_end (); ++ii) { + make_subcircuit (circuit, inst->cell_index (), inst->complex_trans (*ii), subcircuits, circuits); + } } } From 782f6fe601c172ad54038a8176f8ad694eab7f35 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 01:29:56 +0100 Subject: [PATCH 13/21] BUGFIX: the L2N and LVSDB writer was writing too much Sometimes, shapes from child cells were propagated into parent cells in the L2N and LVSDB output. Because of this fix, many testdata files have to be updated. --- src/db/db/dbHierNetworkProcessor.cc | 11 +- src/db/db/dbHierNetworkProcessor.h | 22 +- src/db/db/dbLayoutToNetlistWriter.cc | 130 +- src/db/db/dbLayoutToNetlistWriter.h | 28 +- .../dbLayoutToNetlistReaderTests.cc | 2 +- testdata/algo/l2n_reader_au_1.gds | Bin 20994 -> 6690 bytes testdata/algo/l2n_reader_au_1b.gds | Bin 7938 -> 434 bytes testdata/algo/l2n_reader_au_1c.gds | Bin 23298 -> 15618 bytes testdata/algo/l2n_reader_au_1d.gds | Bin 10672 -> 2992 bytes testdata/algo/l2n_reader_au_1e.gds | Bin 10768 -> 3088 bytes testdata/algo/l2n_reader_au_1f.gds | Bin 15632 -> 7952 bytes testdata/algo/l2n_writer_au.txt | 262 +--- testdata/algo/l2n_writer_au_2b.txt | 254 +--- testdata/algo/l2n_writer_au_2s.txt | 254 +--- testdata/algo/l2n_writer_au_p.oas | Bin 2370 -> 1578 bytes testdata/algo/l2n_writer_au_p.txt | 262 +--- testdata/algo/l2n_writer_au_s.txt | 262 +--- testdata/algo/lvs_test1_au.lvsdb.1 | 480 +------- testdata/algo/lvs_test1b_au.lvsdb.1 | 480 +------- testdata/algo/lvs_test2_au.lvsdb.1 | 480 +------- testdata/algo/lvs_test2b_au.lvsdb.1 | 480 +------- testdata/algo/meander.gds.gz | Bin 0 -> 337 bytes testdata/lvs/floating.lvsdb | 42 +- testdata/lvs/invchain_cheat.lvsdb | 150 +-- testdata/lvs/ringo_layout_var.lvsdb.1 | 91 +- testdata/lvs/ringo_layout_var.lvsdb.2 | 1076 ----------------- 26 files changed, 350 insertions(+), 4416 deletions(-) create mode 100644 testdata/algo/meander.gds.gz delete mode 100644 testdata/lvs/ringo_layout_var.lvsdb.2 diff --git a/src/db/db/dbHierNetworkProcessor.cc b/src/db/db/dbHierNetworkProcessor.cc index 7af394f59..721d17aac 100644 --- a/src/db/db/dbHierNetworkProcessor.cc +++ b/src/db/db/dbHierNetworkProcessor.cc @@ -2286,8 +2286,8 @@ template class DB_PUBLIC hier_clusters; // recursive_cluster_shape_iterator implementation template -recursive_cluster_shape_iterator::recursive_cluster_shape_iterator (const hier_clusters &hc, unsigned int layer, db::cell_index_type ci, typename local_cluster::id_type id) - : mp_hc (&hc), m_layer (layer), m_id (id) +recursive_cluster_shape_iterator::recursive_cluster_shape_iterator (const hier_clusters &hc, unsigned int layer, db::cell_index_type ci, typename local_cluster::id_type id, const CircuitCallback *callback) + : mp_hc (&hc), m_layer (layer), m_id (id), mp_callback (callback) { if (id == 0) { return; @@ -2352,7 +2352,12 @@ void recursive_cluster_shape_iterator::next_conn () if (m_conn_iter_stack.back ().first != m_conn_iter_stack.back ().second) { const ClusterInstance &cli = *m_conn_iter_stack.back ().first; - down (cli.inst_cell_index (), cli.id (), cli.inst_trans ()); + if (mp_callback && ! mp_callback->new_cell (cli.inst_cell_index ())) { + // skip this cell + ++m_conn_iter_stack.back ().first; + } else { + down (cli.inst_cell_index (), cli.id (), cli.inst_trans ()); + } } else { diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index a29dfcce3..923c57e78 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -1038,6 +1038,25 @@ private: int m_base_verbosity; }; +/** + * @brief A callback function for the recursive cluster shape and cluster iterator selecting cells/circuits + * + * Reimplement the "new_circuit" method to receive a callback on a new cell or circuit. + */ +class DB_PUBLIC CircuitCallback +{ +public: + CircuitCallback () { } + + /** + * @brief This method is called whenever a circuit is entered when descending. + * Return false to skip this circuit and all of it's children. This method is called before the + * new cell is entered. + * @param new_ci The cell index of the cell to enter + */ + virtual bool new_cell (db::cell_index_type /*new_ci*/) const { return true; } +}; + /** * @brief A recursive shape iterator for the shapes of a cluster * @@ -1057,7 +1076,7 @@ public: /** * @brief Constructor */ - recursive_cluster_shape_iterator (const hier_clusters &hc, unsigned int layer, db::cell_index_type ci, typename local_cluster::id_type id); + recursive_cluster_shape_iterator (const hier_clusters &hc, unsigned int layer, db::cell_index_type ci, typename local_cluster::id_type id, const CircuitCallback *callback = 0); /** * @brief Returns a value indicating whether there are any more shapes @@ -1138,6 +1157,7 @@ private: typename db::local_cluster::shape_iterator m_shape_iter; unsigned int m_layer; typename db::local_cluster::id_type m_id; + const CircuitCallback *mp_callback; void next_conn (); void up (); diff --git a/src/db/db/dbLayoutToNetlistWriter.cc b/src/db/db/dbLayoutToNetlistWriter.cc index fad0c3a9f..62c9d6116 100644 --- a/src/db/db/dbLayoutToNetlistWriter.cc +++ b/src/db/db/dbLayoutToNetlistWriter.cc @@ -57,7 +57,7 @@ static const std::string indent2 (" "); template std_writer_impl::std_writer_impl (tl::OutputStream &stream, double dbu, const std::string &progress_description) - : mp_stream (&stream), m_dbu (dbu), + : mp_stream (&stream), m_dbu (dbu), mp_netlist (0), m_progress (progress_description.empty () ? tl::to_string (tr ("Writing L2N database")) : progress_description, 10000) { m_progress.set_format (tl::to_string (tr ("%.0f MB"))); @@ -76,17 +76,51 @@ static std::string name_for_layer (const db::LayoutToNetlist *l2n, unsigned int template void std_writer_impl::write (const db::LayoutToNetlist *l2n) { - write (l2n->netlist (), l2n, false, 0); + try { + + mp_netlist = l2n->netlist (); + mp_l2n = l2n; + + write (false, 0); + + mp_netlist = 0; + mp_l2n = 0; + + } catch (...) { + mp_netlist = 0; + mp_l2n = 0; + throw; + } } template -void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetlist *l2n, bool nested, std::map > *net2id_per_circuit) +void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, bool nested, std::map > *net2id_per_circuit) +{ + try { + + mp_netlist = netlist; + mp_l2n = l2n; + + write (nested, net2id_per_circuit); + + mp_netlist = 0; + mp_l2n = 0; + + } catch (...) { + mp_netlist = 0; + mp_l2n = 0; + throw; + } +} + +template +void std_writer_impl::write (bool nested, std::map > *net2id_per_circuit) { bool any = false; const int version = 0; - const db::Layout *ly = l2n ? l2n->internal_layout () : 0; + const db::Layout *ly = mp_l2n ? mp_l2n->internal_layout () : 0; const std::string indent (nested ? indent1 : ""); if (! nested) { @@ -97,11 +131,11 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl *mp_stream << indent << Keys::version_key << "(" << version << ")" << endl; } if (ly) { - *mp_stream << indent << Keys::top_key << "(" << tl::to_word_or_quoted_string (ly->cell_name (l2n->internal_top_cell ()->cell_index ())) << ")" << endl; + *mp_stream << indent << Keys::top_key << "(" << tl::to_word_or_quoted_string (ly->cell_name (mp_l2n->internal_top_cell ()->cell_index ())) << ")" << endl; *mp_stream << indent << Keys::unit_key << "(" << m_dbu << ")" << endl; } - if (l2n) { + if (mp_l2n) { if (! Keys::is_short ()) { *mp_stream << endl << indent << "# Layer section" << endl; @@ -111,8 +145,8 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl if (! Keys::is_short ()) { *mp_stream << endl << indent << "# Mask layers" << endl; } - for (db::Connectivity::layer_iterator l = l2n->connectivity ().begin_layers (); l != l2n->connectivity ().end_layers (); ++l) { - *mp_stream << indent << Keys::layer_key << "(" << name_for_layer (l2n, *l); + for (db::Connectivity::layer_iterator l = mp_l2n->connectivity ().begin_layers (); l != mp_l2n->connectivity ().end_layers (); ++l) { + *mp_stream << indent << Keys::layer_key << "(" << name_for_layer (mp_l2n, *l); db::LayerProperties lp = ly->get_properties (*l); if (! lp.is_null ()) { *mp_stream << " " << tl::to_word_or_quoted_string (lp.to_string ()); @@ -124,14 +158,14 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl if (! Keys::is_short ()) { *mp_stream << endl << indent << "# Mask layer connectivity" << endl; } - for (db::Connectivity::layer_iterator l = l2n->connectivity ().begin_layers (); l != l2n->connectivity ().end_layers (); ++l) { + for (db::Connectivity::layer_iterator l = mp_l2n->connectivity ().begin_layers (); l != mp_l2n->connectivity ().end_layers (); ++l) { - db::Connectivity::layer_iterator ce = l2n->connectivity ().end_connected (*l); - db::Connectivity::layer_iterator cb = l2n->connectivity ().begin_connected (*l); + db::Connectivity::layer_iterator ce = mp_l2n->connectivity ().end_connected (*l); + db::Connectivity::layer_iterator cb = mp_l2n->connectivity ().begin_connected (*l); if (cb != ce) { - *mp_stream << indent << Keys::connect_key << "(" << name_for_layer (l2n, *l); - for (db::Connectivity::layer_iterator c = l2n->connectivity ().begin_connected (*l); c != ce; ++c) { - *mp_stream << " " << name_for_layer (l2n, *c); + *mp_stream << indent << Keys::connect_key << "(" << name_for_layer (mp_l2n, *l); + for (db::Connectivity::layer_iterator c = mp_l2n->connectivity ().begin_connected (*l); c != ce; ++c) { + *mp_stream << " " << name_for_layer (mp_l2n, *c); } *mp_stream << ")" << endl; m_progress.set (mp_stream->pos ()); @@ -140,10 +174,10 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl } any = false; - for (db::Connectivity::layer_iterator l = l2n->connectivity ().begin_layers (); l != l2n->connectivity ().end_layers (); ++l) { + for (db::Connectivity::layer_iterator l = mp_l2n->connectivity ().begin_layers (); l != mp_l2n->connectivity ().end_layers (); ++l) { - db::Connectivity::global_nets_iterator ge = l2n->connectivity ().end_global_connections (*l); - db::Connectivity::global_nets_iterator gb = l2n->connectivity ().begin_global_connections (*l); + db::Connectivity::global_nets_iterator ge = mp_l2n->connectivity ().end_global_connections (*l); + db::Connectivity::global_nets_iterator gb = mp_l2n->connectivity ().begin_global_connections (*l); if (gb != ge) { if (! any) { if (! Keys::is_short ()) { @@ -151,9 +185,9 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl } any = true; } - *mp_stream << indent << Keys::global_key << "(" << name_for_layer (l2n, *l); + *mp_stream << indent << Keys::global_key << "(" << name_for_layer (mp_l2n, *l); for (db::Connectivity::global_nets_iterator g = gb; g != ge; ++g) { - *mp_stream << " " << tl::to_word_or_quoted_string (l2n->connectivity ().global_net_name (*g)); + *mp_stream << " " << tl::to_word_or_quoted_string (mp_l2n->connectivity ().global_net_name (*g)); } *mp_stream << ")" << endl; m_progress.set (mp_stream->pos ()); @@ -163,9 +197,9 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl } - if (nl->begin_device_classes () != nl->end_device_classes () && ! Keys::is_short ()) { + if (mp_netlist->begin_device_classes () != mp_netlist->end_device_classes () && ! Keys::is_short ()) { *mp_stream << endl << indent << "# Device class section" << endl; - for (db::Netlist::const_device_class_iterator c = nl->begin_device_classes (); c != nl->end_device_classes (); ++c) { + for (db::Netlist::const_device_class_iterator c = mp_netlist->begin_device_classes (); c != mp_netlist->end_device_classes (); ++c) { db::DeviceClassTemplateBase *temp = db::DeviceClassTemplateBase::is_a (c.operator-> ()); if (temp) { *mp_stream << indent << Keys::class_key << "(" << tl::to_word_or_quoted_string (c->name ()) << " " << tl::to_word_or_quoted_string (temp->name ()) << ")" << endl; @@ -174,14 +208,14 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl } } - if (nl->begin_device_abstracts () != nl->end_device_abstracts () && ! Keys::is_short ()) { + if (mp_netlist->begin_device_abstracts () != mp_netlist->end_device_abstracts () && ! Keys::is_short ()) { *mp_stream << endl << indent << "# Device abstracts section" << endl; *mp_stream << indent << "# Device abstracts list the pin shapes of the devices." << endl; } - for (db::Netlist::const_abstract_model_iterator m = nl->begin_device_abstracts (); m != nl->end_device_abstracts (); ++m) { + for (db::Netlist::const_abstract_model_iterator m = mp_netlist->begin_device_abstracts (); m != mp_netlist->end_device_abstracts (); ++m) { if (m->device_class ()) { *mp_stream << indent << Keys::device_key << "(" << tl::to_word_or_quoted_string (m->name ()) << " " << tl::to_word_or_quoted_string (m->device_class ()->name ()) << endl; - write (l2n, *m, indent); + write (*m, indent); *mp_stream << indent << ")" << endl; m_progress.set (mp_stream->pos ()); } @@ -191,10 +225,10 @@ void std_writer_impl::write (const db::Netlist *nl, const db::LayoutToNetl *mp_stream << endl << indent << "# Circuit section" << endl; *mp_stream << indent << "# Circuits are the hierarchical building blocks of the netlist." << endl; } - for (db::Netlist::const_bottom_up_circuit_iterator i = nl->begin_bottom_up (); i != nl->end_bottom_up (); ++i) { + for (db::Netlist::const_bottom_up_circuit_iterator i = mp_netlist->begin_bottom_up (); i != mp_netlist->end_bottom_up (); ++i) { const db::Circuit *x = i.operator-> (); *mp_stream << indent << Keys::circuit_key << "(" << tl::to_word_or_quoted_string (x->name ()) << endl; - write (nl, l2n, *x, indent, net2id_per_circuit); + write (*x, indent, net2id_per_circuit); *mp_stream << indent << ")" << endl; m_progress.set (mp_stream->pos ()); } @@ -243,7 +277,7 @@ void write_points (tl::OutputStream &stream, const T &poly, const Tr &tr, db::Po } template -void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, const db::Circuit &circuit, const std::string &indent, std::map > *net2id_per_circuit) +void std_writer_impl::write (const db::Circuit &circuit, const std::string &indent, std::map > *net2id_per_circuit) { if (circuit.boundary ().vertices () > 0) { @@ -298,14 +332,14 @@ void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutT if (circuit.begin_nets () != circuit.end_nets ()) { if (! Keys::is_short ()) { - if (l2n) { + if (mp_l2n) { *mp_stream << endl << indent << indent1 << "# Nets with their geometries" << endl; } else { *mp_stream << endl << indent << indent1 << "# Nets" << endl; } } for (db::Circuit::const_net_iterator n = circuit.begin_nets (); n != circuit.end_nets (); ++n) { - write (netlist, l2n, *n, (*net2id) [n.operator-> ()], indent); + write (*n, (*net2id) [n.operator-> ()], indent); m_progress.set (mp_stream->pos ()); } } @@ -336,7 +370,7 @@ void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutT *mp_stream << endl << indent << indent1 << "# Devices and their connections" << endl; } for (db::Circuit::const_device_iterator d = circuit.begin_devices (); d != circuit.end_devices (); ++d) { - write (l2n, *d, *net2id, indent); + write (*d, *net2id, indent); m_progress.set (mp_stream->pos ()); } } @@ -346,7 +380,7 @@ void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutT *mp_stream << endl << indent << indent1 << "# Subcircuits and their connections" << endl; } for (db::Circuit::const_subcircuit_iterator x = circuit.begin_subcircuits (); x != circuit.end_subcircuits (); ++x) { - write (l2n, *x, *net2id, indent); + write (*x, *net2id, indent); m_progress.set (mp_stream->pos ()); } } @@ -393,15 +427,21 @@ void std_writer_impl::write (const db::PolygonRef *s, const db::ICplxTrans } template -void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, const db::Net &net, unsigned int id, const std::string &indent) +bool std_writer_impl::new_cell (cell_index_type ci) const { - const db::hier_clusters &clusters = l2n->net_clusters (); + return ! (mp_netlist->circuit_by_cell_index (ci) || mp_netlist->device_abstract_by_cell_index (ci)); +} + +template +void std_writer_impl::write (const db::Net &net, unsigned int id, const std::string &indent) +{ + const db::hier_clusters &clusters = mp_l2n->net_clusters (); const db::Circuit *circuit = net.circuit (); - const db::Connectivity &conn = l2n->connectivity (); + const db::Connectivity &conn = mp_l2n->connectivity (); bool any = false; - if (l2n) { + if (mp_l2n) { reset_geometry_ref (); @@ -410,13 +450,13 @@ void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutT db::cell_index_type cci = circuit->cell_index (); db::cell_index_type prev_ci = cci; - for (db::recursive_cluster_shape_iterator si (clusters, *l, cci, net.cluster_id ()); ! si.at_end (); ) { + for (db::recursive_cluster_shape_iterator si (clusters, *l, cci, net.cluster_id (), this); ! si.at_end (); ) { // NOTE: we don't recursive into circuits which will later be output. However, as circuits may // vanish in "purge" but the clusters will still be there we need to recursive into clusters from // unknown cells. db::cell_index_type ci = si.cell_index (); - if (ci != prev_ci && ci != cci && (netlist->circuit_by_cell_index (ci) || netlist->device_abstract_by_cell_index (ci))) { + if (ci != prev_ci && ci != cci && (mp_netlist->circuit_by_cell_index (ci) || mp_netlist->device_abstract_by_cell_index (ci))) { si.skip_cell (); @@ -439,7 +479,7 @@ void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutT } *mp_stream << indent << indent2; - write (si.operator-> (), si.trans (), name_for_layer (l2n, *l), true); + write (si.operator-> (), si.trans (), name_for_layer (mp_l2n, *l), true); *mp_stream << endl; m_progress.set (mp_stream->pos ()); @@ -477,7 +517,7 @@ void std_writer_impl::write (const db::Netlist *netlist, const db::LayoutT } template -void std_writer_impl::write (const db::LayoutToNetlist *l2n, const db::SubCircuit &subcircuit, std::map &net2id, const std::string &indent) +void std_writer_impl::write (const db::SubCircuit &subcircuit, std::map &net2id, const std::string &indent) { *mp_stream << indent << indent1 << Keys::circuit_key << "(" << tl::to_string (subcircuit.id ()); *mp_stream << " " << tl::to_word_or_quoted_string (subcircuit.circuit_ref ()->name ()); @@ -486,7 +526,7 @@ void std_writer_impl::write (const db::LayoutToNetlist *l2n, const db::Sub *mp_stream << " " << Keys::name_key << "(" << tl::to_word_or_quoted_string (subcircuit.name ()) << ")"; } - if (l2n) { + if (mp_l2n) { *mp_stream << " "; write (subcircuit.trans ()); } @@ -526,12 +566,12 @@ void std_writer_impl::write (const db::LayoutToNetlist *l2n, const db::Sub } template -void std_writer_impl::write (const db::LayoutToNetlist *l2n, const db::DeviceAbstract &device_abstract, const std::string &indent) +void std_writer_impl::write (const db::DeviceAbstract &device_abstract, const std::string &indent) { const std::vector &td = device_abstract.device_class ()->terminal_definitions (); - const db::hier_clusters &clusters = l2n->net_clusters (); - const db::Connectivity &conn = l2n->connectivity (); + const db::hier_clusters &clusters = mp_l2n->net_clusters (); + const db::Connectivity &conn = mp_l2n->connectivity (); for (std::vector::const_iterator t = td.begin (); t != td.end (); ++t) { @@ -551,7 +591,7 @@ void std_writer_impl::write (const db::LayoutToNetlist *l2n, const db::Dev for (db::local_cluster::shape_iterator s = lc.begin (*l); ! s.at_end (); ++s) { *mp_stream << indent << indent2; - write (s.operator-> (), db::ICplxTrans (), name_for_layer (l2n, *l), true); + write (s.operator-> (), db::ICplxTrans (), name_for_layer (mp_l2n, *l), true); *mp_stream << endl; m_progress.set (mp_stream->pos ()); @@ -598,7 +638,7 @@ void std_writer_impl::write (const db::DCplxTrans &tr) } template -void std_writer_impl::write (const db::LayoutToNetlist * /*l2n*/, const db::Device &device, std::map &net2id, const std::string &indent) +void std_writer_impl::write (const db::Device &device, std::map &net2id, const std::string &indent) { tl_assert (device.device_class () != 0); const std::vector &td = device.device_class ()->terminal_definitions (); diff --git a/src/db/db/dbLayoutToNetlistWriter.h b/src/db/db/dbLayoutToNetlistWriter.h index 4e259bc7d..c2bf1bad1 100644 --- a/src/db/db/dbLayoutToNetlistWriter.h +++ b/src/db/db/dbLayoutToNetlistWriter.h @@ -27,6 +27,7 @@ #include "dbPoint.h" #include "dbTrans.h" #include "dbPolygon.h" +#include "dbHierNetworkProcessor.h" #include "tlStream.h" #include "tlProgress.h" @@ -46,23 +47,15 @@ namespace l2n_std_format template class std_writer_impl + : private db::CircuitCallback { public: std_writer_impl (tl::OutputStream &stream, double dbu, const std::string &progress_description = std::string ()); void write (const db::LayoutToNetlist *l2n); + void write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, bool nested, std::map > *net2id_per_circuit); protected: - void write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, bool nested, std::map > *net2id_per_circuit); - void write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, const db::Circuit &circuit, const std::string &indent, std::map > *net2id_per_circuit); - void write (const db::Netlist *netlist, const db::LayoutToNetlist *l2n, const db::Net &net, unsigned int id, const std::string &indent); - void write (const db::LayoutToNetlist *l2n, const db::SubCircuit &subcircuit, std::map &net2id, const std::string &indent); - void write (const db::LayoutToNetlist *l2n, const db::Device &device, std::map &net2id, const std::string &indent); - void write (const db::LayoutToNetlist *l2n, const db::DeviceAbstract &device_abstract, const std::string &indent); - void write (const db::PolygonRef *s, const db::ICplxTrans &tr, const std::string &lname, bool relative); - void write (const db::DCplxTrans &trans); - void reset_geometry_ref (); - tl::OutputStream &stream () { return *mp_stream; @@ -72,7 +65,22 @@ private: tl::OutputStream *mp_stream; db::Point m_ref; double m_dbu; + const db::Netlist *mp_netlist; + const db::LayoutToNetlist *mp_l2n; tl::AbsoluteProgress m_progress; + + void write (bool nested, std::map > *net2id_per_circuit); + void write (const db::Circuit &circuit, const std::string &indent, std::map > *net2id_per_circuit); + void write (const db::Net &net, unsigned int id, const std::string &indent); + void write (const db::SubCircuit &subcircuit, std::map &net2id, const std::string &indent); + void write (const db::Device &device, std::map &net2id, const std::string &indent); + void write (const db::DeviceAbstract &device_abstract, const std::string &indent); + void write (const db::PolygonRef *s, const db::ICplxTrans &tr, const std::string &lname, bool relative); + void write (const db::DCplxTrans &trans); + void reset_geometry_ref (); + + // implementation of CircuitCallback + bool new_cell (cell_index_type ci) const; }; } diff --git a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc index cc3c0fb90..b17f83219 100644 --- a/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc +++ b/src/db/unit_tests/dbLayoutToNetlistReaderTests.cc @@ -101,7 +101,7 @@ TEST(1_ReaderBasic) std::vector nets; nets.push_back (l2n.netlist ()->circuit_by_name ("RINGO")->net_by_name ("VSS")); - nets.push_back (l2n.netlist ()->circuit_by_name ("RINGO")->net_by_name ("VDD")); + nets.push_back (l2n.netlist ()->circuit_by_name ("RINGO")->net_by_name ("FB")); db::CellMapping cm = l2n.cell_mapping_into (ly2, top2, nets); diff --git a/testdata/algo/l2n_reader_au_1.gds b/testdata/algo/l2n_reader_au_1.gds index 2b85b42acbdaebea22df8912a3fc3ee4ec3ecf44..5f2f481e38037d896713fa1fe6f0eb714ef451f8 100644 GIT binary patch delta 764 zcmZo#!nnvpiGhuQi7A3XhLMT=F#`_+KLaBWTOzY3Dk+O%mxxNlA#oudyToJ{MjTou z?_$KIM~?}Yo+UVCq?mE(nZS(89u^i{da77(>3PQzi^Hc0tT<#gUt)dEgk96-a~wFO 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z_S7Tw4a6_>4Drq9llu6EK7OIEsJ>BO$~SoU1L7BaLyM<;>p7^tf%x{R!GQSY^Nsm7 zlJc$N5B2!QD)~guTgM^wr{j?N)j4Kp@w9KPzf#{o{6fzV-+Vr)k8kMX7y63o8}+4p zgNHvLe!(}ic*?idf2waFzP0@|Ainv0W4`I%ca?rKTl)Sc-zHzK?VGNO`zC+$_b+?_ z@k`c!WN7h}Z-v5t7Vu56{e9Ilw7B>e@lEv~-Btb8XH;Jizbv2PDH${t!fA#p5*S}eqoKEewuRLGdHRo6*pU7F0LG2%lt_b3mtpB~C z#Z#_1H$SYq4P=+0XUJ~z`J_I(4SjYQ`ii>Ss4unK;IXSfb{Tv_i^pA)`p)Za1KDj~ znhwZr^Z9yQ>&WHiUYwD0ofl(zi+^<@4i;x0;sBrGQ6$@KS^2Zcbbh2pezZn@M~(c> j8u?u{^1Ex~_tePmP37l#7bbCjiht9yEHAT>wl?>FxeFh3 diff --git a/testdata/algo/l2n_writer_au.txt b/testdata/algo/l2n_writer_au.txt index 3d97644d3..b56ff4d5f 100644 --- a/testdata/algo/l2n_writer_au.txt +++ b/testdata/algo/l2n_writer_au.txt @@ -217,259 +217,41 @@ circuit(RINGO # Nets with their geometries net(1 name(FB) - rect(diff_cont (22850 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-24770 1310) (360 360)) + rect(metal1 (-1700 1620) (360 360)) rect(via1 (-305 -305) (250 250)) rect(via1 (24230 -250) (250 250)) rect(metal2 (-24805 -325) (24880 400)) rect(metal2_lbl (-23161 -201) (2 2)) ) net(2 name(OSC) - rect(diff_cont (24450 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(via1 (-235 1765) (250 250)) + rect(via1 (24435 1675) (250 250)) rect(metal2 (-325 -325) (400 400)) rect(metal2_lbl (-201 -201) (2 2)) ) net(3 name(VSS) - rect(diff_cont (2530 -310) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (5060 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -290) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (4920 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal2_lbl (-23941 -381) (2 2)) + rect(metal2_lbl (-1 -1) (2 2)) ) net(4 name(VDD) - rect(diff_cont (2530 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (5060 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (2420 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -290) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (4920 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (2280 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal2_lbl (-23941 -381) (2 2)) - ) - net(5 - rect(diff_cont (20210 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(6 - rect(diff_cont (17570 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7 - rect(diff_cont (14930 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(8 - rect(diff_cont (12290 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(9 - rect(diff_cont (9650 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(10 - rect(diff_cont (7010 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(11 - rect(diff_cont (4370 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(12 - rect(diff_cont (1730 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(13 - rect(diff_cont (-910 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(14 - rect(diff_cont (690 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(15 - rect(diff_cont (21810 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(16 - rect(diff_cont (19170 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(17 - rect(diff_cont (16530 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(18 - rect(diff_cont (13890 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(19 - rect(diff_cont (11250 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(20 - rect(diff_cont (8610 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(21 - rect(diff_cont (5970 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(22 - rect(diff_cont (3330 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) + rect(metal2_lbl (-1 2799) (2 2)) ) + net(5) + net(6) + net(7) + net(8) + net(9) + net(10) + net(11) + net(12) + net(13) + net(14) + net(15) + net(16) + net(17) + net(18) + net(19) + net(20) + net(21) + net(22) # Outgoing pins and their connections to nets pin(1 name(FB)) diff --git a/testdata/algo/l2n_writer_au_2b.txt b/testdata/algo/l2n_writer_au_2b.txt index c232887a5..ac5c60d66 100644 --- a/testdata/algo/l2n_writer_au_2b.txt +++ b/testdata/algo/l2n_writer_au_2b.txt @@ -257,59 +257,13 @@ circuit(INV2PAIR # Nets with their geometries net(1 name(BULK)) - net(2 - rect(diff_cont (3430 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(3 - rect(diff_cont (790 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(4 - rect(diff_cont (4230 3290) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (2350 -290) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - ) - net(5 - rect(diff_cont (4230 490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (2350 -290) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - ) - net(6 - rect(diff_cont (2390 3690) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) + net(2) + net(3) + net(4) + net(5) + net(6) net(7) - net(8 - rect(diff_cont (5030 3690) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) + net(8) net(9) # Outgoing pins and their connections to nets @@ -349,67 +303,19 @@ circuit(RINGO # Nets with their geometries net(1 name(FB) - rect(diff_cont (22850 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(metal1 (-24770 1310) (360 360)) + rect(metal1 (-1700 1620) (360 360)) rect(via1 (-305 -305) (250 250)) rect(via1 (24230 -250) (250 250)) rect(metal2 (-24805 -325) (24880 400)) rect(metal2_lbl (-23161 -201) (2 2)) ) net(2 name(OSC) - rect(diff_cont (24450 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(via1 (-235 1765) (250 250)) + rect(via1 (24435 1675) (250 250)) rect(metal2 (-325 -325) (400 400)) rect(metal2_lbl (-201 -201) (2 2)) ) net(3 name(VDD) - rect(diff_cont (7810 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (12980 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 390) (360 1120)) + rect(metal1 (-180 3100) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) @@ -419,70 +325,10 @@ circuit(RINGO rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -1800) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (12840 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (7560 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (7560 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal2_lbl (-21301 -381) (2 2)) + rect(metal2_lbl (-23941 -1421) (2 2)) ) net(4 name(VSS) - rect(diff_cont (7810 -310) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (12980 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (7700 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-2860 -220) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -220) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(metal1 (-21410 -1330) (360 1120)) + rect(metal1 (-180 -1420) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) @@ -492,76 +338,16 @@ circuit(RINGO rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) rect(metal1 (2280 -1120) (360 1120)) - rect(metal1 (-16200 -80) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (12840 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (7560 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (7560 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal1 (-3000 -760) (360 760)) - rect(metal1 (-360 -760) (360 760)) - rect(metal2_lbl (-21301 -381) (2 2)) - ) - net(5 - rect(diff_cont (17570 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(6 - rect(diff_cont (12290 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(7 - rect(diff_cont (7010 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(8 - rect(diff_cont (1730 2490) (220 220)) - rect(diff_cont (-220 180) (220 220)) - rect(diff_cont (-220 -3420) (220 220)) - rect(diff_cont (-220 180) (220 220)) - ) - net(9 - rect(diff_cont (3330 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(10 - rect(diff_cont (19170 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(11 - rect(diff_cont (13890 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - ) - net(12 - rect(diff_cont (8610 2890) (220 220)) - rect(diff_cont (-220 -620) (220 220)) - rect(diff_cont (-220 -2620) (220 220)) - rect(diff_cont (-220 -620) (220 220)) + rect(metal2_lbl (-23941 299) (2 2)) ) + net(5) + net(6) + net(7) + net(8) + net(9) + net(10) + net(11) + net(12) # Outgoing pins and their connections to nets pin(1 name(FB)) diff --git a/testdata/algo/l2n_writer_au_2s.txt b/testdata/algo/l2n_writer_au_2s.txt index c12295b2d..e06f526ba 100644 --- a/testdata/algo/l2n_writer_au_2s.txt +++ b/testdata/algo/l2n_writer_au_2s.txt @@ -225,59 +225,13 @@ X(INV2 X(INV2PAIR R((0 -840) (5740 6220)) N(1 I(BULK)) - N(2 - R(diff_cont (3430 3290) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - ) - N(3 - R(diff_cont (790 3290) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - ) - N(4 - R(diff_cont (4230 3290) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(metal1 (2350 -290) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - ) - N(5 - R(diff_cont (4230 490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(metal1 (2350 -290) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - ) - N(6 - R(diff_cont (2390 3690) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - ) + N(2) + N(3) + N(4) + N(5) + N(6) N(7) - N(8 - R(diff_cont (5030 3690) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - ) + N(8) N(9) P(1 I(BULK)) P(2) @@ -308,67 +262,19 @@ X(INV2PAIR X(RINGO R((-1720 -1640) (26880 6220)) N(1 I(FB) - R(diff_cont (22850 2490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(metal1 (-24770 1310) (360 360)) + R(metal1 (-1700 1620) (360 360)) R(via1 (-305 -305) (250 250)) R(via1 (24230 -250) (250 250)) R(metal2 (-24805 -325) (24880 400)) R(metal2_lbl (-23161 -201) (2 2)) ) N(2 I(OSC) - R(diff_cont (24450 2890) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(via1 (-235 1765) (250 250)) + R(via1 (24435 1675) (250 250)) R(metal2 (-325 -325) (400 400)) R(metal2_lbl (-201 -201) (2 2)) ) N(3 I(VDD) - R(diff_cont (7810 2490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (12980 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (7700 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (7700 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(metal1 (-21410 390) (360 1120)) + R(metal1 (-180 3100) (360 1120)) R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) @@ -378,70 +284,10 @@ X(RINGO R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) - R(metal1 (-16200 -1800) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (12840 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (7560 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (7560 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal2_lbl (-21301 -381) (2 2)) + R(metal2_lbl (-23941 -1421) (2 2)) ) N(4 I(VSS) - R(diff_cont (7810 -310) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (12980 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (7700 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (7700 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-2860 -220) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -220) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(metal1 (-21410 -1330) (360 1120)) + R(metal1 (-180 -1420) (360 1120)) R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) @@ -451,76 +297,16 @@ X(RINGO R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) R(metal1 (2280 -1120) (360 1120)) - R(metal1 (-16200 -80) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (12840 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (7560 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (7560 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal1 (-3000 -760) (360 760)) - R(metal1 (-360 -760) (360 760)) - R(metal2_lbl (-21301 -381) (2 2)) - ) - N(5 - R(diff_cont (17570 2490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - ) - N(6 - R(diff_cont (12290 2490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - ) - N(7 - R(diff_cont (7010 2490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - ) - N(8 - R(diff_cont (1730 2490) (220 220)) - R(diff_cont (-220 180) (220 220)) - R(diff_cont (-220 -3420) (220 220)) - R(diff_cont (-220 180) (220 220)) - ) - N(9 - R(diff_cont (3330 2890) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - ) - N(10 - R(diff_cont (19170 2890) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - ) - N(11 - R(diff_cont (13890 2890) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) - ) - N(12 - R(diff_cont (8610 2890) (220 220)) - R(diff_cont (-220 -620) (220 220)) - R(diff_cont (-220 -2620) (220 220)) - R(diff_cont (-220 -620) (220 220)) + R(metal2_lbl (-23941 299) (2 2)) ) + N(5) + N(6) + N(7) + N(8) + N(9) + N(10) + N(11) + N(12) P(1 I(FB)) P(2 I(OSC)) P(3 I(VDD)) diff --git a/testdata/algo/l2n_writer_au_p.oas b/testdata/algo/l2n_writer_au_p.oas index 4db5853310aeaf2d750a1848b3692c92c808cf97..24c2e239c5febead971265d79c2f75509feedbd7 100644 GIT binary patch delta 88 zcmX>kw2EiLHO9@QOsPx~Vj{OW7@3&wY4eIgSj@a4BDdKYCiAe%GT&xnm>kMJS6WQ) ifT-XB5y2CT+#DA~1Ykh$fH2eKK#up56FB&o7#INA6clU# delta 900 zcmaivziSjh6vt;~_byA~N#14hWA84>CAl8~o9vojb{5)7gtQ_AE%OfqbVFEDh9h^R z69uo3SQxOhdB_$KEUu8i`6D)`Bt?pVAyL%0o0(w-E!^V0?|hc`nK#>)UT1gqXka2uhhO$ z`~J&4dY=W8{Ig9y(s267?qM}6yOhmT1!~^Ws3K6bPBkkF)_GyDlC-rAHX(IuOwW!> z-}AtLV^a9eU`5Hg_3WrXk1lI8B2bvuXjq`;4UGx{MavrH1Hn35#=<#iLxZ_ecWAI7 z>Dx5+9hAOT1{)CU6a7}9gpiuW8&Q?;MrVQWpb@UbvH6t7HF}%W&Ph_k$1LHyNsW%< z`XGJ4&Qgc$piCXo;)H*2D6{sjWcro<$o@zFU;Dkk_1{yb-pX)c4}a?i@pjh_`t=vv z%JH^Svsypds>|O~wtvnx3Yk7R@I?>QpV+R`j`x3)d*&vG`lkKx_9S2xumV^HECEgc zjsp$?4gmH8a=<>oAwU-}2bc#e01g9=z%K1^TD(_%fTMs#z%f?$Qm6InsWczdH1|HX{DY;-4*dnQqe2*DSaIuTV`KAmWnkfCU|{2AVqj!o<6~j~ zvK2uj2R}0dgSr5Ni~x{U)?i@JdjO$p8UFu2*Z`s#SOkHXodK^M9BgbM{sBOB+(46s zK=!doF#@&o$gnzXVSoS*VI~F^p#31bxK>p#Fc_U+U_Ak$VSKP%a5F$Un4vn@!(M<@ za5H3pX&4_>2hdgqOj}`QaPe6%FihxRU`yEnreS;xGa67`%eHF;SRMBq2o2*CV>jFk zsGW>WJ5bz!%WjyPnFTda?1b^L>BHr3SST~e{XhwI%+Q9pmZ{_gN+`qlU>zK&DM<&E jc0gc`1B5;tz`$gdfuLdHKpK{oSXdYU6rfz~`T_s|XXB4{ literal 0 HcmV?d00001 diff --git a/testdata/lvs/floating.lvsdb b/testdata/lvs/floating.lvsdb index abb305d27..8dddf3ead 100644 --- a/testdata/lvs/floating.lvsdb +++ b/testdata/lvs/floating.lvsdb @@ -170,32 +170,22 @@ layout( # Nets with their geometries net(1 name('A<1>') - rect(l8 (510 3010) (180 180)) - rect(l11 (-91 -91) (2 2)) + rect(l11 (599 3099) (2 2)) ) net(2 name('A<2>') - rect(l8 (2310 3010) (180 180)) - rect(l11 (-91 -91) (2 2)) + rect(l11 (2399 3099) (2 2)) ) net(3 name('B<2>') rect(l11 (2999 3999) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(4 name('B<1>') rect(l11 (1199 3999) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(5 name(VDD) rect(l11 (1799 7199) (2 2)) - rect(l2 (299 -2151) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) ) net(6 name(VSS) rect(l11 (1799 799) (2 2)) - rect(l6 (299 859) (425 950)) - rect(l6 (-2225 -950) (425 950)) ) # Outgoing pins and their connections to nets @@ -227,33 +217,17 @@ layout( # Nets with their geometries net(1 - rect(l8 (4110 3010) (180 180)) - rect(l11 (-1190 -240) (950 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (3100 2950) (950 300)) ) net(2 name(A) - rect(l8 (510 3010) (180 180)) - rect(l11 (-91 -91) (2 2)) + rect(l11 (599 3099) (2 2)) ) net(3 name(C) - rect(l8 (2310 3010) (180 180)) - rect(l11 (-91 -91) (2 2)) - ) - net(4 name(SUBSTRATE) - rect(l6 (3900 1660) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - ) - net(5 - rect(l2 (4575 5050) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l2 (3900 5050) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) + rect(l11 (2399 3099) (2 2)) ) + net(4 name(SUBSTRATE)) + net(5) + net(6) # Outgoing pins and their connections to nets pin(2 name(A)) diff --git a/testdata/lvs/invchain_cheat.lvsdb b/testdata/lvs/invchain_cheat.lvsdb index 5b854ca93..a661487b5 100644 --- a/testdata/lvs/invchain_cheat.lvsdb +++ b/testdata/lvs/invchain_cheat.lvsdb @@ -116,36 +116,12 @@ J( ) X(INV2 R((0 0) (5500 4600)) - N(1 - R(l6 (1790 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - ) - N(2 - R(l6 (3490 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - ) + N(1) + N(2) N(3) N(4) - N(5 - R(l6 (990 3290) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l8 (-3590 -690) (360 760)) - R(l8 (2940 -760) (360 760)) - ) - N(6 - R(l6 (990 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l8 (-3590 -690) (360 760)) - R(l8 (2940 -760) (360 760)) - ) + N(5) + N(6) P(1) P(2) P(3) @@ -177,48 +153,16 @@ J( R(l11 (4829 1889) (2 2)) ) N(4 I('4') - R(l6 (990 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l12 (-121 -1941) (2 2)) + R(l12 (1089 1969) (2 2)) ) N(5 I('6') - R(l6 (2590 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l12 (-131 -1971) (2 2)) + R(l12 (2679 1939) (2 2)) ) N(6 I('8') - R(l6 (4290 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l12 (-101 -1991) (2 2)) - ) - N(7 - R(l6 (1790 3290) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l8 (-3590 -690) (360 760)) - R(l8 (-360 -760) (360 760)) - R(l8 (2940 -760) (360 760)) - ) - N(8 - R(l6 (1790 490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l8 (-3590 -690) (360 760)) - R(l8 (-360 -760) (360 760)) - R(l8 (2940 -760) (360 760)) + R(l12 (4409 1919) (2 2)) ) + N(7) + N(8) P(1 I('3')) P(2 I('5')) P(3 I('7')) @@ -254,99 +198,39 @@ J( ) N(2 R(l3 (445 805) (480 550)) - R(l6 (-1435 -1665) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l7 (780 -2120) (220 220)) + R(l7 (-435 -365) (220 220)) R(l8 (-1065 -285) (1105 350)) ) N(3 R(l3 (1345 925) (1945 350)) - R(l6 (-2200 -1585) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l7 (95 -2120) (220 220)) + R(l7 (-1885 -285) (220 220)) R(l8 (-295 -370) (440 520)) ) N(4 R(l3 (3745 805) (480 550)) - R(l6 (-1435 -1665) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l7 (780 -2120) (220 220)) + R(l7 (-435 -365) (220 220)) R(l8 (-1065 -285) (1105 350)) ) N(5 R(l3 (4645 925) (1945 350)) - R(l6 (-2200 -1585) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l7 (95 -2120) (220 220)) + R(l7 (-1885 -285) (220 220)) R(l8 (-295 -370) (440 520)) ) N(6 R(l3 (7045 805) (480 550)) - R(l6 (-1435 -1665) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l7 (780 -2120) (220 220)) + R(l7 (-435 -365) (220 220)) R(l8 (-1065 -285) (1105 350)) ) N(7 I(OUT) - R(l6 (7690 -310) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 2180) (220 220)) - R(l6 (-220 180) (220 220)) - R(l12 (-121 -2011) (2 2)) + R(l12 (7789 1099) (2 2)) ) N(8 I(VSS) - R(l6 (6890 -310) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-3520 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-6820 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l8 (3010 -690) (360 760)) - R(l8 (-3660 -760) (360 760)) - R(l8 (2940 -760) (360 760)) - R(l8 (-6960 -760) (360 760)) - R(l8 (-360 -760) (360 760)) - R(l8 (2940 -760) (360 760)) - R(l13 (2719 -381) (2 2)) + R(l13 (6599 -1) (2 2)) R(l13 (-3302 -2) (2 2)) R(l13 (-3302 -2) (2 2)) ) N(9 I(VDD) - R(l6 (6890 2490) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-3520 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-6820 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (-220 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l6 (3080 -620) (220 220)) - R(l6 (-220 180) (220 220)) - R(l8 (3010 -690) (360 760)) - R(l8 (-3660 -760) (360 760)) - R(l8 (2940 -760) (360 760)) - R(l8 (-6960 -760) (360 760)) - R(l8 (-360 -760) (360 760)) - R(l8 (2940 -760) (360 760)) - R(l13 (-581 -381) (2 2)) + R(l13 (3299 2799) (2 2)) R(l13 (3298 -2) (2 2)) R(l13 (-6602 -2) (2 2)) ) diff --git a/testdata/lvs/ringo_layout_var.lvsdb.1 b/testdata/lvs/ringo_layout_var.lvsdb.1 index 35a52028c..167b0044a 100644 --- a/testdata/lvs/ringo_layout_var.lvsdb.1 +++ b/testdata/lvs/ringo_layout_var.lvsdb.1 @@ -449,70 +449,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -521,8 +488,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -544,20 +509,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l9 (-20175 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -565,12 +517,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -591,19 +540,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-20175 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_layout_var.lvsdb.2 b/testdata/lvs/ringo_layout_var.lvsdb.2 deleted file mode 100644 index f7ed4588d..000000000 --- a/testdata/lvs/ringo_layout_var.lvsdb.2 +++ /dev/null @@ -1,1076 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX1B - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l9 (-20175 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-20175 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1B location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1B location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1B location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX1B INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(3 3 match) - circuit(5 5 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(2 2 match) - circuit(4 4 match) - circuit(6 6 match) - circuit(1 1 match) - ) - ) -) From d0fc1edf3543b0232332677825fba992e3c38c43 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 01:45:15 +0100 Subject: [PATCH 14/21] Further updates of test data. --- testdata/lvs/ringo_device_subcircuits.lvsdb.1 | 91 +- testdata/lvs/ringo_device_subcircuits.lvsdb.2 | 971 -------------- testdata/lvs/ringo_mixed_hierarchy.lvsdb | 81 +- testdata/lvs/ringo_simple.lvsdb.1 | 91 +- testdata/lvs/ringo_simple.lvsdb.2 | 971 -------------- testdata/lvs/ringo_simple_blackboxing.lvsdb | 37 +- .../lvs/ringo_simple_device_scaling.lvsdb.1 | 91 +- .../lvs/ringo_simple_device_scaling.lvsdb.2 | 971 -------------- testdata/lvs/ringo_simple_dmos.lvsdb.1 | 37 +- testdata/lvs/ringo_simple_dmos.lvsdb.2 | 925 ------------- .../lvs/ringo_simple_dummy_device.lvsdb.1 | 91 +- .../lvs/ringo_simple_dummy_device.lvsdb.2 | 1028 --------------- .../lvs/ringo_simple_dummy_device.lvsdb.3 | 1028 --------------- .../ringo_simple_implicit_connections.lvsdb.1 | 91 +- .../ringo_simple_implicit_connections.lvsdb.2 | 990 -------------- testdata/lvs/ringo_simple_io.lvsdb.1 | 91 +- testdata/lvs/ringo_simple_io.lvsdb.2 | 891 ------------- testdata/lvs/ringo_simple_io2.l2n.1 | 91 +- testdata/lvs/ringo_simple_io2.l2n.2 | 580 -------- testdata/lvs/ringo_simple_io2.lvsdb.1 | 91 +- testdata/lvs/ringo_simple_io2.lvsdb.2 | 971 -------------- ...simple_net_and_circuit_equivalence.lvsdb.1 | 91 +- ...simple_net_and_circuit_equivalence.lvsdb.2 | 970 -------------- .../lvs/ringo_simple_pin_swapping.lvsdb.1 | 91 +- .../lvs/ringo_simple_pin_swapping.lvsdb.2 | 971 -------------- .../ringo_simple_same_device_classes.lvsdb.1 | 91 +- .../ringo_simple_same_device_classes.lvsdb.2 | 973 -------------- .../lvs/ringo_simple_simplification.lvsdb.1 | 95 +- .../lvs/ringo_simple_simplification.lvsdb.2 | 1162 ----------------- .../lvs/ringo_simple_simplification.lvsdb.3 | 1162 ----------------- ...o_simple_simplification_with_align.lvsdb.1 | 95 +- ...o_simple_simplification_with_align.lvsdb.2 | 1162 ----------------- ...o_simple_simplification_with_align.lvsdb.3 | 1162 ----------------- 33 files changed, 219 insertions(+), 18015 deletions(-) delete mode 100644 testdata/lvs/ringo_device_subcircuits.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_device_scaling.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_dmos.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_dummy_device.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_dummy_device.lvsdb.3 delete mode 100644 testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_io.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_io2.l2n.2 delete mode 100644 testdata/lvs/ringo_simple_io2.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_simplification.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_simplification.lvsdb.3 delete mode 100644 testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 delete mode 100644 testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 diff --git a/testdata/lvs/ringo_device_subcircuits.lvsdb.1 b/testdata/lvs/ringo_device_subcircuits.lvsdb.1 index 46d09231c..d9f58648a 100644 --- a/testdata/lvs/ringo_device_subcircuits.lvsdb.1 +++ b/testdata/lvs/ringo_device_subcircuits.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,20 +422,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -478,12 +430,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -504,19 +453,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_device_subcircuits.lvsdb.2 b/testdata/lvs/ringo_device_subcircuits.lvsdb.2 deleted file mode 100644 index 5f01d5105..000000000 --- a/testdata/lvs/ringo_device_subcircuits.lvsdb.2 +++ /dev/null @@ -1,971 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(XPMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 XPMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 XPMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 XPMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_mixed_hierarchy.lvsdb b/testdata/lvs/ringo_mixed_hierarchy.lvsdb index d71d08c6a..9a4c2d3ef 100644 --- a/testdata/lvs/ringo_mixed_hierarchy.lvsdb +++ b/testdata/lvs/ringo_mixed_hierarchy.lvsdb @@ -231,8 +231,7 @@ layout( rect(l4 (-250 -2000) (250 2000)) rect(l4 (-250 -5390) (250 1450)) rect(l8 (-285 1050) (180 180)) - rect(l8 (19340 -1080) (180 180)) - rect(l11 (-19760 660) (300 300)) + rect(l11 (-240 -240) (300 300)) rect(l11 (-131 -151) (2 2)) rect(l11 (18449 -1051) (900 300)) rect(l11 (-1390 590) (320 320)) @@ -243,8 +242,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (17919 -201) (400 400)) rect(l13 (-18540 -400) (400 400)) - rect(l2 (17895 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(2 name('A,ENABLE') rect(l4 (2525 2860) (250 1940)) @@ -288,18 +285,7 @@ layout( rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) rect(l2 (-23025 -2550) (450 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l9 (-20175 -450) (500 1500)) + rect(l9 (-2275 -450) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(4 @@ -311,8 +297,7 @@ layout( rect(l8 (1220 920) (180 180)) rect(l8 (-180 -1280) (180 180)) rect(l8 (-180 370) (180 180)) - rect(l8 (920 -2880) (180 180)) - polygon(l11 (-1340 -1480) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) rect(l11 (-110 1390) (300 1400)) rect(l11 (0 -1550) (610 300)) polygon(l11 (-2500 1250) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) @@ -324,66 +309,37 @@ layout( rect(l6 (-425 -4890) (425 950)) ) net(5 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(6 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(7 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(8 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(9 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(10 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(12 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(13 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(14 name(OUT) rect(l11 (23440 3840) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(15 rect(l6 (2775 1660) (450 950)) @@ -410,18 +366,7 @@ layout( rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-20175 -2210) (500 1500)) + rect(l10 (-1575 -2210) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple.lvsdb.1 b/testdata/lvs/ringo_simple.lvsdb.1 index a68dae475..b4494918c 100644 --- a/testdata/lvs/ringo_simple.lvsdb.1 +++ b/testdata/lvs/ringo_simple.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,20 +422,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -478,12 +430,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -504,19 +453,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple.lvsdb.2 b/testdata/lvs/ringo_simple.lvsdb.2 deleted file mode 100644 index 834cc43fe..000000000 --- a/testdata/lvs/ringo_simple.lvsdb.2 +++ /dev/null @@ -1,971 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_blackboxing.lvsdb b/testdata/lvs/ringo_simple_blackboxing.lvsdb index 0ab36f522..6089203e1 100644 --- a/testdata/lvs/ringo_simple_blackboxing.lvsdb +++ b/testdata/lvs/ringo_simple_blackboxing.lvsdb @@ -94,25 +94,19 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (18150 2950) (900 300)) ) net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (19950 2950) (900 300)) ) net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -152,8 +146,7 @@ layout( rect(l13 (-201 -201) (400 400)) ) net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -178,28 +171,22 @@ layout( rect(l10 (22900 -1500) (500 1500)) ) net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (7350 2950) (900 300)) ) net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (16350 2950) (900 300)) ) net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (9150 2950) (900 300)) ) net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (10950 2950) (900 300)) ) net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (12750 2950) (900 300)) ) net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) + rect(l11 (14550 2950) (900 300)) ) # Outgoing pins and their connections to nets diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 index d4ba4694d..fb98c1325 100644 --- a/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 +++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,20 +422,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -478,12 +430,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -504,19 +453,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 deleted file mode 100644 index 354c9386a..000000000 --- a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 +++ /dev/null @@ -1,971 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.5) - param(W 3) - param(AS 2.55) - param(AD 1.35) - param(PS 7.7) - param(PD 3.9) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.5) - param(W 3) - param(AS 1.35) - param(AD 2.55) - param(PS 3.9) - param(PD 7.7) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.5) - param(W 1.9) - param(AS 1.615) - param(AD 0.855) - param(PS 5.5) - param(PD 2.8) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.5) - param(W 1.9) - param(AS 0.855) - param(AD 1.615) - param(PS 2.8) - param(PD 5.5) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.5) - param(W 3) - param(AS 2.55) - param(AD 2.55) - param(PS 7.7) - param(PD 7.7) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.5) - param(W 1.9) - param(AS 1.615) - param(AD 1.615) - param(PS 5.5) - param(PD 5.5) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.5) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.5) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.5) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.5) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.5) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.5) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.1 b/testdata/lvs/ringo_simple_dmos.lvsdb.1 index 9e3146d88..47ac96fa8 100644 --- a/testdata/lvs/ringo_simple_dmos.lvsdb.1 +++ b/testdata/lvs/ringo_simple_dmos.lvsdb.1 @@ -366,49 +366,37 @@ layout( # Nets with their geometries net(1 - rect(l10 (4710 3010) (180 180)) - rect(l13 (-850 -240) (610 300)) + rect(l13 (4040 2950) (610 300)) ) net(2 - rect(l10 (6510 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (5550 2950) (900 300)) ) net(3 - rect(l10 (8310 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (7350 2950) (900 300)) ) net(4 - rect(l10 (10110 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (9150 2950) (900 300)) ) net(5 - rect(l10 (11910 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (10950 2950) (900 300)) ) net(6 - rect(l10 (13710 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (12750 2950) (900 300)) ) net(7 - rect(l10 (15510 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (14550 2950) (900 300)) ) net(8 - rect(l10 (17310 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (16350 2950) (900 300)) ) net(9 - rect(l10 (19110 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (18150 2950) (900 300)) ) net(10 - rect(l10 (20910 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) + rect(l13 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l10 (22710 3010) (180 180)) - rect(l10 (-19700 720) (180 180)) - rect(l13 (18380 -1140) (900 300)) + rect(l13 (21750 2950) (900 300)) rect(l13 (-19530 590) (320 320)) rect(l13 (17820 -320) (320 320)) rect(l14 (-18400 -260) (200 200)) @@ -448,8 +436,7 @@ layout( rect(l15 (-201 -201) (400 400)) ) net(14 name(ENABLE) - rect(l10 (2510 3010) (180 180)) - rect(l13 (-250 -250) (320 320)) + rect(l13 (2440 2940) (320 320)) rect(l14 (-260 -260) (200 200)) rect(l15 (-101 -101) (2 2)) rect(l15 (-201 -201) (400 400)) diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.2 b/testdata/lvs/ringo_simple_dmos.lvsdb.2 deleted file mode 100644 index 4256ead4a..000000000 --- a/testdata/lvs/ringo_simple_dmos.lvsdb.2 +++ /dev/null @@ -1,925 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l4 '1/0') - layer(l5 '5/0') - layer(l10 '8/0') - layer(l13 '9/0') - layer(l14 '10/0') - layer(l15 '11/0') - layer(l9) - layer(l3) - layer(l1) - layer(l11) - layer(l8) - layer(l6) - layer(l12) - - # Mask layer connectivity - connect(l4 l4 l11) - connect(l5 l5 l10) - connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12) - connect(l13 l10 l13 l14) - connect(l14 l13 l14 l15) - connect(l15 l14 l15) - connect(l9 l9) - connect(l3 l10 l3) - connect(l1 l10 l1) - connect(l11 l4 l10 l11) - connect(l8 l10 l8) - connect(l6 l10 l6) - connect(l12 l10 l12) - - # Global nets and connectivity - global(l9 SUBSTRATE) - global(l12 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l3 (125 -750) (450 1500)) - ) - terminal(G - rect(l5 (-125 -750) (250 1500)) - ) - terminal(D - rect(l1 (-550 -750) (425 1500)) - ) - terminal(B - rect(l4 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l3 (-575 -750) (450 1500)) - ) - terminal(G - rect(l5 (-125 -750) (250 1500)) - ) - terminal(D - rect(l1 (125 -750) (425 1500)) - ) - terminal(B - rect(l4 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l3 (-550 -750) (425 1500)) - ) - terminal(G - rect(l5 (-125 -750) (250 1500)) - ) - terminal(D - rect(l1 (125 -750) (425 1500)) - ) - terminal(B - rect(l4 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l8 (125 -475) (450 950)) - ) - terminal(G - rect(l5 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (-550 -475) (425 950)) - ) - terminal(B - rect(l9 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l8 (-575 -475) (450 950)) - ) - terminal(G - rect(l5 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l9 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l8 (-550 -475) (425 950)) - ) - terminal(G - rect(l5 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l9 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l10 (1110 5160) (180 180)) - rect(l10 (-180 920) (180 180)) - rect(l10 (-180 -730) (180 180)) - rect(l13 (-240 -790) (300 1700)) - rect(l13 (-1350 0) (2400 800)) - rect(l13 (-1151 -401) (2 2)) - rect(l3 (-251 -2151) (425 1500)) - rect(l3 (-450 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l10 (1810 1770) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l10 (-1580 3760) (180 180)) - rect(l10 (-180 -730) (180 180)) - rect(l10 (-180 -730) (180 180)) - rect(l10 (1220 920) (180 180)) - rect(l10 (-180 -1280) (180 180)) - rect(l10 (-180 370) (180 180)) - polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l13 (-110 1390) (300 1400)) - polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l13 (-141 -501) (2 2)) - rect(l13 (-1751 1099) (300 1400)) - rect(l13 (1100 -1700) (300 300)) - rect(l13 (-300 0) (300 1400)) - rect(l1 (-1750 -1450) (425 1500)) - rect(l1 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l10 (410 1770) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l13 (-240 -1300) (300 1360)) - rect(l13 (-650 -2160) (2400 800)) - rect(l13 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l8 (1000 1660) (425 950)) - rect(l8 (-450 -950) (425 950)) - ) - net(5 - rect(l4 (-100 4500) (2600 3500)) - ) - net(6 name(B) - rect(l5 (1425 2860) (250 1940)) - rect(l5 (-345 -950) (300 300)) - rect(l5 (-205 650) (250 2000)) - rect(l5 (-250 -2000) (250 2000)) - rect(l5 (-250 -5390) (250 1450)) - rect(l10 (-285 1050) (180 180)) - rect(l13 (-71 -91) (2 2)) - rect(l13 (-171 -151) (300 300)) - ) - net(7 name(A) - rect(l5 (725 2860) (250 1940)) - rect(l5 (-325 -1850) (300 300)) - rect(l5 (-225 1550) (250 2000)) - rect(l5 (-250 -2000) (250 2000)) - rect(l5 (-250 -5390) (250 1450)) - rect(l10 (-265 150) (180 180)) - rect(l13 (-91 -91) (2 2)) - rect(l13 (-151 -151) (300 300)) - ) - net(8 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(5) - pin(6 name(B)) - pin(7 name(A)) - pin(8 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 7) - terminal(D 2) - terminal(B 5) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 6) - terminal(D 2) - terminal(B 5) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 4) - terminal(G 7) - terminal(D 3) - terminal(B 8) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 4) - terminal(G 6) - terminal(D 2) - terminal(B 8) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l10 (410 6260) (180 180)) - rect(l10 (-180 -730) (180 180)) - rect(l10 (-180 -730) (180 180)) - rect(l13 (-240 -240) (300 1400)) - rect(l13 (-650 300) (1800 800)) - rect(l13 (-1450 -1100) (300 300)) - rect(l13 (299 399) (2 2)) - rect(l3 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l10 (1110 5160) (180 180)) - rect(l10 (-180 920) (180 180)) - rect(l10 (-180 -730) (180 180)) - rect(l10 (-180 -4120) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l13 (-240 -790) (300 4790)) - rect(l13 (-151 -2501) (2 2)) - rect(l1 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l10 (410 1770) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l13 (-240 -1300) (300 1360)) - rect(l13 (-650 -2160) (1800 800)) - rect(l13 (-851 -401) (2 2)) - rect(l8 (-651 859) (425 950)) - ) - net(4 - rect(l4 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l5 (725 2860) (250 1940)) - rect(l5 (-525 -1850) (300 300)) - rect(l5 (-25 1550) (250 2000)) - rect(l5 (-250 -2000) (250 2000)) - rect(l5 (-250 -5390) (250 1450)) - rect(l10 (-465 150) (180 180)) - rect(l13 (-91 -91) (2 2)) - rect(l13 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l10 (4710 3010) (180 180)) - rect(l13 (-850 -240) (610 300)) - ) - net(2 - rect(l10 (6510 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(3 - rect(l10 (8310 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(4 - rect(l10 (10110 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(5 - rect(l10 (11910 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(6 - rect(l10 (13710 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(7 - rect(l10 (15510 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(8 - rect(l10 (17310 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(9 - rect(l10 (19110 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(10 - rect(l10 (20910 3010) (180 180)) - rect(l13 (-1140 -240) (900 300)) - ) - net(11 name(FB) - rect(l10 (22710 3010) (180 180)) - rect(l10 (-19700 720) (180 180)) - rect(l13 (18380 -1140) (900 300)) - rect(l13 (-19530 590) (320 320)) - rect(l13 (17820 -320) (320 320)) - rect(l14 (-18400 -260) (200 200)) - rect(l14 (17940 -200) (200 200)) - rect(l15 (-18040 -300) (17740 400)) - rect(l15 (-17921 -201) (2 2)) - rect(l15 (-221 -201) (400 400)) - rect(l15 (17740 -400) (400 400)) - ) - net(12 name(VDD) - rect(l4 (500 4500) (1400 3500)) - rect(l4 (-1900 -3500) (600 3500)) - rect(l4 (23300 -3500) (1400 3500)) - rect(l4 (-100 -3500) (600 3500)) - rect(l10 (-24690 -1240) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l10 (-180 -1280) (180 180)) - rect(l10 (23220 370) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l10 (-180 -1280) (180 180)) - rect(l13 (-21741 859) (2 2)) - rect(l13 (-2351 -451) (1200 800)) - rect(l13 (-750 -1450) (300 1400)) - rect(l13 (-101 -351) (2 2)) - rect(l13 (-1251 -401) (600 800)) - rect(l13 (23400 -800) (1200 800)) - rect(l13 (-750 -1450) (300 1400)) - rect(l13 (-101 -351) (2 2)) - rect(l13 (549 -401) (600 800)) - rect(l11 (-24850 -1500) (500 1500)) - rect(l11 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l13 (23440 3840) (320 320)) - rect(l14 (-260 -260) (200 200)) - rect(l15 (-101 -101) (2 2)) - rect(l15 (-201 -201) (400 400)) - ) - net(14 name(ENABLE) - rect(l10 (2510 3010) (180 180)) - rect(l13 (-250 -250) (320 320)) - rect(l14 (-260 -260) (200 200)) - rect(l15 (-101 -101) (2 2)) - rect(l15 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l10 (1110 1610) (180 180)) - rect(l10 (-180 -1280) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l10 (23220 370) (180 180)) - rect(l10 (-180 -1280) (180 180)) - rect(l10 (-180 370) (180 180)) - rect(l13 (-21741 -391) (2 2)) - rect(l13 (-1901 -401) (300 1400)) - rect(l13 (-750 -1450) (1200 800)) - rect(l13 (-551 -401) (2 2)) - rect(l13 (-1251 -401) (600 800)) - rect(l13 (23850 -750) (300 1400)) - rect(l13 (-750 -1450) (1200 800)) - rect(l13 (-551 -401) (2 2)) - rect(l13 (549 -401) (600 800)) - rect(l12 (-24850 -800) (500 1500)) - rect(l12 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 nomatch - xref( - net(4 8 mismatch) - net(5 4 mismatch) - net(7 6 match) - net(6 5 match) - net(2 2 mismatch) - net(8 7 mismatch) - net(1 1 mismatch) - net(3 3 mismatch) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(4 4 match) - device(3 3 mismatch) - device(2 2 match) - device(1 1 mismatch) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 index ee46022fe..f5c5cb5a0 100644 --- a/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 @@ -369,70 +369,37 @@ layout( rect(l11 (-240 -240) (300 300)) ) net(2 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(3 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(4 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(5 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(6 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(7 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(8 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(9 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(10 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(11 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(12 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -441,8 +408,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(13 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -470,20 +435,7 @@ layout( rect(l11 (0 -800) (600 800)) rect(l11 (0 -800) (600 800)) rect(l11 (0 -800) (600 800)) - rect(l2 (-24825 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-26650 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(14 name(OUT) @@ -491,12 +443,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(15 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -526,19 +475,7 @@ layout( rect(l11 (0 -800) (600 800)) rect(l11 (0 -800) (600 800)) rect(l11 (0 -800) (600 800)) - rect(l6 (-25500 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (2975 -1010) (425 950)) + rect(l6 (-1700 400) (425 950)) rect(l6 (250 -950) (425 950)) rect(l10 (-26050 -2150) (500 1500)) rect(l10 (22900 -1500) (500 1500)) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 deleted file mode 100644 index 3c0b06564..000000000 --- a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 +++ /dev/null @@ -1,1028 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS$1 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$2 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (27600 7650)) - - # Nets with their geometries - net(1 - rect(l4 (26050 2800) (525 550)) - rect(l4 (-525 -300) (300 300)) - rect(l4 (-25 -2000) (250 1450)) - rect(l8 (-465 310) (180 180)) - rect(l11 (-240 -240) (300 300)) - ) - net(2 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(13 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l8 (-26490 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l2 (-24825 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(14 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(15 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(16 name(VSS) - rect(l8 (26010 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (520 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-25780 -890) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (1260 -40) (300 1360)) - rect(l11 (400 -1360) (300 1360)) - rect(l11 (-24001 -1711) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l6 (-25500 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3650 -1010) (425 950)) - rect(l6 (-1100 -950) (425 950)) - rect(l10 (-25375 -2150) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(12 name(FB)) - pin(13 name(VDD)) - pin(14 name(OUT)) - pin(15 name(ENABLE)) - pin(16 name(VSS)) - - # Devices and their connections - device(1 D$NMOS - location(26450 2075) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 16) - terminal(G 1) - terminal(D 16) - terminal(B 16) - ) - - # Subcircuits and their connections - circuit(3 ND2X1 location(1800 0) - pin(0 13) - pin(1 2) - pin(2 16) - pin(3 13) - pin(4 12) - pin(5 15) - pin(6 16) - ) - circuit(4 INVX1 location(4200 0) - pin(0 13) - pin(1 3) - pin(2 16) - pin(3 13) - pin(4 2) - pin(5 16) - ) - circuit(5 INVX1 location(6000 0) - pin(0 13) - pin(1 4) - pin(2 16) - pin(3 13) - pin(4 3) - pin(5 16) - ) - circuit(6 INVX1 location(7800 0) - pin(0 13) - pin(1 5) - pin(2 16) - pin(3 13) - pin(4 4) - pin(5 16) - ) - circuit(7 INVX1 location(9600 0) - pin(0 13) - pin(1 6) - pin(2 16) - pin(3 13) - pin(4 5) - pin(5 16) - ) - circuit(8 INVX1 location(11400 0) - pin(0 13) - pin(1 7) - pin(2 16) - pin(3 13) - pin(4 6) - pin(5 16) - ) - circuit(9 INVX1 location(13200 0) - pin(0 13) - pin(1 8) - pin(2 16) - pin(3 13) - pin(4 7) - pin(5 16) - ) - circuit(10 INVX1 location(15000 0) - pin(0 13) - pin(1 9) - pin(2 16) - pin(3 13) - pin(4 8) - pin(5 16) - ) - circuit(11 INVX1 location(16800 0) - pin(0 13) - pin(1 10) - pin(2 16) - pin(3 13) - pin(4 9) - pin(5 16) - ) - circuit(12 INVX1 location(18600 0) - pin(0 13) - pin(1 11) - pin(2 16) - pin(3 13) - pin(4 10) - pin(5 16) - ) - circuit(13 INVX1 location(20400 0) - pin(0 13) - pin(1 12) - pin(2 16) - pin(3 13) - pin(4 11) - pin(5 16) - ) - circuit(14 INVX1 location(22200 0) - pin(0 13) - pin(1 14) - pin(2 16) - pin(3 13) - pin(4 12) - pin(5 16) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(NMOS MOS4) - class(PMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - net(16 name(DUMMY)) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Devices and their connections - device(1 NMOS - name($1) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 16) - terminal(D 1) - terminal(B 1) - ) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(2 6 match) - net(11 15 match) - net(3 7 match) - net(4 8 match) - net(5 9 match) - net(6 10 match) - net(7 11 match) - net(8 12 match) - net(9 13 match) - net(10 14 match) - net(1 16 match) - net(15 4 match) - net(12 3 match) - net(14 5 match) - net(13 2 match) - net(16 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - device(1 1 match) - circuit(4 2 match) - circuit(5 3 match) - circuit(6 4 match) - circuit(7 5 match) - circuit(8 6 match) - circuit(9 7 match) - circuit(10 8 match) - circuit(11 9 match) - circuit(12 10 match) - circuit(13 11 match) - circuit(14 12 match) - circuit(3 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 deleted file mode 100644 index f4780ff2d..000000000 --- a/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 +++ /dev/null @@ -1,1028 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS$1 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$2 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (27600 7650)) - - # Nets with their geometries - net(1 - rect(l4 (26050 2800) (525 550)) - rect(l4 (-525 -300) (300 300)) - rect(l4 (-25 -2000) (250 1450)) - rect(l8 (-465 310) (180 180)) - rect(l11 (-240 -240) (300 300)) - ) - net(2 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(13 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l8 (-26490 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l2 (-24825 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(14 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(15 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(16 name(VSS) - rect(l8 (26010 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (520 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-25780 -890) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (1260 -40) (300 1360)) - rect(l11 (400 -1360) (300 1360)) - rect(l11 (-24001 -1711) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l6 (-25500 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3650 -1010) (425 950)) - rect(l6 (-1100 -950) (425 950)) - rect(l10 (-25375 -2150) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(12 name(FB)) - pin(13 name(VDD)) - pin(14 name(OUT)) - pin(15 name(ENABLE)) - pin(16 name(VSS)) - - # Devices and their connections - device(1 D$NMOS - location(26450 2075) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 16) - terminal(G 1) - terminal(D 16) - terminal(B 16) - ) - - # Subcircuits and their connections - circuit(3 ND2X1 location(1800 0) - pin(0 13) - pin(1 2) - pin(2 16) - pin(3 13) - pin(4 12) - pin(5 15) - pin(6 16) - ) - circuit(4 INVX1 location(4200 0) - pin(0 13) - pin(1 3) - pin(2 16) - pin(3 13) - pin(4 2) - pin(5 16) - ) - circuit(5 INVX1 location(6000 0) - pin(0 13) - pin(1 4) - pin(2 16) - pin(3 13) - pin(4 3) - pin(5 16) - ) - circuit(6 INVX1 location(7800 0) - pin(0 13) - pin(1 5) - pin(2 16) - pin(3 13) - pin(4 4) - pin(5 16) - ) - circuit(7 INVX1 location(9600 0) - pin(0 13) - pin(1 6) - pin(2 16) - pin(3 13) - pin(4 5) - pin(5 16) - ) - circuit(8 INVX1 location(11400 0) - pin(0 13) - pin(1 7) - pin(2 16) - pin(3 13) - pin(4 6) - pin(5 16) - ) - circuit(9 INVX1 location(13200 0) - pin(0 13) - pin(1 8) - pin(2 16) - pin(3 13) - pin(4 7) - pin(5 16) - ) - circuit(10 INVX1 location(15000 0) - pin(0 13) - pin(1 9) - pin(2 16) - pin(3 13) - pin(4 8) - pin(5 16) - ) - circuit(11 INVX1 location(16800 0) - pin(0 13) - pin(1 10) - pin(2 16) - pin(3 13) - pin(4 9) - pin(5 16) - ) - circuit(12 INVX1 location(18600 0) - pin(0 13) - pin(1 11) - pin(2 16) - pin(3 13) - pin(4 10) - pin(5 16) - ) - circuit(13 INVX1 location(20400 0) - pin(0 13) - pin(1 12) - pin(2 16) - pin(3 13) - pin(4 11) - pin(5 16) - ) - circuit(14 INVX1 location(22200 0) - pin(0 13) - pin(1 14) - pin(2 16) - pin(3 13) - pin(4 12) - pin(5 16) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(NMOS MOS4) - class(PMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - net(16 name(DUMMY)) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Devices and their connections - device(1 NMOS - name($1) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 16) - terminal(D 1) - terminal(B 1) - ) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(2 6 match) - net(11 15 match) - net(3 7 match) - net(4 8 match) - net(5 9 match) - net(6 10 match) - net(7 11 match) - net(8 12 match) - net(9 13 match) - net(10 14 match) - net(1 16 match) - net(15 4 match) - net(12 3 match) - net(14 5 match) - net(13 2 match) - net(16 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - device(1 1 match) - circuit(4 2 match) - circuit(5 3 match) - circuit(6 4 match) - circuit(7 5 match) - circuit(8 6 match) - circuit(9 7 match) - circuit(10 8 match) - circuit(11 9 match) - circuit(12 10 match) - circuit(13 11 match) - circuit(14 12 match) - circuit(3 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 index 2760c734e..ff9b41108 100644 --- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 +++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (5210 3010) (180 180)) - rect(l11 (-1350 -240) (1160 300)) - rect(l2 (-3100 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (1160 300)) ) net(2 - rect(l8 (7010 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (6050 2950) (900 300)) ) net(3 - rect(l8 (8810 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7850 2950) (900 300)) ) net(4 - rect(l8 (10610 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9650 2950) (900 300)) ) net(5 - rect(l8 (12410 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (11450 2950) (900 300)) ) net(6 - rect(l8 (14210 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (13250 2950) (900 300)) ) net(7 - rect(l8 (16010 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (15050 2950) (900 300)) ) net(8 - rect(l8 (17810 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16850 2950) (900 300)) ) net(9 - rect(l8 (19610 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18650 2950) (900 300)) ) net(10 - rect(l8 (21410 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (20450 2950) (900 300)) ) net(11 name(FB) - rect(l8 (25210 3010) (180 180)) - rect(l8 (-22200 720) (180 180)) - rect(l11 (18880 -1140) (2900 300)) + rect(l11 (22250 2950) (2900 300)) rect(l11 (-21980 590) (320 320)) rect(l11 (18570 -320) (320 320)) rect(l12 (-19150 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-19071 -201) (2 2)) rect(l13 (-171 -201) (400 400)) rect(l13 (18490 -400) (400 400)) - rect(l2 (-545 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (22600 4500) (1400 3500)) @@ -466,20 +431,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23300 -2550) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (-18850 -1500) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (21775 -1500) (425 1500)) - rect(l9 (-2375 -450) (500 1500)) + rect(l9 (-5250 -1500) (500 1500)) rect(l9 (-22600 -1500) (500 1500)) rect(l9 (25400 -1500) (500 1500)) ) @@ -488,12 +440,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-151 -101) (2 2)) rect(l13 (-151 -201) (400 400)) - rect(l2 (-675 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-200 -250) (320 320)) + rect(l11 (2490 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-151 -101) (2 2)) rect(l13 (-151 -201) (400 400)) @@ -522,19 +471,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (-1251 -401) (600 800)) - rect(l6 (24400 460) (425 950)) - rect(l6 (-20425 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (-19525 -950) (425 950)) - rect(l10 (24325 -2210) (500 1500)) + rect(l10 (26250 -800) (500 1500)) rect(l10 (-4300 -1500) (500 1500)) rect(l10 (-22600 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 deleted file mode 100644 index 4a0b7e13e..000000000 --- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 +++ /dev/null @@ -1,990 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (28300 7650)) - - # Nets with their geometries - net(1 - rect(l8 (5210 3010) (180 180)) - rect(l11 (-1350 -240) (1160 300)) - rect(l2 (-1725 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (7010 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8810 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10610 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (12410 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (14210 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (16010 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17810 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19610 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (21410 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (25210 3010) (180 180)) - rect(l8 (-22200 720) (180 180)) - rect(l11 (18880 -1140) (2900 300)) - rect(l11 (-21980 590) (320 320)) - rect(l11 (18570 -320) (320 320)) - rect(l12 (-19150 -260) (200 200)) - rect(l12 (18690 -200) (200 200)) - rect(l13 (-18840 -300) (18890 400)) - rect(l13 (-19071 -201) (2 2)) - rect(l13 (-171 -201) (400 400)) - rect(l13 (18490 -400) (400 400)) - rect(l2 (-545 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (22600 4500) (1400 3500)) - rect(l3 (-23500 -3500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (25800 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-5090 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-22280 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (25720 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-4891 1009) (2 2)) - rect(l11 (2798 -52) (2 2)) - rect(l11 (-22152 -102) (2 2)) - rect(l11 (19749 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-22751 -401) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (25900 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23300 -2550) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (-18850 -1500) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (21775 -1500) (425 1500)) - rect(l9 (-2375 -450) (500 1500)) - rect(l9 (-22600 -1500) (500 1500)) - rect(l9 (25400 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (25990 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-151 -101) (2 2)) - rect(l13 (-151 -201) (400 400)) - rect(l2 (-675 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-200 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-151 -101) (2 2)) - rect(l13 (-151 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (27010 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-3980 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-22280 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (24709 -291) (2 2)) - rect(l11 (-3852 -2) (2 2)) - rect(l11 (-19202 -102) (2 2)) - rect(l11 (23999 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l11 (-5150 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-22301 -351) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l6 (24400 460) (425 950)) - rect(l6 (-20425 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (-19525 -950) (425 950)) - rect(l10 (24325 -2210) (500 1500)) - rect(l10 (-4300 -1500) (500 1500)) - rect(l10 (-22600 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4700 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6500 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(8300 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(10100 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11900 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13700 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15500 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(17300 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(19100 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20900 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(24700 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.1 b/testdata/lvs/ringo_simple_io.lvsdb.1 index edb8e90ce..ab4626e4d 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io.lvsdb.1 @@ -319,70 +319,37 @@ J( X(RINGO R((0 350) (25800 7650)) N(1 - R(l8 (4710 3010) (180 180)) - R(l11 (-850 -240) (610 300)) - R(l2 (-2550 1800) (425 1500)) - R(l2 (950 -1500) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (4040 2950) (610 300)) ) N(2 - R(l8 (6510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (5550 2950) (900 300)) ) N(3 - R(l8 (8310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (7350 2950) (900 300)) ) N(4 - R(l8 (10110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (9150 2950) (900 300)) ) N(5 - R(l8 (11910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (10950 2950) (900 300)) ) N(6 - R(l8 (13710 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (12750 2950) (900 300)) ) N(7 - R(l8 (15510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (14550 2950) (900 300)) ) N(8 - R(l8 (17310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (16350 2950) (900 300)) ) N(9 - R(l8 (19110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (18150 2950) (900 300)) ) N(10 - R(l8 (20910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (19950 2950) (900 300)) ) N(11 I(FB) - R(l8 (22710 3010) (180 180)) - R(l8 (-19700 720) (180 180)) - R(l11 (18380 -1140) (900 300)) + R(l11 (21750 2950) (900 300)) R(l11 (-19530 590) (320 320)) R(l11 (17820 -320) (320 320)) R(l12 (-18400 -260) (200 200)) @@ -391,8 +358,6 @@ J( R(l13 (-17921 -201) (2 2)) R(l13 (-221 -201) (400 400)) R(l13 (17740 -400) (400 400)) - R(l2 (-245 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) ) N(12 I(VDD) R(l3 (500 4500) (1400 3500)) @@ -414,20 +379,7 @@ J( R(l11 (-750 -1450) (300 1400)) R(l11 (-101 -351) (2 2)) R(l11 (549 -401) (600 800)) - R(l2 (-23025 -2550) (425 1500)) - R(l2 (-400 -1500) (425 1500)) - R(l2 (1275 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l9 (-21975 -450) (500 1500)) + R(l9 (-24850 -1500) (500 1500)) R(l9 (22900 -1500) (500 1500)) ) N(13 I(OUT) @@ -435,12 +387,9 @@ J( R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) - R(l2 (-625 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) ) N(14 I(ENABLE) - R(l8 (2510 3010) (180 180)) - R(l11 (-250 -250) (320 320)) + R(l11 (2440 2940) (320 320)) R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) @@ -461,19 +410,7 @@ J( R(l11 (-750 -1450) (1200 800)) R(l11 (-551 -401) (2 2)) R(l11 (549 -401) (600 800)) - R(l6 (-23700 460) (425 950)) - R(l6 (1975 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l10 (-21975 -2210) (500 1500)) + R(l10 (-24850 -800) (500 1500)) R(l10 (22900 -1500) (500 1500)) ) P(11 I(FB)) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.2 b/testdata/lvs/ringo_simple_io.lvsdb.2 deleted file mode 100644 index 1db7e627a..000000000 --- a/testdata/lvs/ringo_simple_io.lvsdb.2 +++ /dev/null @@ -1,891 +0,0 @@ -#%lvsdb-klayout -J( - W(RINGO) - U(0.001) - L(l3 '1/0') - L(l4 '5/0') - L(l8 '8/0') - L(l11 '9/0') - L(l12 '10/0') - L(l13 '11/0') - L(l7) - L(l2) - L(l9) - L(l6) - L(l10) - C(l3 l3 l9) - C(l4 l4 l8) - C(l8 l4 l8 l11 l2 l9 l6 l10) - C(l11 l8 l11 l12) - C(l12 l11 l12 l13) - C(l13 l12 l13) - C(l7 l7) - C(l2 l8 l2) - C(l9 l3 l8 l9) - C(l6 l8 l6) - C(l10 l8 l10) - G(l7 SUBSTRATE) - G(l10 SUBSTRATE) - D(D$PMOS PMOS - T(S - R(l2 (-550 -750) (425 1500)) - ) - T(G - R(l4 (-125 -750) (250 1500)) - ) - T(D - R(l2 (125 -750) (450 1500)) - ) - T(B - R(l3 (-125 -750) (250 1500)) - ) - ) - D(D$PMOS$1 PMOS - T(S - R(l2 (-575 -750) (450 1500)) - ) - T(G - R(l4 (-125 -750) (250 1500)) - ) - T(D - R(l2 (125 -750) (425 1500)) - ) - T(B - R(l3 (-125 -750) (250 1500)) - ) - ) - D(D$PMOS$2 PMOS - T(S - R(l2 (-550 -750) (425 1500)) - ) - T(G - R(l4 (-125 -750) (250 1500)) - ) - T(D - R(l2 (125 -750) (425 1500)) - ) - T(B - R(l3 (-125 -750) (250 1500)) - ) - ) - D(D$NMOS NMOS - T(S - R(l6 (-550 -475) (425 950)) - ) - T(G - R(l4 (-125 -475) (250 950)) - ) - T(D - R(l6 (125 -475) (450 950)) - ) - T(B - R(l7 (-125 -475) (250 950)) - ) - ) - D(D$NMOS$1 NMOS - T(S - R(l6 (-575 -475) (450 950)) - ) - T(G - R(l4 (-125 -475) (250 950)) - ) - T(D - R(l6 (125 -475) (425 950)) - ) - T(B - R(l7 (-125 -475) (250 950)) - ) - ) - D(D$NMOS$2 NMOS - T(S - R(l6 (-550 -475) (425 950)) - ) - T(G - R(l4 (-125 -475) (250 950)) - ) - T(D - R(l6 (125 -475) (425 950)) - ) - T(B - R(l7 (-125 -475) (250 950)) - ) - ) - X(ND2X1 - R((-100 400) (2600 7600)) - N(1 I(VDD) - R(l8 (1110 5160) (180 180)) - R(l8 (-180 920) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l11 (-240 -790) (300 1700)) - R(l11 (-1350 0) (2400 800)) - R(l11 (-1151 -401) (2 2)) - R(l2 (-276 -2151) (425 1500)) - R(l2 (-400 -1500) (425 1500)) - ) - N(2 I(OUT) - R(l8 (1810 1770) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (-1580 3760) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (1220 920) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (-180 370) (180 180)) - Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - R(l11 (-110 1390) (300 1400)) - Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - R(l11 (-141 -501) (2 2)) - R(l11 (-1751 1099) (300 1400)) - R(l11 (1100 -1700) (300 300)) - R(l11 (-300 0) (300 1400)) - R(l2 (-375 -1450) (425 1500)) - R(l2 (-1800 -1500) (425 1500)) - R(l6 (950 -4890) (425 950)) - ) - N(3 I(VSS) - R(l8 (410 1770) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-240 -1300) (300 1360)) - R(l11 (-650 -2160) (2400 800)) - R(l11 (-1151 -401) (2 2)) - R(l6 (-951 859) (425 950)) - ) - N(4 - R(l3 (-100 4500) (2600 3500)) - ) - N(5 I(B) - R(l4 (1425 2860) (250 1940)) - R(l4 (-345 -950) (300 300)) - R(l4 (-205 650) (250 2000)) - R(l4 (-250 -2000) (250 2000)) - R(l4 (-250 -5390) (250 1450)) - R(l8 (-285 1050) (180 180)) - R(l11 (-71 -91) (2 2)) - R(l11 (-171 -151) (300 300)) - ) - N(6 I(A) - R(l4 (725 2860) (250 1940)) - R(l4 (-325 -1850) (300 300)) - R(l4 (-225 1550) (250 2000)) - R(l4 (-250 -2000) (250 2000)) - R(l4 (-250 -5390) (250 1450)) - R(l8 (-265 150) (180 180)) - R(l11 (-91 -91) (2 2)) - R(l11 (-151 -151) (300 300)) - ) - N(7 I(SUBSTRATE)) - N(8 - R(l6 (975 1660) (425 950)) - R(l6 (-400 -950) (425 950)) - ) - P(1 I(VDD)) - P(2 I(OUT)) - P(3 I(VSS)) - P(4) - P(5 I(B)) - P(6 I(A)) - P(7 I(SUBSTRATE)) - D(1 D$PMOS - Y(850 5800) - E(L 0.25) - E(W 1.5) - E(AS 0.6375) - E(AD 0.3375) - E(PS 3.85) - E(PD 1.95) - T(S 2) - T(G 6) - T(D 1) - T(B 4) - ) - D(2 D$PMOS$1 - Y(1550 5800) - E(L 0.25) - E(W 1.5) - E(AS 0.3375) - E(AD 0.6375) - E(PS 1.95) - E(PD 3.85) - T(S 1) - T(G 5) - T(D 2) - T(B 4) - ) - D(3 D$NMOS - Y(850 2135) - E(L 0.25) - E(W 0.95) - E(AS 0.40375) - E(AD 0.21375) - E(PS 2.75) - E(PD 1.4) - T(S 3) - T(G 6) - T(D 8) - T(B 7) - ) - D(4 D$NMOS$1 - Y(1550 2135) - E(L 0.25) - E(W 0.95) - E(AS 0.21375) - E(AD 0.40375) - E(PS 1.4) - E(PD 2.75) - T(S 8) - T(G 5) - T(D 2) - T(B 7) - ) - ) - X(INVX1 - R((-100 400) (2000 7600)) - N(1 I(VDD) - R(l8 (410 6260) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l11 (-240 -240) (300 1400)) - R(l11 (-650 300) (1800 800)) - R(l11 (-1450 -1100) (300 300)) - R(l11 (299 399) (2 2)) - R(l2 (-651 -2151) (425 1500)) - ) - N(2 I(OUT) - R(l8 (1110 5160) (180 180)) - R(l8 (-180 920) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (-180 -4120) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-240 -790) (300 4790)) - R(l11 (-151 -2501) (2 2)) - R(l2 (-226 1049) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(3 I(VSS) - R(l8 (410 1770) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-240 -1300) (300 1360)) - R(l11 (-650 -2160) (1800 800)) - R(l11 (-851 -401) (2 2)) - R(l6 (-651 859) (425 950)) - ) - N(4 - R(l3 (-100 4500) (2000 3500)) - ) - N(5 I(IN) - R(l4 (725 2860) (250 1940)) - R(l4 (-525 -1850) (300 300)) - R(l4 (-25 1550) (250 2000)) - R(l4 (-250 -2000) (250 2000)) - R(l4 (-250 -5390) (250 1450)) - R(l8 (-465 150) (180 180)) - R(l11 (-91 -91) (2 2)) - R(l11 (-151 -151) (300 300)) - ) - N(6 I(SUBSTRATE)) - P(1 I(VDD)) - P(2 I(OUT)) - P(3 I(VSS)) - P(4) - P(5 I(IN)) - P(6 I(SUBSTRATE)) - D(1 D$PMOS$2 - Y(850 5800) - E(L 0.25) - E(W 1.5) - E(AS 0.6375) - E(AD 0.6375) - E(PS 3.85) - E(PD 3.85) - T(S 1) - T(G 5) - T(D 2) - T(B 4) - ) - D(2 D$NMOS$2 - Y(850 2135) - E(L 0.25) - E(W 0.95) - E(AS 0.40375) - E(AD 0.40375) - E(PS 2.75) - E(PD 2.75) - T(S 3) - T(G 5) - T(D 2) - T(B 6) - ) - ) - X(RINGO - R((0 350) (25800 7650)) - N(1 - R(l8 (4710 3010) (180 180)) - R(l11 (-850 -240) (610 300)) - R(l2 (-1175 1800) (425 1500)) - R(l2 (-1800 -1500) (425 1500)) - R(l6 (950 -4890) (425 950)) - ) - N(2 - R(l8 (6510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(3 - R(l8 (8310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(4 - R(l8 (10110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(5 - R(l8 (11910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(6 - R(l8 (13710 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(7 - R(l8 (15510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(8 - R(l8 (17310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(9 - R(l8 (19110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(10 - R(l8 (20910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(11 I(FB) - R(l8 (22710 3010) (180 180)) - R(l8 (-19700 720) (180 180)) - R(l11 (18380 -1140) (900 300)) - R(l11 (-19530 590) (320 320)) - R(l11 (17820 -320) (320 320)) - R(l12 (-18400 -260) (200 200)) - R(l12 (17940 -200) (200 200)) - R(l13 (-18040 -300) (17740 400)) - R(l13 (-17921 -201) (2 2)) - R(l13 (-221 -201) (400 400)) - R(l13 (17740 -400) (400 400)) - R(l2 (-245 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(12 I(VDD) - R(l3 (500 4500) (1400 3500)) - R(l3 (-1900 -3500) (600 3500)) - R(l3 (23300 -3500) (1400 3500)) - R(l3 (-100 -3500) (600 3500)) - R(l8 (-24690 -1240) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (23220 370) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l11 (-21741 859) (2 2)) - R(l11 (-2351 -451) (1200 800)) - R(l11 (-750 -1450) (300 1400)) - R(l11 (-101 -351) (2 2)) - R(l11 (-1251 -401) (600 800)) - R(l11 (23400 -800) (1200 800)) - R(l11 (-750 -1450) (300 1400)) - R(l11 (-101 -351) (2 2)) - R(l11 (549 -401) (600 800)) - R(l2 (-23025 -2550) (425 1500)) - R(l2 (-400 -1500) (425 1500)) - R(l2 (1275 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l9 (-21975 -450) (500 1500)) - R(l9 (22900 -1500) (500 1500)) - ) - N(13 I(OUT) - R(l11 (23440 3840) (320 320)) - R(l12 (-260 -260) (200 200)) - R(l13 (-101 -101) (2 2)) - R(l13 (-201 -201) (400 400)) - R(l2 (-625 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(14 I(ENABLE) - R(l8 (2510 3010) (180 180)) - R(l11 (-250 -250) (320 320)) - R(l12 (-260 -260) (200 200)) - R(l13 (-101 -101) (2 2)) - R(l13 (-201 -201) (400 400)) - ) - N(15 I(VSS) - R(l8 (1110 1610) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (23220 370) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-21741 -391) (2 2)) - R(l11 (-1901 -401) (300 1400)) - R(l11 (-750 -1450) (1200 800)) - R(l11 (-551 -401) (2 2)) - R(l11 (-1251 -401) (600 800)) - R(l11 (23850 -750) (300 1400)) - R(l11 (-750 -1450) (1200 800)) - R(l11 (-551 -401) (2 2)) - R(l11 (549 -401) (600 800)) - R(l6 (-23700 460) (425 950)) - R(l6 (1975 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l10 (-21975 -2210) (500 1500)) - R(l10 (22900 -1500) (500 1500)) - ) - P(11 I(FB)) - P(12 I(VDD)) - P(13 I(OUT)) - P(14 I(ENABLE)) - P(15 I(VSS)) - X(1 ND2X1 Y(1800 0) - P(0 12) - P(1 1) - P(2 15) - P(3 12) - P(4 11) - P(5 14) - P(6 15) - ) - X(2 INVX1 Y(4200 0) - P(0 12) - P(1 2) - P(2 15) - P(3 12) - P(4 1) - P(5 15) - ) - X(3 INVX1 Y(6000 0) - P(0 12) - P(1 3) - P(2 15) - P(3 12) - P(4 2) - P(5 15) - ) - X(4 INVX1 Y(7800 0) - P(0 12) - P(1 4) - P(2 15) - P(3 12) - P(4 3) - P(5 15) - ) - X(5 INVX1 Y(9600 0) - P(0 12) - P(1 5) - P(2 15) - P(3 12) - P(4 4) - P(5 15) - ) - X(6 INVX1 Y(11400 0) - P(0 12) - P(1 6) - P(2 15) - P(3 12) - P(4 5) - P(5 15) - ) - X(7 INVX1 Y(13200 0) - P(0 12) - P(1 7) - P(2 15) - P(3 12) - P(4 6) - P(5 15) - ) - X(8 INVX1 Y(15000 0) - P(0 12) - P(1 8) - P(2 15) - P(3 12) - P(4 7) - P(5 15) - ) - X(9 INVX1 Y(16800 0) - P(0 12) - P(1 9) - P(2 15) - P(3 12) - P(4 8) - P(5 15) - ) - X(10 INVX1 Y(18600 0) - P(0 12) - P(1 10) - P(2 15) - P(3 12) - P(4 9) - P(5 15) - ) - X(11 INVX1 Y(20400 0) - P(0 12) - P(1 11) - P(2 15) - P(3 12) - P(4 10) - P(5 15) - ) - X(12 INVX1 Y(22200 0) - P(0 12) - P(1 13) - P(2 15) - P(3 12) - P(4 11) - P(5 15) - ) - ) -) -H( - X(ND2X1 - N(1 I(VDD)) - N(2 I(OUT)) - N(3 I(VSS)) - N(4 I(NWELL)) - N(5 I(B)) - N(6 I(A)) - N(7 I(BULK)) - N(8 I('1')) - P(1 I(VDD)) - P(2 I(OUT)) - P(3 I(VSS)) - P(4 I(NWELL)) - P(5 I(B)) - P(6 I(A)) - P(7 I(BULK)) - D(1 PMOS - I($1) - E(L 0.25) - E(W 1.5) - E(AS 0) - E(AD 0) - E(PS 0) - E(PD 0) - T(S 2) - T(G 6) - T(D 1) - T(B 4) - ) - D(2 PMOS - I($2) - E(L 0.25) - E(W 1.5) - E(AS 0) - E(AD 0) - E(PS 0) - E(PD 0) - T(S 1) - T(G 5) - T(D 2) - T(B 4) - ) - D(3 NMOS - I($3) - E(L 0.25) - E(W 0.95) - E(AS 0) - E(AD 0) - E(PS 0) - E(PD 0) - T(S 3) - T(G 6) - T(D 8) - T(B 7) - ) - D(4 NMOS - I($4) - E(L 0.25) - E(W 0.95) - E(AS 0) - E(AD 0) - E(PS 0) - E(PD 0) - T(S 8) - T(G 5) - T(D 2) - T(B 7) - ) - ) - X(INVX1 - N(1 I(VDD)) - N(2 I(OUT)) - N(3 I(VSS)) - N(4 I(NWELL)) - N(5 I(IN)) - N(6 I(BULK)) - P(1 I(VDD)) - P(2 I(OUT)) - P(3 I(VSS)) - P(4 I(NWELL)) - P(5 I(IN)) - P(6 I(BULK)) - D(1 PMOS - I($1) - E(L 0.25) - E(W 1.5) - E(AS 0) - E(AD 0) - E(PS 0) - E(PD 0) - T(S 1) - T(G 5) - T(D 2) - T(B 4) - ) - D(2 NMOS - I($2) - E(L 0.25) - E(W 0.95) - E(AS 0) - E(AD 0) - E(PS 0) - E(PD 0) - T(S 3) - T(G 5) - T(D 2) - T(B 6) - ) - ) - X(RINGO - N(1 I(VSS)) - N(2 I(VDD)) - N(3 I(FB)) - N(4 I(ENABLE)) - N(5 I(OUT)) - N(6 I('1')) - N(7 I('2')) - N(8 I('3')) - N(9 I('4')) - N(10 I('5')) - N(11 I('6')) - N(12 I('7')) - N(13 I('8')) - N(14 I('9')) - N(15 I('10')) - P(1 I(VSS)) - P(2 I(VDD)) - P(3 I(FB)) - P(4 I(ENABLE)) - P(5 I(OUT)) - X(1 ND2X1 I($1) - P(0 2) - P(1 6) - P(2 1) - P(3 2) - P(4 3) - P(5 4) - P(6 1) - ) - X(2 INVX1 I($2) - P(0 2) - P(1 7) - P(2 1) - P(3 2) - P(4 6) - P(5 1) - ) - X(3 INVX1 I($3) - P(0 2) - P(1 8) - P(2 1) - P(3 2) - P(4 7) - P(5 1) - ) - X(4 INVX1 I($4) - P(0 2) - P(1 9) - P(2 1) - P(3 2) - P(4 8) - P(5 1) - ) - X(5 INVX1 I($5) - P(0 2) - P(1 10) - P(2 1) - P(3 2) - P(4 9) - P(5 1) - ) - X(6 INVX1 I($6) - P(0 2) - P(1 11) - P(2 1) - P(3 2) - P(4 10) - P(5 1) - ) - X(7 INVX1 I($7) - P(0 2) - P(1 12) - P(2 1) - P(3 2) - P(4 11) - P(5 1) - ) - X(8 INVX1 I($8) - P(0 2) - P(1 13) - P(2 1) - P(3 2) - P(4 12) - P(5 1) - ) - X(9 INVX1 I($9) - P(0 2) - P(1 14) - P(2 1) - P(3 2) - P(4 13) - P(5 1) - ) - X(10 INVX1 I($10) - P(0 2) - P(1 15) - P(2 1) - P(3 2) - P(4 14) - P(5 1) - ) - X(11 INVX1 I($11) - P(0 2) - P(1 3) - P(2 1) - P(3 2) - P(4 15) - P(5 1) - ) - X(12 INVX1 I($12) - P(0 2) - P(1 5) - P(2 1) - P(3 2) - P(4 3) - P(5 1) - ) - ) -) -Z( - X(INVX1 INVX1 1 - Z( - N(4 4 1) - N(5 5 1) - N(2 2 1) - N(6 6 1) - N(1 1 1) - N(3 3 1) - P(3 3 1) - P(4 4 1) - P(1 1 1) - P(5 5 1) - P(0 0 1) - P(2 2 1) - D(2 2 1) - D(1 1 1) - ) - ) - X(ND2X1 ND2X1 1 - Z( - N(8 8 1) - N(4 4 1) - N(6 6 1) - N(5 5 1) - N(2 2 1) - N(7 7 1) - N(1 1 1) - N(3 3 1) - P(3 3 1) - P(5 5 1) - P(4 4 1) - P(1 1 1) - P(6 6 1) - P(0 0 1) - P(2 2 1) - D(3 3 1) - D(4 4 1) - D(1 1 1) - D(2 2 1) - ) - ) - X(RINGO RINGO 1 - Z( - N(1 6 1) - N(10 15 1) - N(2 7 1) - N(3 8 1) - N(4 9 1) - N(5 10 1) - N(6 11 1) - N(7 12 1) - N(8 13 1) - N(9 14 1) - N(14 4 1) - N(11 3 1) - N(13 5 1) - N(12 2 1) - N(15 1 1) - P(3 3 1) - P(0 2 1) - P(2 4 1) - P(1 1 1) - P(4 0 1) - X(2 2 1) - X(3 3 1) - X(4 4 1) - X(5 5 1) - X(6 6 1) - X(7 7 1) - X(8 8 1) - X(9 9 1) - X(10 10 1) - X(11 11 1) - X(12 12 1) - X(1 1 1) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_io2.l2n.1 b/testdata/lvs/ringo_simple_io2.l2n.1 index 3d7cc23b1..ca7ecbc14 100644 --- a/testdata/lvs/ringo_simple_io2.l2n.1 +++ b/testdata/lvs/ringo_simple_io2.l2n.1 @@ -318,70 +318,37 @@ X(INVX1 X(RINGO R((0 350) (25800 7650)) N(1 - R(l8 (4710 3010) (180 180)) - R(l11 (-850 -240) (610 300)) - R(l2 (-2550 1800) (425 1500)) - R(l2 (950 -1500) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (4040 2950) (610 300)) ) N(2 - R(l8 (6510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (5550 2950) (900 300)) ) N(3 - R(l8 (8310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (7350 2950) (900 300)) ) N(4 - R(l8 (10110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (9150 2950) (900 300)) ) N(5 - R(l8 (11910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (10950 2950) (900 300)) ) N(6 - R(l8 (13710 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (12750 2950) (900 300)) ) N(7 - R(l8 (15510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (14550 2950) (900 300)) ) N(8 - R(l8 (17310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (16350 2950) (900 300)) ) N(9 - R(l8 (19110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (18150 2950) (900 300)) ) N(10 - R(l8 (20910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) + R(l11 (19950 2950) (900 300)) ) N(11 I(FB) - R(l8 (22710 3010) (180 180)) - R(l8 (-19700 720) (180 180)) - R(l11 (18380 -1140) (900 300)) + R(l11 (21750 2950) (900 300)) R(l11 (-19530 590) (320 320)) R(l11 (17820 -320) (320 320)) R(l12 (-18400 -260) (200 200)) @@ -390,8 +357,6 @@ X(RINGO R(l13 (-17921 -201) (2 2)) R(l13 (-221 -201) (400 400)) R(l13 (17740 -400) (400 400)) - R(l2 (-245 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) ) N(12 I(VDD) R(l3 (500 4500) (1400 3500)) @@ -413,20 +378,7 @@ X(RINGO R(l11 (-750 -1450) (300 1400)) R(l11 (-101 -351) (2 2)) R(l11 (549 -401) (600 800)) - R(l2 (-23025 -2550) (425 1500)) - R(l2 (-400 -1500) (425 1500)) - R(l2 (1275 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l9 (-21975 -450) (500 1500)) + R(l9 (-24850 -1500) (500 1500)) R(l9 (22900 -1500) (500 1500)) ) N(13 I(OUT) @@ -434,12 +386,9 @@ X(RINGO R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) - R(l2 (-625 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) ) N(14 I(ENABLE) - R(l8 (2510 3010) (180 180)) - R(l11 (-250 -250) (320 320)) + R(l11 (2440 2940) (320 320)) R(l12 (-260 -260) (200 200)) R(l13 (-101 -101) (2 2)) R(l13 (-201 -201) (400 400)) @@ -460,19 +409,7 @@ X(RINGO R(l11 (-750 -1450) (1200 800)) R(l11 (-551 -401) (2 2)) R(l11 (549 -401) (600 800)) - R(l6 (-23700 460) (425 950)) - R(l6 (1975 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l10 (-21975 -2210) (500 1500)) + R(l10 (-24850 -800) (500 1500)) R(l10 (22900 -1500) (500 1500)) ) P(11 I(FB)) diff --git a/testdata/lvs/ringo_simple_io2.l2n.2 b/testdata/lvs/ringo_simple_io2.l2n.2 deleted file mode 100644 index 715c73183..000000000 --- a/testdata/lvs/ringo_simple_io2.l2n.2 +++ /dev/null @@ -1,580 +0,0 @@ -#%l2n-klayout -W(RINGO) -U(0.001) -L(l3 '1/0') -L(l4 '5/0') -L(l8 '8/0') -L(l11 '9/0') -L(l12 '10/0') -L(l13 '11/0') -L(l7) -L(l2) -L(l9) -L(l6) -L(l10) -C(l3 l3 l9) -C(l4 l4 l8) -C(l8 l4 l8 l11 l2 l9 l6 l10) -C(l11 l8 l11 l12) -C(l12 l11 l12 l13) -C(l13 l12 l13) -C(l7 l7) -C(l2 l8 l2) -C(l9 l3 l8 l9) -C(l6 l8 l6) -C(l10 l8 l10) -G(l7 SUBSTRATE) -G(l10 SUBSTRATE) -D(D$PMOS PMOS - T(S - R(l2 (-550 -750) (425 1500)) - ) - T(G - R(l4 (-125 -750) (250 1500)) - ) - T(D - R(l2 (125 -750) (450 1500)) - ) - T(B - R(l3 (-125 -750) (250 1500)) - ) -) -D(D$PMOS$1 PMOS - T(S - R(l2 (-575 -750) (450 1500)) - ) - T(G - R(l4 (-125 -750) (250 1500)) - ) - T(D - R(l2 (125 -750) (425 1500)) - ) - T(B - R(l3 (-125 -750) (250 1500)) - ) -) -D(D$PMOS$2 PMOS - T(S - R(l2 (-550 -750) (425 1500)) - ) - T(G - R(l4 (-125 -750) (250 1500)) - ) - T(D - R(l2 (125 -750) (425 1500)) - ) - T(B - R(l3 (-125 -750) (250 1500)) - ) -) -D(D$NMOS NMOS - T(S - R(l6 (-550 -475) (425 950)) - ) - T(G - R(l4 (-125 -475) (250 950)) - ) - T(D - R(l6 (125 -475) (450 950)) - ) - T(B - R(l7 (-125 -475) (250 950)) - ) -) -D(D$NMOS$1 NMOS - T(S - R(l6 (-575 -475) (450 950)) - ) - T(G - R(l4 (-125 -475) (250 950)) - ) - T(D - R(l6 (125 -475) (425 950)) - ) - T(B - R(l7 (-125 -475) (250 950)) - ) -) -D(D$NMOS$2 NMOS - T(S - R(l6 (-550 -475) (425 950)) - ) - T(G - R(l4 (-125 -475) (250 950)) - ) - T(D - R(l6 (125 -475) (425 950)) - ) - T(B - R(l7 (-125 -475) (250 950)) - ) -) -X(ND2X1 - R((-100 400) (2600 7600)) - N(1 I(VDD) - R(l8 (1110 5160) (180 180)) - R(l8 (-180 920) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l11 (-240 -790) (300 1700)) - R(l11 (-1350 0) (2400 800)) - R(l11 (-1151 -401) (2 2)) - R(l2 (-276 -2151) (425 1500)) - R(l2 (-400 -1500) (425 1500)) - ) - N(2 I(OUT) - R(l8 (1810 1770) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (-1580 3760) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (1220 920) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (-180 370) (180 180)) - Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - R(l11 (-110 1390) (300 1400)) - Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - R(l11 (-141 -501) (2 2)) - R(l11 (-1751 1099) (300 1400)) - R(l11 (1100 -1700) (300 300)) - R(l11 (-300 0) (300 1400)) - R(l2 (-375 -1450) (425 1500)) - R(l2 (-1800 -1500) (425 1500)) - R(l6 (950 -4890) (425 950)) - ) - N(3 I(VSS) - R(l8 (410 1770) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-240 -1300) (300 1360)) - R(l11 (-650 -2160) (2400 800)) - R(l11 (-1151 -401) (2 2)) - R(l6 (-951 859) (425 950)) - ) - N(4 - R(l3 (-100 4500) (2600 3500)) - ) - N(5 I(B) - R(l4 (1425 2860) (250 1940)) - R(l4 (-345 -950) (300 300)) - R(l4 (-205 650) (250 2000)) - R(l4 (-250 -2000) (250 2000)) - R(l4 (-250 -5390) (250 1450)) - R(l8 (-285 1050) (180 180)) - R(l11 (-71 -91) (2 2)) - R(l11 (-171 -151) (300 300)) - ) - N(6 I(A) - R(l4 (725 2860) (250 1940)) - R(l4 (-325 -1850) (300 300)) - R(l4 (-225 1550) (250 2000)) - R(l4 (-250 -2000) (250 2000)) - R(l4 (-250 -5390) (250 1450)) - R(l8 (-265 150) (180 180)) - R(l11 (-91 -91) (2 2)) - R(l11 (-151 -151) (300 300)) - ) - N(7 I(SUBSTRATE)) - N(8 - R(l6 (975 1660) (425 950)) - R(l6 (-400 -950) (425 950)) - ) - P(1 I(VDD)) - P(2 I(OUT)) - P(3 I(VSS)) - P(4) - P(5 I(B)) - P(6 I(A)) - P(7 I(SUBSTRATE)) - D(1 D$PMOS - Y(850 5800) - E(L 0.25) - E(W 1.5) - E(AS 0.6375) - E(AD 0.3375) - E(PS 3.85) - E(PD 1.95) - T(S 2) - T(G 6) - T(D 1) - T(B 4) - ) - D(2 D$PMOS$1 - Y(1550 5800) - E(L 0.25) - E(W 1.5) - E(AS 0.3375) - E(AD 0.6375) - E(PS 1.95) - E(PD 3.85) - T(S 1) - T(G 5) - T(D 2) - T(B 4) - ) - D(3 D$NMOS - Y(850 2135) - E(L 0.25) - E(W 0.95) - E(AS 0.40375) - E(AD 0.21375) - E(PS 2.75) - E(PD 1.4) - T(S 3) - T(G 6) - T(D 8) - T(B 7) - ) - D(4 D$NMOS$1 - Y(1550 2135) - E(L 0.25) - E(W 0.95) - E(AS 0.21375) - E(AD 0.40375) - E(PS 1.4) - E(PD 2.75) - T(S 8) - T(G 5) - T(D 2) - T(B 7) - ) -) -X(INVX1 - R((-100 400) (2000 7600)) - N(1 I(VDD) - R(l8 (410 6260) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l11 (-240 -240) (300 1400)) - R(l11 (-650 300) (1800 800)) - R(l11 (-1450 -1100) (300 300)) - R(l11 (299 399) (2 2)) - R(l2 (-651 -2151) (425 1500)) - ) - N(2 I(OUT) - R(l8 (1110 5160) (180 180)) - R(l8 (-180 920) (180 180)) - R(l8 (-180 -730) (180 180)) - R(l8 (-180 -4120) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-240 -790) (300 4790)) - R(l11 (-151 -2501) (2 2)) - R(l2 (-226 1049) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(3 I(VSS) - R(l8 (410 1770) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-240 -1300) (300 1360)) - R(l11 (-650 -2160) (1800 800)) - R(l11 (-851 -401) (2 2)) - R(l6 (-651 859) (425 950)) - ) - N(4 - R(l3 (-100 4500) (2000 3500)) - ) - N(5 I(IN) - R(l4 (725 2860) (250 1940)) - R(l4 (-525 -1850) (300 300)) - R(l4 (-25 1550) (250 2000)) - R(l4 (-250 -2000) (250 2000)) - R(l4 (-250 -5390) (250 1450)) - R(l8 (-465 150) (180 180)) - R(l11 (-91 -91) (2 2)) - R(l11 (-151 -151) (300 300)) - ) - N(6 I(SUBSTRATE)) - P(1 I(VDD)) - P(2 I(OUT)) - P(3 I(VSS)) - P(4) - P(5 I(IN)) - P(6 I(SUBSTRATE)) - D(1 D$PMOS$2 - Y(850 5800) - E(L 0.25) - E(W 1.5) - E(AS 0.6375) - E(AD 0.6375) - E(PS 3.85) - E(PD 3.85) - T(S 1) - T(G 5) - T(D 2) - T(B 4) - ) - D(2 D$NMOS$2 - Y(850 2135) - E(L 0.25) - E(W 0.95) - E(AS 0.40375) - E(AD 0.40375) - E(PS 2.75) - E(PD 2.75) - T(S 3) - T(G 5) - T(D 2) - T(B 6) - ) -) -X(RINGO - R((0 350) (25800 7650)) - N(1 - R(l8 (4710 3010) (180 180)) - R(l11 (-850 -240) (610 300)) - R(l2 (-1175 1800) (425 1500)) - R(l2 (-1800 -1500) (425 1500)) - R(l6 (950 -4890) (425 950)) - ) - N(2 - R(l8 (6510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(3 - R(l8 (8310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(4 - R(l8 (10110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(5 - R(l8 (11910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(6 - R(l8 (13710 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(7 - R(l8 (15510 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(8 - R(l8 (17310 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(9 - R(l8 (19110 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(10 - R(l8 (20910 3010) (180 180)) - R(l11 (-1140 -240) (900 300)) - R(l2 (-1275 1800) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(11 I(FB) - R(l8 (22710 3010) (180 180)) - R(l8 (-19700 720) (180 180)) - R(l11 (18380 -1140) (900 300)) - R(l11 (-19530 590) (320 320)) - R(l11 (17820 -320) (320 320)) - R(l12 (-18400 -260) (200 200)) - R(l12 (17940 -200) (200 200)) - R(l13 (-18040 -300) (17740 400)) - R(l13 (-17921 -201) (2 2)) - R(l13 (-221 -201) (400 400)) - R(l13 (17740 -400) (400 400)) - R(l2 (-245 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(12 I(VDD) - R(l3 (500 4500) (1400 3500)) - R(l3 (-1900 -3500) (600 3500)) - R(l3 (23300 -3500) (1400 3500)) - R(l3 (-100 -3500) (600 3500)) - R(l8 (-24690 -1240) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (23220 370) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l11 (-21741 859) (2 2)) - R(l11 (-2351 -451) (1200 800)) - R(l11 (-750 -1450) (300 1400)) - R(l11 (-101 -351) (2 2)) - R(l11 (-1251 -401) (600 800)) - R(l11 (23400 -800) (1200 800)) - R(l11 (-750 -1450) (300 1400)) - R(l11 (-101 -351) (2 2)) - R(l11 (549 -401) (600 800)) - R(l2 (-23025 -2550) (425 1500)) - R(l2 (-400 -1500) (425 1500)) - R(l2 (1275 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l2 (1375 -1500) (425 1500)) - R(l9 (-21975 -450) (500 1500)) - R(l9 (22900 -1500) (500 1500)) - ) - N(13 I(OUT) - R(l11 (23440 3840) (320 320)) - R(l12 (-260 -260) (200 200)) - R(l13 (-101 -101) (2 2)) - R(l13 (-201 -201) (400 400)) - R(l2 (-625 850) (425 1500)) - R(l6 (-425 -4890) (425 950)) - ) - N(14 I(ENABLE) - R(l8 (2510 3010) (180 180)) - R(l11 (-250 -250) (320 320)) - R(l12 (-260 -260) (200 200)) - R(l13 (-101 -101) (2 2)) - R(l13 (-201 -201) (400 400)) - ) - N(15 I(VSS) - R(l8 (1110 1610) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (-180 370) (180 180)) - R(l8 (23220 370) (180 180)) - R(l8 (-180 -1280) (180 180)) - R(l8 (-180 370) (180 180)) - R(l11 (-21741 -391) (2 2)) - R(l11 (-1901 -401) (300 1400)) - R(l11 (-750 -1450) (1200 800)) - R(l11 (-551 -401) (2 2)) - R(l11 (-1251 -401) (600 800)) - R(l11 (23850 -750) (300 1400)) - R(l11 (-750 -1450) (1200 800)) - R(l11 (-551 -401) (2 2)) - R(l11 (549 -401) (600 800)) - R(l6 (-23700 460) (425 950)) - R(l6 (1975 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l6 (1375 -950) (425 950)) - R(l10 (-21975 -2210) (500 1500)) - R(l10 (22900 -1500) (500 1500)) - ) - P(11 I(FB)) - P(12 I(VDD)) - P(13 I(OUT)) - P(14 I(ENABLE)) - P(15 I(VSS)) - X(1 ND2X1 Y(1800 0) - P(0 12) - P(1 1) - P(2 15) - P(3 12) - P(4 11) - P(5 14) - P(6 15) - ) - X(2 INVX1 Y(4200 0) - P(0 12) - P(1 2) - P(2 15) - P(3 12) - P(4 1) - P(5 15) - ) - X(3 INVX1 Y(6000 0) - P(0 12) - P(1 3) - P(2 15) - P(3 12) - P(4 2) - P(5 15) - ) - X(4 INVX1 Y(7800 0) - P(0 12) - P(1 4) - P(2 15) - P(3 12) - P(4 3) - P(5 15) - ) - X(5 INVX1 Y(9600 0) - P(0 12) - P(1 5) - P(2 15) - P(3 12) - P(4 4) - P(5 15) - ) - X(6 INVX1 Y(11400 0) - P(0 12) - P(1 6) - P(2 15) - P(3 12) - P(4 5) - P(5 15) - ) - X(7 INVX1 Y(13200 0) - P(0 12) - P(1 7) - P(2 15) - P(3 12) - P(4 6) - P(5 15) - ) - X(8 INVX1 Y(15000 0) - P(0 12) - P(1 8) - P(2 15) - P(3 12) - P(4 7) - P(5 15) - ) - X(9 INVX1 Y(16800 0) - P(0 12) - P(1 9) - P(2 15) - P(3 12) - P(4 8) - P(5 15) - ) - X(10 INVX1 Y(18600 0) - P(0 12) - P(1 10) - P(2 15) - P(3 12) - P(4 9) - P(5 15) - ) - X(11 INVX1 Y(20400 0) - P(0 12) - P(1 11) - P(2 15) - P(3 12) - P(4 10) - P(5 15) - ) - X(12 INVX1 Y(22200 0) - P(0 12) - P(1 13) - P(2 15) - P(3 12) - P(4 11) - P(5 15) - ) -) diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.1 b/testdata/lvs/ringo_simple_io2.lvsdb.1 index a68dae475..b4494918c 100644 --- a/testdata/lvs/ringo_simple_io2.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io2.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,20 +422,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -478,12 +430,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -504,19 +453,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.2 b/testdata/lvs/ringo_simple_io2.lvsdb.2 deleted file mode 100644 index 834cc43fe..000000000 --- a/testdata/lvs/ringo_simple_io2.lvsdb.2 +++ /dev/null @@ -1,971 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 index bee7ccfc8..a43d6f458 100644 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,20 +422,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -478,12 +430,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -504,19 +453,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 deleted file mode 100644 index f57553a48..000000000 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 +++ /dev/null @@ -1,970 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(top) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(nd2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INV - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(top - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 nd2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INV location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INV location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INV location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INV location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INV location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INV location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INV location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INV location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INV location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INV location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INV location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INV INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(nd2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(top RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 index 4c98e224d..42ac52dd1 100644 --- a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 +++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 @@ -362,70 +362,37 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -434,8 +401,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -457,20 +422,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -478,12 +430,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -504,19 +453,7 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 deleted file mode 100644 index 45cc8683d..000000000 --- a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 +++ /dev/null @@ -1,971 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(7 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(8 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(9 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(10 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21741 859) (2 2)) - rect(l11 (-2351 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23025 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l9 (-21975 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l8 (1110 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-21741 -391) (2 2)) - rect(l11 (-1901 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-23700 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l10 (-21975 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(A)) - net(6 name(B)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(A)) - pin(6 name(B)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 5) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 6) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 6) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 5 match) - net(5 6 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 4 match) - pin(4 5 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 index bff454e1e..1260655ac 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 @@ -364,70 +364,37 @@ layout( # Nets with their geometries net(1 - rect(l14 (4710 3010) (180 180)) - rect(l17 (-850 -240) (610 300)) - rect(l4 (-2550 1800) (425 1500)) - rect(l4 (950 -1500) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (4040 2950) (610 300)) ) net(2 - rect(l14 (6510 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (5550 2950) (900 300)) ) net(3 - rect(l14 (8310 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (7350 2950) (900 300)) ) net(4 - rect(l14 (10110 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (9150 2950) (900 300)) ) net(5 - rect(l14 (11910 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (10950 2950) (900 300)) ) net(6 - rect(l14 (13710 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (12750 2950) (900 300)) ) net(7 - rect(l14 (15510 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (14550 2950) (900 300)) ) net(8 - rect(l14 (17310 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (16350 2950) (900 300)) ) net(9 - rect(l14 (19110 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (18150 2950) (900 300)) ) net(10 - rect(l14 (20910 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) + rect(l17 (19950 2950) (900 300)) ) net(11 name(FB) - rect(l14 (22710 3010) (180 180)) - rect(l14 (-19700 720) (180 180)) - rect(l17 (18380 -1140) (900 300)) + rect(l17 (21750 2950) (900 300)) rect(l17 (-19530 590) (320 320)) rect(l17 (17820 -320) (320 320)) rect(l18 (-18400 -260) (200 200)) @@ -436,8 +403,6 @@ layout( rect(l19 (-17921 -201) (2 2)) rect(l19 (-221 -201) (400 400)) rect(l19 (17740 -400) (400 400)) - rect(l4 (-245 850) (425 1500)) - rect(l9 (-425 -4890) (425 950)) ) net(12 name(VDD) rect(l3 (500 4500) (1400 3500)) @@ -459,20 +424,7 @@ layout( rect(l17 (-750 -1450) (300 1400)) rect(l17 (-101 -351) (2 2)) rect(l17 (549 -401) (600 800)) - rect(l4 (-23025 -2550) (425 1500)) - rect(l4 (-400 -1500) (425 1500)) - rect(l4 (1275 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l15 (-21975 -450) (500 1500)) + rect(l15 (-24850 -1500) (500 1500)) rect(l15 (22900 -1500) (500 1500)) ) net(13 name(OUT) @@ -480,12 +432,9 @@ layout( rect(l18 (-260 -260) (200 200)) rect(l19 (-101 -101) (2 2)) rect(l19 (-201 -201) (400 400)) - rect(l4 (-625 850) (425 1500)) - rect(l9 (-425 -4890) (425 950)) ) net(14 name(ENABLE) - rect(l14 (2510 3010) (180 180)) - rect(l17 (-250 -250) (320 320)) + rect(l17 (2440 2940) (320 320)) rect(l18 (-260 -260) (200 200)) rect(l19 (-101 -101) (2 2)) rect(l19 (-201 -201) (400 400)) @@ -506,19 +455,7 @@ layout( rect(l17 (-750 -1450) (1200 800)) rect(l17 (-551 -401) (2 2)) rect(l17 (549 -401) (600 800)) - rect(l9 (-23700 460) (425 950)) - rect(l9 (1975 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l16 (-21975 -2210) (500 1500)) + rect(l16 (-24850 -800) (500 1500)) rect(l16 (22900 -1500) (500 1500)) ) diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 deleted file mode 100644 index 2d7583393..000000000 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 +++ /dev/null @@ -1,973 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l5 '5/0') - layer(l14 '8/0') - layer(l17 '9/0') - layer(l18 '10/0') - layer(l19 '11/0') - layer(l8) - layer(l4) - layer(l15) - layer(l9) - layer(l16) - - # Mask layer connectivity - connect(l3 l3 l15) - connect(l5 l5 l14) - connect(l14 l5 l14 l17 l4 l15 l9 l16) - connect(l17 l14 l17 l18) - connect(l18 l17 l18 l19) - connect(l19 l18 l19) - connect(l8 l8) - connect(l4 l14 l4) - connect(l15 l3 l14 l15) - connect(l9 l14 l9) - connect(l16 l14 l16) - - # Global nets and connectivity - global(l8 SUBSTRATE) - global(l16 SUBSTRATE) - - # Device class section - class(PM MOS4) - class(NM MOS4) - class(PMHV MOS4) - class(NMHV MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PM PM - terminal(S - rect(l4 (-550 -750) (425 1500)) - ) - terminal(G - rect(l5 (-125 -750) (250 1500)) - ) - terminal(D - rect(l4 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PM$1 PM - terminal(S - rect(l4 (-575 -750) (450 1500)) - ) - terminal(G - rect(l5 (-125 -750) (250 1500)) - ) - terminal(D - rect(l4 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PM$2 PM - terminal(S - rect(l4 (-550 -750) (425 1500)) - ) - terminal(G - rect(l5 (-125 -750) (250 1500)) - ) - terminal(D - rect(l4 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NM NM - terminal(S - rect(l9 (-550 -475) (425 950)) - ) - terminal(G - rect(l5 (-125 -475) (250 950)) - ) - terminal(D - rect(l9 (125 -475) (450 950)) - ) - terminal(B - rect(l8 (-125 -475) (250 950)) - ) - ) - device(D$NM$1 NM - terminal(S - rect(l9 (-575 -475) (450 950)) - ) - terminal(G - rect(l5 (-125 -475) (250 950)) - ) - terminal(D - rect(l9 (125 -475) (425 950)) - ) - terminal(B - rect(l8 (-125 -475) (250 950)) - ) - ) - device(D$NM$2 NM - terminal(S - rect(l9 (-550 -475) (425 950)) - ) - terminal(G - rect(l5 (-125 -475) (250 950)) - ) - terminal(D - rect(l9 (125 -475) (425 950)) - ) - terminal(B - rect(l8 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l14 (1110 5160) (180 180)) - rect(l14 (-180 920) (180 180)) - rect(l14 (-180 -730) (180 180)) - rect(l17 (-240 -790) (300 1700)) - rect(l17 (-1350 0) (2400 800)) - rect(l17 (-1151 -401) (2 2)) - rect(l4 (-276 -2151) (425 1500)) - rect(l4 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l14 (1810 1770) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l14 (-1580 3760) (180 180)) - rect(l14 (-180 -730) (180 180)) - rect(l14 (-180 -730) (180 180)) - rect(l14 (1220 920) (180 180)) - rect(l14 (-180 -1280) (180 180)) - rect(l14 (-180 370) (180 180)) - polygon(l17 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l17 (-110 1390) (300 1400)) - polygon(l17 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l17 (-141 -501) (2 2)) - rect(l17 (-1751 1099) (300 1400)) - rect(l17 (1100 -1700) (300 300)) - rect(l17 (-300 0) (300 1400)) - rect(l4 (-375 -1450) (425 1500)) - rect(l4 (-1800 -1500) (425 1500)) - rect(l9 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l14 (410 1770) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l17 (-240 -1300) (300 1360)) - rect(l17 (-650 -2160) (2400 800)) - rect(l17 (-1151 -401) (2 2)) - rect(l9 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l5 (1425 2860) (250 1940)) - rect(l5 (-345 -950) (300 300)) - rect(l5 (-205 650) (250 2000)) - rect(l5 (-250 -2000) (250 2000)) - rect(l5 (-250 -5390) (250 1450)) - rect(l14 (-285 1050) (180 180)) - rect(l17 (-71 -91) (2 2)) - rect(l17 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l5 (725 2860) (250 1940)) - rect(l5 (-325 -1850) (300 300)) - rect(l5 (-225 1550) (250 2000)) - rect(l5 (-250 -2000) (250 2000)) - rect(l5 (-250 -5390) (250 1450)) - rect(l14 (-265 150) (180 180)) - rect(l17 (-91 -91) (2 2)) - rect(l17 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l9 (975 1660) (425 950)) - rect(l9 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PM - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PM$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NM - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NM$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l14 (410 6260) (180 180)) - rect(l14 (-180 -730) (180 180)) - rect(l14 (-180 -730) (180 180)) - rect(l17 (-240 -240) (300 1400)) - rect(l17 (-650 300) (1800 800)) - rect(l17 (-1450 -1100) (300 300)) - rect(l17 (299 399) (2 2)) - rect(l4 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l14 (1110 5160) (180 180)) - rect(l14 (-180 920) (180 180)) - rect(l14 (-180 -730) (180 180)) - rect(l14 (-180 -4120) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l17 (-240 -790) (300 4790)) - rect(l17 (-151 -2501) (2 2)) - rect(l4 (-226 1049) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l14 (410 1770) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l17 (-240 -1300) (300 1360)) - rect(l17 (-650 -2160) (1800 800)) - rect(l17 (-851 -401) (2 2)) - rect(l9 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l5 (725 2860) (250 1940)) - rect(l5 (-525 -1850) (300 300)) - rect(l5 (-25 1550) (250 2000)) - rect(l5 (-250 -2000) (250 2000)) - rect(l5 (-250 -5390) (250 1450)) - rect(l14 (-465 150) (180 180)) - rect(l17 (-91 -91) (2 2)) - rect(l17 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PM$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NM$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l14 (4710 3010) (180 180)) - rect(l17 (-850 -240) (610 300)) - rect(l4 (-1175 1800) (425 1500)) - rect(l4 (-1800 -1500) (425 1500)) - rect(l9 (950 -4890) (425 950)) - ) - net(2 - rect(l14 (6510 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(3 - rect(l14 (8310 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(4 - rect(l14 (10110 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(5 - rect(l14 (11910 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(6 - rect(l14 (13710 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(7 - rect(l14 (15510 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(8 - rect(l14 (17310 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(9 - rect(l14 (19110 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(10 - rect(l14 (20910 3010) (180 180)) - rect(l17 (-1140 -240) (900 300)) - rect(l4 (-1275 1800) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(11 name(FB) - rect(l14 (22710 3010) (180 180)) - rect(l14 (-19700 720) (180 180)) - rect(l17 (18380 -1140) (900 300)) - rect(l17 (-19530 590) (320 320)) - rect(l17 (17820 -320) (320 320)) - rect(l18 (-18400 -260) (200 200)) - rect(l18 (17940 -200) (200 200)) - rect(l19 (-18040 -300) (17740 400)) - rect(l19 (-17921 -201) (2 2)) - rect(l19 (-221 -201) (400 400)) - rect(l19 (17740 -400) (400 400)) - rect(l4 (-245 850) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(12 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l14 (-24690 -1240) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l14 (-180 -1280) (180 180)) - rect(l14 (23220 370) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l14 (-180 -1280) (180 180)) - rect(l17 (-21741 859) (2 2)) - rect(l17 (-2351 -451) (1200 800)) - rect(l17 (-750 -1450) (300 1400)) - rect(l17 (-101 -351) (2 2)) - rect(l17 (-1251 -401) (600 800)) - rect(l17 (23400 -800) (1200 800)) - rect(l17 (-750 -1450) (300 1400)) - rect(l17 (-101 -351) (2 2)) - rect(l17 (549 -401) (600 800)) - rect(l4 (-23025 -2550) (425 1500)) - rect(l4 (-400 -1500) (425 1500)) - rect(l4 (1275 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l4 (1375 -1500) (425 1500)) - rect(l15 (-21975 -450) (500 1500)) - rect(l15 (22900 -1500) (500 1500)) - ) - net(13 name(OUT) - rect(l17 (23440 3840) (320 320)) - rect(l18 (-260 -260) (200 200)) - rect(l19 (-101 -101) (2 2)) - rect(l19 (-201 -201) (400 400)) - rect(l4 (-625 850) (425 1500)) - rect(l9 (-425 -4890) (425 950)) - ) - net(14 name(ENABLE) - rect(l14 (2510 3010) (180 180)) - rect(l17 (-250 -250) (320 320)) - rect(l18 (-260 -260) (200 200)) - rect(l19 (-101 -101) (2 2)) - rect(l19 (-201 -201) (400 400)) - ) - net(15 name(VSS) - rect(l14 (1110 1610) (180 180)) - rect(l14 (-180 -1280) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l14 (23220 370) (180 180)) - rect(l14 (-180 -1280) (180 180)) - rect(l14 (-180 370) (180 180)) - rect(l17 (-21741 -391) (2 2)) - rect(l17 (-1901 -401) (300 1400)) - rect(l17 (-750 -1450) (1200 800)) - rect(l17 (-551 -401) (2 2)) - rect(l17 (-1251 -401) (600 800)) - rect(l17 (23850 -750) (300 1400)) - rect(l17 (-750 -1450) (1200 800)) - rect(l17 (-551 -401) (2 2)) - rect(l17 (549 -401) (600 800)) - rect(l9 (-23700 460) (425 950)) - rect(l9 (1975 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l9 (1375 -950) (425 950)) - rect(l16 (-21975 -2210) (500 1500)) - rect(l16 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(11 name(FB)) - pin(12 name(VDD)) - pin(13 name(OUT)) - pin(14 name(ENABLE)) - pin(15 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 12) - pin(1 1) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 14) - pin(6 15) - ) - circuit(2 INVX1 location(4200 0) - pin(0 12) - pin(1 2) - pin(2 15) - pin(3 12) - pin(4 1) - pin(5 15) - ) - circuit(3 INVX1 location(6000 0) - pin(0 12) - pin(1 3) - pin(2 15) - pin(3 12) - pin(4 2) - pin(5 15) - ) - circuit(4 INVX1 location(7800 0) - pin(0 12) - pin(1 4) - pin(2 15) - pin(3 12) - pin(4 3) - pin(5 15) - ) - circuit(5 INVX1 location(9600 0) - pin(0 12) - pin(1 5) - pin(2 15) - pin(3 12) - pin(4 4) - pin(5 15) - ) - circuit(6 INVX1 location(11400 0) - pin(0 12) - pin(1 6) - pin(2 15) - pin(3 12) - pin(4 5) - pin(5 15) - ) - circuit(7 INVX1 location(13200 0) - pin(0 12) - pin(1 7) - pin(2 15) - pin(3 12) - pin(4 6) - pin(5 15) - ) - circuit(8 INVX1 location(15000 0) - pin(0 12) - pin(1 8) - pin(2 15) - pin(3 12) - pin(4 7) - pin(5 15) - ) - circuit(9 INVX1 location(16800 0) - pin(0 12) - pin(1 9) - pin(2 15) - pin(3 12) - pin(4 8) - pin(5 15) - ) - circuit(10 INVX1 location(18600 0) - pin(0 12) - pin(1 10) - pin(2 15) - pin(3 12) - pin(4 9) - pin(5 15) - ) - circuit(11 INVX1 location(20400 0) - pin(0 12) - pin(1 11) - pin(2 15) - pin(3 12) - pin(4 10) - pin(5 15) - ) - circuit(12 INVX1 location(22200 0) - pin(0 12) - pin(1 13) - pin(2 15) - pin(3 12) - pin(4 11) - pin(5 15) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.1 b/testdata/lvs/ringo_simple_simplification.lvsdb.1 index b0e4b5871..fb0393863 100644 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.1 +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.1 @@ -484,34 +484,19 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -520,8 +505,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(6 name(VDD) rect(l3 (1100 4500) (1400 3500)) @@ -543,21 +526,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23625 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l2 (-3600 -1500) (425 1500)) - rect(l9 (-19575 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(7 name(OUT) @@ -565,14 +534,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) ) net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -593,57 +557,26 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-24300 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (950 -950) (425 950)) - rect(l6 (-3600 -950) (425 950)) - rect(l10 (-19575 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) # Outgoing pins and their connections to nets diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.2 b/testdata/lvs/ringo_simple_simplification.lvsdb.2 deleted file mode 100644 index 77e688c6e..000000000 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.2 +++ /dev/null @@ -1,1162 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-225 -1300) (675 450)) - rect(l4 (0 -1100) (250 1950)) - rect(l4 (-1225 -1850) (300 300)) - rect(l4 (675 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-950 -2000) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (450 -5390) (250 1450)) - rect(l4 (-950 -1450) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(2 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-1640 -240) (300 1400)) - rect(l11 (-650 300) (2400 800)) - rect(l11 (-2050 -1100) (300 300)) - rect(l11 (1100 -300) (300 300)) - rect(l11 (-1101 399) (2 2)) - rect(l11 (799 -2101) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - ) - net(3 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(4 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (1220 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-1640 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-650 0) (300 1360)) - rect(l11 (-1101 -1761) (2 2)) - rect(l6 (724 859) (425 950)) - rect(l6 (-1800 -950) (425 950)) - ) - net(5 - rect(l3 (-100 4500) (2600 3500)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(IN)) - pin(2 name(VDD)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 5800) - param(L 0.25) - param(W 3) - param(AS 0.975) - param(AD 0.975) - param(PS 5.8) - param(PD 5.8) - terminal(S 2) - terminal(G 1) - terminal(D 3) - terminal(B 5) - ) - device(3 D$NMOS - device(D$NMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 2135) - param(L 0.25) - param(W 1.9) - param(AS 0.6175) - param(AD 0.6175) - param(PS 4.15) - param(PD 4.15) - terminal(S 4) - terminal(G 1) - terminal(D 3) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((600 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 name(VDD) - rect(l3 (1100 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-22341 859) (2 2)) - rect(l11 (-1751 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23625 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l2 (-3600 -1500) (425 1500)) - rect(l9 (-19575 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(7 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(9 name(VSS) - rect(l8 (1710 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-22341 -391) (2 2)) - rect(l11 (-1301 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-24300 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (4550 -950) (425 950)) - rect(l6 (-1800 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-19575 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(5 name(FB)) - pin(6 name(VDD)) - pin(7 name(OUT)) - pin(8 name(ENABLE)) - pin(9 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 6) - pin(1 1) - pin(2 9) - pin(3 6) - pin(4 5) - pin(5 8) - pin(6 9) - ) - circuit(2 INVX1 location(4200 0) - pin(0 6) - pin(1 2) - pin(2 9) - pin(3 6) - pin(4 1) - pin(5 9) - ) - circuit(3 INVX1 location(6000 0) - pin(0 6) - pin(1 10) - pin(2 9) - pin(3 6) - pin(4 2) - pin(5 9) - ) - circuit(4 INVX1 location(16800 0) - pin(0 6) - pin(1 3) - pin(2 9) - pin(3 6) - pin(4 11) - pin(5 9) - ) - circuit(5 INVX1 location(18600 0) - pin(0 6) - pin(1 4) - pin(2 9) - pin(3 6) - pin(4 3) - pin(5 9) - ) - circuit(6 INVX1 location(20400 0) - pin(0 6) - pin(1 5) - pin(2 9) - pin(3 6) - pin(4 4) - pin(5 9) - ) - circuit(7 INVX2 location(22200 0) - pin(0 5) - pin(1 6) - pin(2 7) - pin(3 9) - pin(4 6) - pin(5 9) - ) - circuit(17 INVX1 location(7800 0) - pin(0 6) - pin(1 12) - pin(2 9) - pin(3 6) - pin(4 10) - pin(5 9) - ) - circuit(18 INVX1 location(9600 0) - pin(0 6) - pin(1 13) - pin(2 9) - pin(3 6) - pin(4 12) - pin(5 9) - ) - circuit(19 INVX1 location(11400 0) - pin(0 6) - pin(1 14) - pin(2 9) - pin(3 6) - pin(4 13) - pin(5 9) - ) - circuit(20 INVX1 location(13200 0) - pin(0 6) - pin(1 15) - pin(2 9) - pin(3 6) - pin(4 14) - pin(5 9) - ) - circuit(21 INVX1 location(15000 0) - pin(0 6) - pin(1 11) - pin(2 9) - pin(3 6) - pin(4 15) - pin(5 9) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX2 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX2 INVX2 match - xref( - net(5 4 match) - net(1 5 match) - net(3 2 match) - net(6 6 match) - net(2 1 match) - net(4 3 match) - pin(4 3 match) - pin(0 4 match) - pin(2 1 match) - pin(5 5 match) - pin(1 0 match) - pin(3 2 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(4 15 match) - net(2 7 match) - net(10 8 match) - net(12 9 match) - net(13 10 match) - net(14 11 match) - net(15 12 match) - net(11 13 match) - net(3 14 match) - net(8 4 match) - net(5 3 match) - net(7 5 match) - net(6 2 match) - net(9 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(17 4 match) - circuit(18 5 match) - circuit(19 6 match) - circuit(20 7 match) - circuit(21 8 match) - circuit(4 9 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.3 b/testdata/lvs/ringo_simple_simplification.lvsdb.3 deleted file mode 100644 index 2492067a3..000000000 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.3 +++ /dev/null @@ -1,1162 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-225 -1300) (675 450)) - rect(l4 (0 -1100) (250 1950)) - rect(l4 (-1225 -1850) (300 300)) - rect(l4 (675 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-950 -2000) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (450 -5390) (250 1450)) - rect(l4 (-950 -1450) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(2 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-1640 -240) (300 1400)) - rect(l11 (-650 300) (2400 800)) - rect(l11 (-2050 -1100) (300 300)) - rect(l11 (1100 -300) (300 300)) - rect(l11 (-1101 399) (2 2)) - rect(l11 (799 -2101) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - ) - net(3 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(4 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (1220 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-1640 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-650 0) (300 1360)) - rect(l11 (-1101 -1761) (2 2)) - rect(l6 (724 859) (425 950)) - rect(l6 (-1800 -950) (425 950)) - ) - net(5 - rect(l3 (-100 4500) (2600 3500)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(IN)) - pin(2 name(VDD)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 5800) - param(L 0.25) - param(W 3) - param(AS 0.975) - param(AD 0.975) - param(PS 5.8) - param(PD 5.8) - terminal(S 2) - terminal(G 1) - terminal(D 3) - terminal(B 5) - ) - device(3 D$NMOS - device(D$NMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 2135) - param(L 0.25) - param(W 1.9) - param(AS 0.6175) - param(AD 0.6175) - param(PS 4.15) - param(PD 4.15) - terminal(S 4) - terminal(G 1) - terminal(D 3) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((600 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 name(VDD) - rect(l3 (1100 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-22341 859) (2 2)) - rect(l11 (-1751 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23625 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (4550 -1500) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l9 (-19575 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(7 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(9 name(VSS) - rect(l8 (1710 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-22341 -391) (2 2)) - rect(l11 (-1301 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-24300 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (4550 -950) (425 950)) - rect(l6 (-1800 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-19575 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(5 name(FB)) - pin(6 name(VDD)) - pin(7 name(OUT)) - pin(8 name(ENABLE)) - pin(9 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 6) - pin(1 1) - pin(2 9) - pin(3 6) - pin(4 5) - pin(5 8) - pin(6 9) - ) - circuit(2 INVX1 location(4200 0) - pin(0 6) - pin(1 2) - pin(2 9) - pin(3 6) - pin(4 1) - pin(5 9) - ) - circuit(3 INVX1 location(6000 0) - pin(0 6) - pin(1 10) - pin(2 9) - pin(3 6) - pin(4 2) - pin(5 9) - ) - circuit(4 INVX1 location(16800 0) - pin(0 6) - pin(1 3) - pin(2 9) - pin(3 6) - pin(4 11) - pin(5 9) - ) - circuit(5 INVX1 location(18600 0) - pin(0 6) - pin(1 4) - pin(2 9) - pin(3 6) - pin(4 3) - pin(5 9) - ) - circuit(6 INVX1 location(20400 0) - pin(0 6) - pin(1 5) - pin(2 9) - pin(3 6) - pin(4 4) - pin(5 9) - ) - circuit(7 INVX2 location(22200 0) - pin(0 5) - pin(1 6) - pin(2 7) - pin(3 9) - pin(4 6) - pin(5 9) - ) - circuit(17 INVX1 location(7800 0) - pin(0 6) - pin(1 12) - pin(2 9) - pin(3 6) - pin(4 10) - pin(5 9) - ) - circuit(18 INVX1 location(9600 0) - pin(0 6) - pin(1 13) - pin(2 9) - pin(3 6) - pin(4 12) - pin(5 9) - ) - circuit(19 INVX1 location(11400 0) - pin(0 6) - pin(1 14) - pin(2 9) - pin(3 6) - pin(4 13) - pin(5 9) - ) - circuit(20 INVX1 location(13200 0) - pin(0 6) - pin(1 15) - pin(2 9) - pin(3 6) - pin(4 14) - pin(5 9) - ) - circuit(21 INVX1 location(15000 0) - pin(0 6) - pin(1 11) - pin(2 9) - pin(3 6) - pin(4 15) - pin(5 9) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX2 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX2 INVX2 match - xref( - net(5 4 match) - net(1 5 match) - net(3 2 match) - net(6 6 match) - net(2 1 match) - net(4 3 match) - pin(4 3 match) - pin(0 4 match) - pin(2 1 match) - pin(5 5 match) - pin(1 0 match) - pin(3 2 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(4 15 match) - net(2 7 match) - net(10 8 match) - net(12 9 match) - net(13 10 match) - net(14 11 match) - net(15 12 match) - net(11 13 match) - net(3 14 match) - net(8 4 match) - net(5 3 match) - net(7 5 match) - net(6 2 match) - net(9 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(17 4 match) - circuit(18 5 match) - circuit(19 6 match) - circuit(20 7 match) - circuit(21 8 match) - circuit(4 9 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 index 609357e5f..337303dd0 100644 --- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 @@ -484,34 +484,19 @@ layout( # Nets with their geometries net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (4040 2950) (610 300)) ) net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (5550 2950) (900 300)) ) net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (18150 2950) (900 300)) ) net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (19950 2950) (900 300)) ) net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) + rect(l11 (21750 2950) (900 300)) rect(l11 (-19530 590) (320 320)) rect(l11 (17820 -320) (320 320)) rect(l12 (-18400 -260) (200 200)) @@ -520,8 +505,6 @@ layout( rect(l13 (-17921 -201) (2 2)) rect(l13 (-221 -201) (400 400)) rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) ) net(6 name(VDD) rect(l3 (1100 4500) (1400 3500)) @@ -543,21 +526,7 @@ layout( rect(l11 (-750 -1450) (300 1400)) rect(l11 (-101 -351) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l2 (-23625 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l2 (-3600 -1500) (425 1500)) - rect(l9 (-19575 -450) (500 1500)) + rect(l9 (-24850 -1500) (500 1500)) rect(l9 (22900 -1500) (500 1500)) ) net(7 name(OUT) @@ -565,14 +534,9 @@ layout( rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) ) net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) + rect(l11 (2440 2940) (320 320)) rect(l12 (-260 -260) (200 200)) rect(l13 (-101 -101) (2 2)) rect(l13 (-201 -201) (400 400)) @@ -593,57 +557,26 @@ layout( rect(l11 (-750 -1450) (1200 800)) rect(l11 (-551 -401) (2 2)) rect(l11 (549 -401) (600 800)) - rect(l6 (-24300 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (950 -950) (425 950)) - rect(l6 (-3600 -950) (425 950)) - rect(l10 (-19575 -2210) (500 1500)) + rect(l10 (-24850 -800) (500 1500)) rect(l10 (22900 -1500) (500 1500)) ) net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (7350 2950) (900 300)) ) net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (16350 2950) (900 300)) ) net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (9150 2950) (900 300)) ) net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (10950 2950) (900 300)) ) net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (12750 2950) (900 300)) ) net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) + rect(l11 (14550 2950) (900 300)) ) # Outgoing pins and their connections to nets diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 deleted file mode 100644 index 909c14e3d..000000000 --- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 +++ /dev/null @@ -1,1162 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-225 -1300) (675 450)) - rect(l4 (0 -1100) (250 1950)) - rect(l4 (-1225 -1850) (300 300)) - rect(l4 (675 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-950 -2000) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (450 -5390) (250 1450)) - rect(l4 (-950 -1450) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(2 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-1640 -240) (300 1400)) - rect(l11 (-650 300) (2400 800)) - rect(l11 (-2050 -1100) (300 300)) - rect(l11 (1100 -300) (300 300)) - rect(l11 (-1101 399) (2 2)) - rect(l11 (799 -2101) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - ) - net(3 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(4 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (1220 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-1640 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-650 0) (300 1360)) - rect(l11 (-1101 -1761) (2 2)) - rect(l6 (724 859) (425 950)) - rect(l6 (-1800 -950) (425 950)) - ) - net(5 - rect(l3 (-100 4500) (2600 3500)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(IN)) - pin(2 name(VDD)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 5800) - param(L 0.25) - param(W 3) - param(AS 0.975) - param(AD 0.975) - param(PS 5.8) - param(PD 5.8) - terminal(S 2) - terminal(G 1) - terminal(D 3) - terminal(B 5) - ) - device(3 D$NMOS - device(D$NMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 2135) - param(L 0.25) - param(W 1.9) - param(AS 0.6175) - param(AD 0.6175) - param(PS 4.15) - param(PD 4.15) - terminal(S 4) - terminal(G 1) - terminal(D 3) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((600 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-2550 1800) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 name(VDD) - rect(l3 (1100 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-22341 859) (2 2)) - rect(l11 (-1751 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23625 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l2 (-3600 -1500) (425 1500)) - rect(l9 (-19575 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(7 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(9 name(VSS) - rect(l8 (1710 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-22341 -391) (2 2)) - rect(l11 (-1301 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-24300 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (4550 -950) (425 950)) - rect(l6 (-1800 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-19575 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(5 name(FB)) - pin(6 name(VDD)) - pin(7 name(OUT)) - pin(8 name(ENABLE)) - pin(9 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 6) - pin(1 1) - pin(2 9) - pin(3 6) - pin(4 5) - pin(5 8) - pin(6 9) - ) - circuit(2 INVX1 location(4200 0) - pin(0 6) - pin(1 2) - pin(2 9) - pin(3 6) - pin(4 1) - pin(5 9) - ) - circuit(3 INVX1 location(6000 0) - pin(0 6) - pin(1 10) - pin(2 9) - pin(3 6) - pin(4 2) - pin(5 9) - ) - circuit(4 INVX1 location(16800 0) - pin(0 6) - pin(1 3) - pin(2 9) - pin(3 6) - pin(4 11) - pin(5 9) - ) - circuit(5 INVX1 location(18600 0) - pin(0 6) - pin(1 4) - pin(2 9) - pin(3 6) - pin(4 3) - pin(5 9) - ) - circuit(6 INVX1 location(20400 0) - pin(0 6) - pin(1 5) - pin(2 9) - pin(3 6) - pin(4 4) - pin(5 9) - ) - circuit(7 INVX2 location(22200 0) - pin(0 5) - pin(1 6) - pin(2 7) - pin(3 9) - pin(4 6) - pin(5 9) - ) - circuit(13 INVX1 location(7800 0) - pin(0 6) - pin(1 12) - pin(2 9) - pin(3 6) - pin(4 10) - pin(5 9) - ) - circuit(14 INVX1 location(9600 0) - pin(0 6) - pin(1 13) - pin(2 9) - pin(3 6) - pin(4 12) - pin(5 9) - ) - circuit(15 INVX1 location(11400 0) - pin(0 6) - pin(1 14) - pin(2 9) - pin(3 6) - pin(4 13) - pin(5 9) - ) - circuit(16 INVX1 location(13200 0) - pin(0 6) - pin(1 15) - pin(2 9) - pin(3 6) - pin(4 14) - pin(5 9) - ) - circuit(17 INVX1 location(15000 0) - pin(0 6) - pin(1 11) - pin(2 9) - pin(3 6) - pin(4 15) - pin(5 9) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX2 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX2 INVX2 match - xref( - net(5 4 match) - net(1 5 match) - net(3 2 match) - net(6 6 match) - net(2 1 match) - net(4 3 match) - pin(4 3 match) - pin(0 4 match) - pin(2 1 match) - pin(5 5 match) - pin(1 0 match) - pin(3 2 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(4 15 match) - net(2 7 match) - net(10 8 match) - net(12 9 match) - net(13 10 match) - net(14 11 match) - net(15 12 match) - net(11 13 match) - net(3 14 match) - net(8 4 match) - net(5 3 match) - net(7 5 match) - net(6 2 match) - net(9 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(13 4 match) - circuit(14 5 match) - circuit(15 6 match) - circuit(16 7 match) - circuit(17 8 match) - circuit(4 9 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 deleted file mode 100644 index 60f468222..000000000 --- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 +++ /dev/null @@ -1,1162 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l2 (-276 -2151) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-141 -501) (2 2)) - rect(l11 (-1751 1099) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1151 -401) (2 2)) - rect(l6 (-951 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-71 -91) (2 2)) - rect(l11 (-171 -151) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (299 399) (2 2)) - rect(l2 (-651 -2151) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-851 -401) (2 2)) - rect(l6 (-651 859) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-225 -1300) (675 450)) - rect(l4 (0 -1100) (250 1950)) - rect(l4 (-1225 -1850) (300 300)) - rect(l4 (675 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-950 -2000) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (450 -5390) (250 1450)) - rect(l4 (-950 -1450) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-91 -91) (2 2)) - rect(l11 (-151 -151) (300 300)) - ) - net(2 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-1640 -240) (300 1400)) - rect(l11 (-650 300) (2400 800)) - rect(l11 (-2050 -1100) (300 300)) - rect(l11 (1100 -300) (300 300)) - rect(l11 (-1101 399) (2 2)) - rect(l11 (799 -2101) (300 1400)) - rect(l2 (-375 -1450) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - ) - net(3 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-151 -2501) (2 2)) - rect(l2 (-226 1049) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(4 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (1220 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-1640 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-650 0) (300 1360)) - rect(l11 (-1101 -1761) (2 2)) - rect(l6 (724 859) (425 950)) - rect(l6 (-1800 -950) (425 950)) - ) - net(5 - rect(l3 (-100 4500) (2600 3500)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(IN)) - pin(2 name(VDD)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 5800) - param(L 0.25) - param(W 3) - param(AS 0.975) - param(AD 0.975) - param(PS 5.8) - param(PD 5.8) - terminal(S 2) - terminal(G 1) - terminal(D 3) - terminal(B 5) - ) - device(3 D$NMOS - device(D$NMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 2135) - param(L 0.25) - param(W 1.9) - param(AS 0.6175) - param(AD 0.6175) - param(PS 4.15) - param(PD 4.15) - terminal(S 4) - terminal(G 1) - terminal(D 3) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((600 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l8 (4710 3010) (180 180)) - rect(l11 (-850 -240) (610 300)) - rect(l2 (-1175 1800) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l6 (950 -4890) (425 950)) - ) - net(2 - rect(l8 (6510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 - rect(l8 (19110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(4 - rect(l8 (20910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(5 name(FB) - rect(l8 (22710 3010) (180 180)) - rect(l8 (-19700 720) (180 180)) - rect(l11 (18380 -1140) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17921 -201) (2 2)) - rect(l13 (-221 -201) (400 400)) - rect(l13 (17740 -400) (400 400)) - rect(l2 (-245 850) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(6 name(VDD) - rect(l3 (1100 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-22341 859) (2 2)) - rect(l11 (-1751 -451) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-101 -351) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l2 (-23625 -2550) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l2 (1275 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l2 (3175 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (1375 -1500) (425 1500)) - rect(l2 (4550 -1500) (425 1500)) - rect(l2 (-1800 -1500) (425 1500)) - rect(l2 (-2225 -1500) (425 1500)) - rect(l9 (-19575 -450) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(7 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - rect(l2 (-625 850) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(8 name(ENABLE) - rect(l8 (2510 3010) (180 180)) - rect(l11 (-250 -250) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-101 -101) (2 2)) - rect(l13 (-201 -201) (400 400)) - ) - net(9 name(VSS) - rect(l8 (1710 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-22341 -391) (2 2)) - rect(l11 (-1301 -401) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (-1251 -401) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-551 -401) (2 2)) - rect(l11 (549 -401) (600 800)) - rect(l6 (-24300 460) (425 950)) - rect(l6 (1975 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l6 (3175 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (1375 -950) (425 950)) - rect(l6 (4550 -950) (425 950)) - rect(l6 (-1800 -950) (425 950)) - rect(l6 (-2225 -950) (425 950)) - rect(l10 (-19575 -2210) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - net(10 - rect(l8 (8310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(11 - rect(l8 (17310 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(12 - rect(l8 (10110 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(13 - rect(l8 (11910 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(14 - rect(l8 (13710 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(15 - rect(l8 (15510 3010) (180 180)) - rect(l11 (-1140 -240) (900 300)) - rect(l2 (-1275 1800) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(5 name(FB)) - pin(6 name(VDD)) - pin(7 name(OUT)) - pin(8 name(ENABLE)) - pin(9 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 6) - pin(1 1) - pin(2 9) - pin(3 6) - pin(4 5) - pin(5 8) - pin(6 9) - ) - circuit(2 INVX1 location(4200 0) - pin(0 6) - pin(1 2) - pin(2 9) - pin(3 6) - pin(4 1) - pin(5 9) - ) - circuit(3 INVX1 location(6000 0) - pin(0 6) - pin(1 10) - pin(2 9) - pin(3 6) - pin(4 2) - pin(5 9) - ) - circuit(4 INVX1 location(16800 0) - pin(0 6) - pin(1 3) - pin(2 9) - pin(3 6) - pin(4 11) - pin(5 9) - ) - circuit(5 INVX1 location(18600 0) - pin(0 6) - pin(1 4) - pin(2 9) - pin(3 6) - pin(4 3) - pin(5 9) - ) - circuit(6 INVX1 location(20400 0) - pin(0 6) - pin(1 5) - pin(2 9) - pin(3 6) - pin(4 4) - pin(5 9) - ) - circuit(7 INVX2 location(22200 0) - pin(0 5) - pin(1 6) - pin(2 7) - pin(3 9) - pin(4 6) - pin(5 9) - ) - circuit(13 INVX1 location(7800 0) - pin(0 6) - pin(1 12) - pin(2 9) - pin(3 6) - pin(4 10) - pin(5 9) - ) - circuit(14 INVX1 location(9600 0) - pin(0 6) - pin(1 13) - pin(2 9) - pin(3 6) - pin(4 12) - pin(5 9) - ) - circuit(15 INVX1 location(11400 0) - pin(0 6) - pin(1 14) - pin(2 9) - pin(3 6) - pin(4 13) - pin(5 9) - ) - circuit(16 INVX1 location(13200 0) - pin(0 6) - pin(1 15) - pin(2 9) - pin(3 6) - pin(4 14) - pin(5 9) - ) - circuit(17 INVX1 location(15000 0) - pin(0 6) - pin(1 11) - pin(2 9) - pin(3 6) - pin(4 15) - pin(5 9) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX2 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX2 INVX2 match - xref( - net(5 4 match) - net(1 5 match) - net(3 2 match) - net(6 6 match) - net(2 1 match) - net(4 3 match) - pin(4 3 match) - pin(0 4 match) - pin(2 1 match) - pin(5 5 match) - pin(1 0 match) - pin(3 2 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(4 15 match) - net(2 7 match) - net(10 8 match) - net(12 9 match) - net(13 10 match) - net(14 11 match) - net(15 12 match) - net(11 13 match) - net(3 14 match) - net(8 4 match) - net(5 3 match) - net(7 5 match) - net(6 2 match) - net(9 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(13 4 match) - circuit(14 5 match) - circuit(15 6 match) - circuit(16 7 match) - circuit(17 8 match) - circuit(4 9 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) - circuit(1 1 match) - ) - ) -) From a05345945d5c80e093f914a6383689bcbaa4203c Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 09:46:40 +0100 Subject: [PATCH 15/21] Updated test data --- testdata/python/dbLayoutToNetlist.py | 28 ++++++++++++++-------------- testdata/ruby/dbLayoutToNetlist.rb | 28 ++++++++++++++-------------- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/testdata/python/dbLayoutToNetlist.py b/testdata/python/dbLayoutToNetlist.py index f5faace5c..11e395309 100644 --- a/testdata/python/dbLayoutToNetlist.py +++ b/testdata/python/dbLayoutToNetlist.py @@ -191,8 +191,8 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5); end; circuit RINGO (); subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD); - subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I37,$4=VSS,$5=VDD); - subcircuit INV2 $3 (IN=$I37,$2=$I39,OUT=$I1,$4=VSS,$5=VDD); + subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD); + subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD); subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD); subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD); subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD); @@ -272,8 +272,8 @@ end; self.assertEqual(str(l2n.netlist()), """circuit RINGO (); subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD); - subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I37,$4=VSS,$5=VDD); - subcircuit INV2 $3 (IN=$I37,$2=$I39,OUT=$I1,$4=VSS,$5=VDD); + subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD); + subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD); subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD); subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD); subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD); @@ -387,14 +387,14 @@ end; self.assertEqual(str(l2n.netlist()), """circuit RINGO (); subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD); - subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I21,$7=VDD); - subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I21,$6=$I5,$7=VDD); + subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD); + subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD); subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD); subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD); end; -circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1); - subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I6,VSS=$I4,VDD=$I5,BULK=BULK); - subcircuit INV2 $2 ($1=$I1,IN=$I6,$3=$I8,OUT=$I2,VSS=$I4,VDD=$I5,BULK=BULK); +circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1); + subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK); + subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK); end; circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK); device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5); @@ -416,14 +416,14 @@ end; self.assertEqual(str(l2n.netlist()), """circuit RINGO (FB=FB,OSC=OSC,VDD=VDD,VSS=VSS); subcircuit INV2PAIR $1 (BULK=VSS,$2=FB,$3=VDD,$4=VSS,$5=$I7,$6=OSC,$7=VDD); - subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I21,$7=VDD); - subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I21,$6=$I5,$7=VDD); + subcircuit INV2PAIR $2 (BULK=VSS,$2=$I22,$3=VDD,$4=VSS,$5=FB,$6=$I13,$7=VDD); + subcircuit INV2PAIR $3 (BULK=VSS,$2=$I23,$3=VDD,$4=VSS,$5=$I13,$6=$I5,$7=VDD); subcircuit INV2PAIR $4 (BULK=VSS,$2=$I24,$3=VDD,$4=VSS,$5=$I5,$6=$I6,$7=VDD); subcircuit INV2PAIR $5 (BULK=VSS,$2=$I25,$3=VDD,$4=VSS,$5=$I6,$6=$I7,$7=VDD); end; -circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I5,$4=$I4,$5=$I3,$6=$I2,$7=$I1); - subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I6,VSS=$I4,VDD=$I5,BULK=BULK); - subcircuit INV2 $2 ($1=$I1,IN=$I6,$3=$I8,OUT=$I2,VSS=$I4,VDD=$I5,BULK=BULK); +circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1); + subcircuit INV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK); + subcircuit INV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK); end; circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK); device PMOS $1 (S=$3,G=IN,D=VDD,B=$1) (L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5); diff --git a/testdata/ruby/dbLayoutToNetlist.rb b/testdata/ruby/dbLayoutToNetlist.rb index aed45f75b..727ab064a 100644 --- a/testdata/ruby/dbLayoutToNetlist.rb +++ b/testdata/ruby/dbLayoutToNetlist.rb @@ -227,8 +227,8 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5); end; circuit RINGO (); subcircuit INV2 $1 (IN=$I8,$2=FB,OUT=OSC,$4=VSS,$5=VDD); - subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I37,$4=VSS,$5=VDD); - subcircuit INV2 $3 (IN=$I37,$2=$I39,OUT=$I1,$4=VSS,$5=VDD); + subcircuit INV2 $2 (IN=FB,$2=$I38,OUT=$I19,$4=VSS,$5=VDD); + subcircuit INV2 $3 (IN=$I19,$2=$I39,OUT=$I1,$4=VSS,$5=VDD); subcircuit INV2 $4 (IN=$I1,$2=$I40,OUT=$I2,$4=VSS,$5=VDD); subcircuit INV2 $5 (IN=$I2,$2=$I41,OUT=$I3,$4=VSS,$5=VDD); subcircuit INV2 $6 (IN=$I3,$2=$I42,OUT=$I4,$4=VSS,$5=VDD); @@ -309,8 +309,8 @@ END assert_equal(l2n.netlist.to_s, < Date: Sun, 15 Dec 2019 10:17:10 +0100 Subject: [PATCH 16/21] Updated test data for windows. --- testdata/algo/lvs_test1_au.lvsdb.2 | 646 ++++++++++ testdata/algo/lvs_test2_au.lvsdb.2 | 682 ++++++++++ testdata/lvs/ringo_device_subcircuits.lvsdb.2 | 908 ++++++++++++++ testdata/lvs/ringo_layout_var.lvsdb.2 | 1013 +++++++++++++++ testdata/lvs/ringo_simple.lvsdb.2 | 908 ++++++++++++++ .../lvs/ringo_simple_device_scaling.lvsdb.2 | 908 ++++++++++++++ testdata/lvs/ringo_simple_dmos.lvsdb.2 | 912 ++++++++++++++ .../lvs/ringo_simple_dummy_device.lvsdb.2 | 965 +++++++++++++++ .../ringo_simple_implicit_connections.lvsdb.2 | 927 ++++++++++++++ testdata/lvs/ringo_simple_io.lvsdb.2 | 828 +++++++++++++ testdata/lvs/ringo_simple_io2.lvsdb.2 | 908 ++++++++++++++ ...simple_net_and_circuit_equivalence.lvsdb.2 | 907 ++++++++++++++ .../lvs/ringo_simple_pin_swapping.lvsdb.2 | 908 ++++++++++++++ .../ringo_simple_same_device_classes.lvsdb.2 | 910 ++++++++++++++ .../lvs/ringo_simple_simplification.lvsdb.2 | 1095 +++++++++++++++++ ...o_simple_simplification_with_align.lvsdb.2 | 1095 +++++++++++++++++ 16 files changed, 14520 insertions(+) create mode 100644 testdata/algo/lvs_test1_au.lvsdb.2 create mode 100644 testdata/algo/lvs_test2_au.lvsdb.2 create mode 100644 testdata/lvs/ringo_device_subcircuits.lvsdb.2 create mode 100644 testdata/lvs/ringo_layout_var.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_device_scaling.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_dmos.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_dummy_device.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_io.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_io2.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_simplification.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 diff --git a/testdata/algo/lvs_test1_au.lvsdb.2 b/testdata/algo/lvs_test1_au.lvsdb.2 new file mode 100644 index 000000000..42c2187d5 --- /dev/null +++ b/testdata/algo/lvs_test1_au.lvsdb.2 @@ -0,0 +1,646 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(bulk '1/0') + layer(nwell '1/0') + layer(poly '3/0') + layer(poly_lbl '3/1') + layer(diff_cont '4/0') + layer(poly_cont '5/0') + layer(metal1 '6/0') + layer(metal1_lbl '6/1') + layer(via1 '7/0') + layer(metal2 '8/0') + layer(metal2_lbl '8/1') + layer(ntie) + layer(psd) + layer(ptie) + layer(nsd) + + # Mask layer connectivity + connect(nwell nwell ntie) + connect(poly poly poly_lbl poly_cont) + connect(poly_lbl poly) + connect(diff_cont diff_cont metal1 ntie psd ptie nsd) + connect(poly_cont poly poly_cont metal1) + connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) + connect(metal1_lbl metal1) + connect(via1 metal1 via1 metal2) + connect(metal2 via1 metal2 metal2_lbl) + connect(metal2_lbl metal2) + connect(ntie nwell diff_cont ntie) + connect(psd diff_cont psd) + connect(ptie diff_cont ptie) + connect(nsd diff_cont nsd) + + # Global nets and connectivity + global(bulk BULK) + global(ptie BULK) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(psd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (550 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(psd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (525 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(nsd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (550 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(nsd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (525 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Circuit boundary + rect((-1700 -2440) (3100 7820)) + + # Nets with their geometries + net(1 + rect(nwell (-1400 1800) (2800 3580)) + rect(diff_cont (-1510 -650) (220 220)) + rect(ntie (-510 -450) (800 680)) + ) + net(2 name(IN) + rect(poly (-525 -250) (250 2500)) + rect(poly (-1425 -630) (2100 360)) + rect(poly (-125 -2230) (250 2500)) + rect(poly (-1050 -3850) (250 2400)) + rect(poly (550 1200) (250 2400)) + rect(poly (-250 -6000) (250 2400)) + rect(poly (-1050 1200) (250 2400)) + rect(poly_lbl (-526 -2601) (2 2)) + rect(poly_cont (-831 -111) (220 220)) + ) + net(3 name(OUT) + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (1310 -3710) (360 2220)) + rect(metal1 (-1900 -800) (2220 360)) + rect(metal1 (-2280 -2400) (360 2840)) + rect(metal1 (-360 -3600) (360 1560)) + rect(metal1 (1240 2040) (360 1560)) + rect(metal1 (-360 -5160) (360 1560)) + rect(metal1 (-1960 2040) (360 1560)) + rect(metal1_lbl (1419 -2181) (2 2)) + rect(psd (-1851 524) (525 1750)) + rect(psd (1050 -1750) (525 1750)) + rect(nsd (-2100 -5350) (525 1750)) + rect(nsd (1050 -1750) (525 1750)) + ) + net(4 name(VSS) + rect(diff_cont (-110 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 980) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-290 -290) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -705) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 -1450) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -775) (2800 1700)) + rect(metal2_lbl (-161 -541) (2 2)) + rect(nsd (-1516 -1186) (550 1750)) + ) + net(5 name(VDD) + rect(diff_cont (-110 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -1420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (-290 -1490) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -1505) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -1575) (2800 1700)) + rect(metal2_lbl (-151 -1251) (2 2)) + rect(psd (-1526 -476) (550 1750)) + ) + net(6 name(BULK) + rect(diff_cont (-110 -2160) (220 220)) + rect(ptie (-510 -450) (800 680)) + ) + + # Outgoing pins and their connections to nets + pin(1) + pin(2 name(IN)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5 name(VDD)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 3200) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(3 D$NMOS + device(D$NMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 -400) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Circuit boundary + rect((0 -1640) (5740 7820)) + + # Nets with their geometries + net(1 name(BULK)) + net(2) + net(3) + net(4) + net(5) + net(6) + net(7) + + # Outgoing pins and their connections to nets + pin(1 name(BULK)) + pin(2) + pin(3) + pin(4) + pin(5) + pin(6) + pin(7) + + # Subcircuits and their connections + circuit(1 INV2 location(1700 800) + pin(0 7) + pin(1 5) + pin(2 4) + pin(3 3) + pin(4 2) + pin(5 1) + ) + circuit(2 INV2 location(4340 800) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((-1720 -2440) (26880 7820)) + + # Nets with their geometries + net(1 name(FB) + rect(metal1 (-1700 1620) (360 360)) + rect(via1 (-305 -305) (250 250)) + rect(via1 (23190 -250) (250 250)) + rect(metal2 (-23765 -325) (23840 400)) + rect(metal2_lbl (-22121 -201) (2 2)) + ) + net(2 name(OSC) + rect(via1 (24435 1675) (250 250)) + rect(metal2 (-325 -325) (400 400)) + rect(metal2_lbl (-201 -201) (2 2)) + ) + net(3 name(VDD) + rect(metal1 (-180 3900) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 -2221) (2 2)) + ) + net(4 name(VSS) + rect(metal1 (-180 -2220) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 1099) (2 2)) + ) + net(5) + net(6) + net(7) + net(8) + net(9) + net(10) + net(11) + net(12) + + # Outgoing pins and their connections to nets + pin(1 name(FB)) + pin(2 name(OSC)) + pin(3 name(VDD)) + pin(4 name(VSS)) + + # Subcircuits and their connections + circuit(1 INV2PAIR location(19420 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 10) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR location(-1700 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 8) + pin(4 1) + pin(5 9) + pin(6 3) + ) + circuit(3 INV2PAIR location(3580 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 7) + pin(4 9) + pin(5 12) + pin(6 3) + ) + circuit(4 INV2PAIR location(8860 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 6) + pin(4 12) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR location(14140 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 5) + pin(4 11) + pin(5 10) + pin(6 3) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(2 NMOS + name($3) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($1) + pin(0 7) + pin(1 5) + pin(2 4) + pin(3 3) + pin(4 2) + pin(5 1) + ) + circuit(2 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('6')) + net(6 name('100')) + net(7 name('5')) + net(8 name('101')) + net(9 name('8')) + net(10 name('102')) + net(11 name('7')) + net(12 name('103')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + + # Subcircuits and their connections + circuit(1 INV2PAIR name($1) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 5) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR name($2) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 6) + pin(4 1) + pin(5 7) + pin(6 3) + ) + circuit(3 INV2PAIR name($3) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 8) + pin(4 7) + pin(5 9) + pin(6 3) + ) + circuit(4 INV2PAIR name($4) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 10) + pin(4 9) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR name($5) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 12) + pin(4 11) + pin(5 5) + pin(6 3) + ) + + ) +) + +# Cross reference +xref( + circuit(INV2 INV2 match + xref( + net(1 1 match) + net(6 6 match) + net(2 2 match) + net(3 3 match) + net(5 5 match) + net(4 4 match) + pin(0 0 match) + pin(5 5 match) + pin(1 1 match) + pin(2 2 match) + pin(4 4 match) + pin(3 3 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(INV2PAIR INV2PAIR match + xref( + net(2 2 match) + net(3 3 match) + net(4 4 match) + net(5 5 match) + net(6 6 match) + net(7 7 match) + net(1 1 match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) + pin(4 4 match) + pin(5 5 match) + pin(6 6 match) + pin(0 0 match) + circuit(1 1 match) + circuit(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(8 6 match) + net(7 8 match) + net(6 10 match) + net(5 12 match) + net(9 7 match) + net(10 5 match) + net(11 11 match) + net(12 9 match) + net(1 1 match) + net(2 2 match) + net(3 3 match) + net(4 4 match) + pin(0 0 match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) + circuit(1 1 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + ) + ) +) diff --git a/testdata/algo/lvs_test2_au.lvsdb.2 b/testdata/algo/lvs_test2_au.lvsdb.2 new file mode 100644 index 000000000..3719b24c1 --- /dev/null +++ b/testdata/algo/lvs_test2_au.lvsdb.2 @@ -0,0 +1,682 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(bulk '1/0') + layer(nwell '1/0') + layer(poly '3/0') + layer(poly_lbl '3/1') + layer(diff_cont '4/0') + layer(poly_cont '5/0') + layer(metal1 '6/0') + layer(metal1_lbl '6/1') + layer(via1 '7/0') + layer(metal2 '8/0') + layer(metal2_lbl '8/1') + layer(ntie) + layer(psd) + layer(ptie) + layer(nsd) + + # Mask layer connectivity + connect(nwell nwell ntie) + connect(poly poly poly_lbl poly_cont) + connect(poly_lbl poly) + connect(diff_cont diff_cont metal1 ntie psd ptie nsd) + connect(poly_cont poly poly_cont metal1) + connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) + connect(metal1_lbl metal1) + connect(via1 metal1 via1 metal2) + connect(metal2 via1 metal2 metal2_lbl) + connect(metal2_lbl metal2) + connect(ntie nwell diff_cont ntie) + connect(psd diff_cont psd) + connect(ptie diff_cont ptie) + connect(nsd diff_cont nsd) + + # Global nets and connectivity + global(bulk BULK) + global(ptie BULK) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(psd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (550 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(psd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (525 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(nsd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (550 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(nsd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (525 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Circuit boundary + rect((-1700 -2440) (3100 7820)) + + # Nets with their geometries + net(1 + rect(nwell (-1400 1800) (2800 3580)) + rect(diff_cont (-1510 -650) (220 220)) + rect(ntie (-510 -450) (800 680)) + ) + net(2 name(IN) + rect(poly (-525 -250) (250 2500)) + rect(poly (-1425 -630) (2100 360)) + rect(poly (-125 -2230) (250 2500)) + rect(poly (-1050 -3850) (250 2400)) + rect(poly (550 1200) (250 2400)) + rect(poly (-250 -6000) (250 2400)) + rect(poly (-1050 1200) (250 2400)) + rect(poly_lbl (-526 -2601) (2 2)) + rect(poly_cont (-831 -111) (220 220)) + ) + net(3 name(OUT) + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (1310 -3710) (360 2220)) + rect(metal1 (-1900 -800) (2220 360)) + rect(metal1 (-2280 -2400) (360 2840)) + rect(metal1 (-360 -3600) (360 1560)) + rect(metal1 (1240 2040) (360 1560)) + rect(metal1 (-360 -5160) (360 1560)) + rect(metal1 (-1960 2040) (360 1560)) + rect(metal1_lbl (1419 -2181) (2 2)) + rect(psd (-1851 524) (525 1750)) + rect(psd (1050 -1750) (525 1750)) + rect(nsd (-2100 -5350) (525 1750)) + rect(nsd (1050 -1750) (525 1750)) + ) + net(4 name(VSS) + rect(diff_cont (-110 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 980) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-290 -290) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -705) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 -1450) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -775) (2800 1700)) + rect(metal2_lbl (-161 -541) (2 2)) + rect(nsd (-1516 -1186) (550 1750)) + ) + net(5 name(VDD) + rect(diff_cont (-110 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -1420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (-290 -1490) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -1505) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -1575) (2800 1700)) + rect(metal2_lbl (-151 -1251) (2 2)) + rect(psd (-1526 -476) (550 1750)) + ) + net(6 name(BULK) + rect(diff_cont (-110 -2160) (220 220)) + rect(ptie (-510 -450) (800 680)) + ) + + # Outgoing pins and their connections to nets + pin(1) + pin(2 name(IN)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5 name(VDD)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 3200) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(3 D$NMOS + device(D$NMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 -400) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Circuit boundary + rect((0 -1640) (5740 7820)) + + # Nets with their geometries + net(1 name(BULK)) + net(2) + net(3) + net(4) + net(5) + net(6) + net(7) + + # Outgoing pins and their connections to nets + pin(1 name(BULK)) + pin(2) + pin(3) + pin(4) + pin(5) + pin(6) + pin(7) + + # Subcircuits and their connections + circuit(1 INV2 location(1700 800) + pin(0 7) + pin(1 5) + pin(2 4) + pin(3 3) + pin(4 2) + pin(5 1) + ) + circuit(2 INV2 location(4340 800) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((-1720 -2440) (26880 7820)) + + # Nets with their geometries + net(1 name(FB) + rect(metal1 (-1700 1620) (360 360)) + rect(via1 (-305 -305) (250 250)) + rect(via1 (23190 -250) (250 250)) + rect(metal2 (-23765 -325) (23840 400)) + rect(metal2_lbl (-22121 -201) (2 2)) + ) + net(2 name(OSC) + rect(via1 (24435 1675) (250 250)) + rect(metal2 (-325 -325) (400 400)) + rect(metal2_lbl (-201 -201) (2 2)) + ) + net(3 name(VDD) + rect(metal1 (-180 3900) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 -2221) (2 2)) + ) + net(4 name(VSS) + rect(metal1 (-180 -2220) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 1099) (2 2)) + ) + net(5) + net(6) + net(7) + net(8) + net(9) + net(10) + net(11) + net(12) + + # Outgoing pins and their connections to nets + pin(1 name(FB)) + pin(2 name(OSC)) + pin(3 name(VDD)) + pin(4 name(VSS)) + + # Subcircuits and their connections + circuit(1 INV2PAIR location(19420 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 10) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR location(-1700 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 8) + pin(4 1) + pin(5 9) + pin(6 3) + ) + circuit(3 INV2PAIR location(3580 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 7) + pin(4 9) + pin(5 12) + pin(6 3) + ) + circuit(4 INV2PAIR location(8860 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 6) + pin(4 12) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR location(14140 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 5) + pin(4 11) + pin(5 10) + pin(6 3) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(2 NMOS + name($3) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('6')) + net(6 name('5')) + net(7 name('101')) + net(8 name('8')) + net(9 name('102')) + net(10 name('7')) + net(11 name('103')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + + # Subcircuits and their connections + circuit(1 INV2PAIR name($1) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 5) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR name($2) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 1) + pin(5 6) + pin(6 3) + ) + circuit(3 INV2PAIR name($3) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 7) + pin(4 6) + pin(5 8) + pin(6 3) + ) + circuit(4 INV2PAIR name($4) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 9) + pin(4 8) + pin(5 10) + pin(6 3) + ) + circuit(5 INV2PAIR name($5) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 11) + pin(4 10) + pin(5 5) + pin(6 3) + ) + + ) + circuit(INV2PAIRX + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(() INV2PAIRX mismatch + xref( + ) + ) + circuit(INV2 INV2 match + xref( + net(1 1 match) + net(6 6 match) + net(2 2 match) + net(3 3 match) + net(5 5 match) + net(4 4 match) + pin(0 0 match) + pin(5 5 match) + pin(1 1 match) + pin(2 2 match) + pin(4 4 match) + pin(3 3 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(INV2PAIR INV2PAIR nomatch + xref( + net(2 2 mismatch) + net(3 3 mismatch) + net(5 4 match) + net(4 5 mismatch) + net(6 6 match) + net(7 7 mismatch) + net(1 1 mismatch) + pin(1 1 match) + pin(2 2 match) + pin(4 3 match) + pin(3 4 match) + pin(5 5 match) + pin(6 6 match) + pin(0 0 match) + circuit(2 () mismatch) + circuit(1 1 mismatch) + ) + ) + circuit(RINGO RINGO nomatch + xref( + net(() 7 mismatch) + net(() 9 mismatch) + net(() 11 mismatch) + net(() 6 mismatch) + net(() 8 mismatch) + net(5 () mismatch) + net(6 () mismatch) + net(7 () mismatch) + net(9 () mismatch) + net(11 () mismatch) + net(12 () mismatch) + net(10 1 mismatch) + net(8 10 mismatch) + net(1 5 mismatch) + net(2 2 match) + net(3 3 match) + net(4 4 match) + pin(() 0 match) + pin(0 () match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) + circuit(() 2 mismatch) + circuit(() 3 mismatch) + circuit(() 4 mismatch) + circuit(() 5 mismatch) + circuit(2 () mismatch) + circuit(3 () mismatch) + circuit(4 () mismatch) + circuit(5 () mismatch) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_device_subcircuits.lvsdb.2 b/testdata/lvs/ringo_device_subcircuits.lvsdb.2 new file mode 100644 index 000000000..30f6382ed --- /dev/null +++ b/testdata/lvs/ringo_device_subcircuits.lvsdb.2 @@ -0,0 +1,908 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(XPMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 XPMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 XPMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 XPMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_layout_var.lvsdb.2 b/testdata/lvs/ringo_layout_var.lvsdb.2 new file mode 100644 index 000000000..d82b5247a --- /dev/null +++ b/testdata/lvs/ringo_layout_var.lvsdb.2 @@ -0,0 +1,1013 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX1B + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1B location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1B location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1B location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX1B INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(3 3 match) + circuit(5 5 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(2 2 match) + circuit(4 4 match) + circuit(6 6 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple.lvsdb.2 b/testdata/lvs/ringo_simple.lvsdb.2 new file mode 100644 index 000000000..b585c4ca4 --- /dev/null +++ b/testdata/lvs/ringo_simple.lvsdb.2 @@ -0,0 +1,908 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 new file mode 100644 index 000000000..c9d7da964 --- /dev/null +++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 @@ -0,0 +1,908 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.5) + param(W 3) + param(AS 2.55) + param(AD 1.35) + param(PS 7.7) + param(PD 3.9) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.5) + param(W 3) + param(AS 1.35) + param(AD 2.55) + param(PS 3.9) + param(PD 7.7) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.5) + param(W 1.9) + param(AS 1.615) + param(AD 0.855) + param(PS 5.5) + param(PD 2.8) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.5) + param(W 1.9) + param(AS 0.855) + param(AD 1.615) + param(PS 2.8) + param(PD 5.5) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.5) + param(W 3) + param(AS 2.55) + param(AD 2.55) + param(PS 7.7) + param(PD 7.7) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.5) + param(W 1.9) + param(AS 1.615) + param(AD 1.615) + param(PS 5.5) + param(PD 5.5) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.5) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.5) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.2 b/testdata/lvs/ringo_simple_dmos.lvsdb.2 new file mode 100644 index 000000000..45fc263a5 --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos.lvsdb.2 @@ -0,0 +1,912 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l4 '1/0') + layer(l5 '5/0') + layer(l10 '8/0') + layer(l13 '9/0') + layer(l14 '10/0') + layer(l15 '11/0') + layer(l9) + layer(l3) + layer(l1) + layer(l11) + layer(l8) + layer(l6) + layer(l12) + + # Mask layer connectivity + connect(l4 l4 l11) + connect(l5 l5 l10) + connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12) + connect(l13 l10 l13 l14) + connect(l14 l13 l14 l15) + connect(l15 l14 l15) + connect(l9 l9) + connect(l3 l10 l3) + connect(l1 l10 l1) + connect(l11 l4 l10 l11) + connect(l8 l10 l8) + connect(l6 l10 l6) + connect(l12 l10 l12) + + # Global nets and connectivity + global(l9 SUBSTRATE) + global(l12 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l3 (125 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (-550 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l3 (-575 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l3 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l8 (125 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (-550 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l8 (-575 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -790) (300 1700)) + rect(l13 (-1350 0) (2400 800)) + rect(l13 (-1151 -401) (2 2)) + rect(l3 (-251 -2151) (425 1500)) + rect(l3 (-450 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1810 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-1580 3760) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (1220 920) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l13 (-110 1390) (300 1400)) + polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l13 (-141 -501) (2 2)) + rect(l13 (-1751 1099) (300 1400)) + rect(l13 (1100 -1700) (300 300)) + rect(l13 (-300 0) (300 1400)) + rect(l1 (-1750 -1450) (425 1500)) + rect(l1 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (2400 800)) + rect(l13 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l8 (1000 1660) (425 950)) + rect(l8 (-450 -950) (425 950)) + ) + net(5 + rect(l4 (-100 4500) (2600 3500)) + ) + net(6 name(B) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-285 1050) (180 180)) + rect(l13 (-71 -91) (2 2)) + rect(l13 (-171 -151) (300 300)) + ) + net(7 name(A) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-265 150) (180 180)) + rect(l13 (-91 -91) (2 2)) + rect(l13 (-151 -151) (300 300)) + ) + net(8 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(5) + pin(6 name(B)) + pin(7 name(A)) + pin(8 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 7) + terminal(D 2) + terminal(B 5) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 5) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 4) + terminal(G 7) + terminal(D 3) + terminal(B 8) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 4) + terminal(G 6) + terminal(D 2) + terminal(B 8) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (410 6260) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -240) (300 1400)) + rect(l13 (-650 300) (1800 800)) + rect(l13 (-1450 -1100) (300 300)) + rect(l13 (299 399) (2 2)) + rect(l3 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -4120) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -790) (300 4790)) + rect(l13 (-151 -2501) (2 2)) + rect(l1 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (1800 800)) + rect(l13 (-851 -401) (2 2)) + rect(l8 (-651 859) (425 950)) + ) + net(4 + rect(l4 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-465 150) (180 180)) + rect(l13 (-91 -91) (2 2)) + rect(l13 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l13 (4040 2950) (610 300)) + ) + net(2 + rect(l13 (5550 2950) (900 300)) + ) + net(3 + rect(l13 (7350 2950) (900 300)) + ) + net(4 + rect(l13 (9150 2950) (900 300)) + ) + net(5 + rect(l13 (10950 2950) (900 300)) + ) + net(6 + rect(l13 (12750 2950) (900 300)) + ) + net(7 + rect(l13 (14550 2950) (900 300)) + ) + net(8 + rect(l13 (16350 2950) (900 300)) + ) + net(9 + rect(l13 (18150 2950) (900 300)) + ) + net(10 + rect(l13 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l13 (21750 2950) (900 300)) + rect(l13 (-19530 590) (320 320)) + rect(l13 (17820 -320) (320 320)) + rect(l14 (-18400 -260) (200 200)) + rect(l14 (17940 -200) (200 200)) + rect(l15 (-18040 -300) (17740 400)) + rect(l15 (-17921 -201) (2 2)) + rect(l15 (-221 -201) (400 400)) + rect(l15 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l4 (500 4500) (1400 3500)) + rect(l4 (-1900 -3500) (600 3500)) + rect(l4 (23300 -3500) (1400 3500)) + rect(l4 (-100 -3500) (600 3500)) + rect(l10 (-24690 -1240) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l13 (-21741 859) (2 2)) + rect(l13 (-2351 -451) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-101 -351) (2 2)) + rect(l13 (-1251 -401) (600 800)) + rect(l13 (23400 -800) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-101 -351) (2 2)) + rect(l13 (549 -401) (600 800)) + rect(l11 (-24850 -1500) (500 1500)) + rect(l11 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l13 (23440 3840) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-101 -101) (2 2)) + rect(l15 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l13 (2440 2940) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-101 -101) (2 2)) + rect(l15 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l10 (1110 1610) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-21741 -391) (2 2)) + rect(l13 (-1901 -401) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-551 -401) (2 2)) + rect(l13 (-1251 -401) (600 800)) + rect(l13 (23850 -750) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-551 -401) (2 2)) + rect(l13 (549 -401) (600 800)) + rect(l12 (-24850 -800) (500 1500)) + rect(l12 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 nomatch + xref( + net(4 8 mismatch) + net(5 4 mismatch) + net(7 6 match) + net(6 5 match) + net(2 2 mismatch) + net(8 7 mismatch) + net(1 1 mismatch) + net(3 3 mismatch) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(4 4 match) + device(3 3 mismatch) + device(2 2 match) + device(1 1 mismatch) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 new file mode 100644 index 000000000..2833efc33 --- /dev/null +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 @@ -0,0 +1,965 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS$1 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$2 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (27600 7650)) + + # Nets with their geometries + net(1 + rect(l4 (26050 2800) (525 550)) + rect(l4 (-525 -300) (300 300)) + rect(l4 (-25 -2000) (250 1450)) + rect(l8 (-465 310) (180 180)) + rect(l11 (-240 -240) (300 300)) + ) + net(2 + rect(l11 (4040 2950) (610 300)) + ) + net(3 + rect(l11 (5550 2950) (900 300)) + ) + net(4 + rect(l11 (7350 2950) (900 300)) + ) + net(5 + rect(l11 (9150 2950) (900 300)) + ) + net(6 + rect(l11 (10950 2950) (900 300)) + ) + net(7 + rect(l11 (12750 2950) (900 300)) + ) + net(8 + rect(l11 (14550 2950) (900 300)) + ) + net(9 + rect(l11 (16350 2950) (900 300)) + ) + net(10 + rect(l11 (18150 2950) (900 300)) + ) + net(11 + rect(l11 (19950 2950) (900 300)) + ) + net(12 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(13 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l8 (-26490 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l9 (-26650 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(14 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(16 name(VSS) + rect(l8 (26010 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (520 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-25780 -890) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (1260 -40) (300 1360)) + rect(l11 (400 -1360) (300 1360)) + rect(l11 (-24001 -1711) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l6 (-1025 400) (425 950)) + rect(l6 (-1100 -950) (425 950)) + rect(l10 (-25375 -2150) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(12 name(FB)) + pin(13 name(VDD)) + pin(14 name(OUT)) + pin(15 name(ENABLE)) + pin(16 name(VSS)) + + # Devices and their connections + device(1 D$NMOS + location(26450 2075) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 16) + terminal(G 1) + terminal(D 16) + terminal(B 16) + ) + + # Subcircuits and their connections + circuit(3 ND2X1 location(1800 0) + pin(0 13) + pin(1 2) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 15) + pin(6 16) + ) + circuit(4 INVX1 location(4200 0) + pin(0 13) + pin(1 3) + pin(2 16) + pin(3 13) + pin(4 2) + pin(5 16) + ) + circuit(5 INVX1 location(6000 0) + pin(0 13) + pin(1 4) + pin(2 16) + pin(3 13) + pin(4 3) + pin(5 16) + ) + circuit(6 INVX1 location(7800 0) + pin(0 13) + pin(1 5) + pin(2 16) + pin(3 13) + pin(4 4) + pin(5 16) + ) + circuit(7 INVX1 location(9600 0) + pin(0 13) + pin(1 6) + pin(2 16) + pin(3 13) + pin(4 5) + pin(5 16) + ) + circuit(8 INVX1 location(11400 0) + pin(0 13) + pin(1 7) + pin(2 16) + pin(3 13) + pin(4 6) + pin(5 16) + ) + circuit(9 INVX1 location(13200 0) + pin(0 13) + pin(1 8) + pin(2 16) + pin(3 13) + pin(4 7) + pin(5 16) + ) + circuit(10 INVX1 location(15000 0) + pin(0 13) + pin(1 9) + pin(2 16) + pin(3 13) + pin(4 8) + pin(5 16) + ) + circuit(11 INVX1 location(16800 0) + pin(0 13) + pin(1 10) + pin(2 16) + pin(3 13) + pin(4 9) + pin(5 16) + ) + circuit(12 INVX1 location(18600 0) + pin(0 13) + pin(1 11) + pin(2 16) + pin(3 13) + pin(4 10) + pin(5 16) + ) + circuit(13 INVX1 location(20400 0) + pin(0 13) + pin(1 12) + pin(2 16) + pin(3 13) + pin(4 11) + pin(5 16) + ) + circuit(14 INVX1 location(22200 0) + pin(0 13) + pin(1 14) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 16) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(NMOS MOS4) + class(PMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + net(16 name(DUMMY)) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Devices and their connections + device(1 NMOS + name($1) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 16) + terminal(D 1) + terminal(B 1) + ) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(2 6 match) + net(11 15 match) + net(3 7 match) + net(4 8 match) + net(5 9 match) + net(6 10 match) + net(7 11 match) + net(8 12 match) + net(9 13 match) + net(10 14 match) + net(1 16 match) + net(15 4 match) + net(12 3 match) + net(14 5 match) + net(13 2 match) + net(16 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + device(1 1 match) + circuit(4 2 match) + circuit(5 3 match) + circuit(6 4 match) + circuit(7 5 match) + circuit(8 6 match) + circuit(9 7 match) + circuit(10 8 match) + circuit(11 9 match) + circuit(12 10 match) + circuit(13 11 match) + circuit(14 12 match) + circuit(3 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 new file mode 100644 index 000000000..0363a34ef --- /dev/null +++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 @@ -0,0 +1,927 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (28300 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (1160 300)) + ) + net(2 + rect(l11 (6050 2950) (900 300)) + ) + net(3 + rect(l11 (7850 2950) (900 300)) + ) + net(4 + rect(l11 (9650 2950) (900 300)) + ) + net(5 + rect(l11 (11450 2950) (900 300)) + ) + net(6 + rect(l11 (13250 2950) (900 300)) + ) + net(7 + rect(l11 (15050 2950) (900 300)) + ) + net(8 + rect(l11 (16850 2950) (900 300)) + ) + net(9 + rect(l11 (18650 2950) (900 300)) + ) + net(10 + rect(l11 (20450 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (22250 2950) (2900 300)) + rect(l11 (-21980 590) (320 320)) + rect(l11 (18570 -320) (320 320)) + rect(l12 (-19150 -260) (200 200)) + rect(l12 (18690 -200) (200 200)) + rect(l13 (-18840 -300) (18890 400)) + rect(l13 (-19071 -201) (2 2)) + rect(l13 (-171 -201) (400 400)) + rect(l13 (18490 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (22600 4500) (1400 3500)) + rect(l3 (-23500 -3500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (25800 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-5090 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-22280 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (25720 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-4891 1009) (2 2)) + rect(l11 (2798 -52) (2 2)) + rect(l11 (-22152 -102) (2 2)) + rect(l11 (19749 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-22751 -401) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (25900 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-5250 -1500) (500 1500)) + rect(l9 (-22600 -1500) (500 1500)) + rect(l9 (25400 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (25990 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-151 -101) (2 2)) + rect(l13 (-151 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2490 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-151 -101) (2 2)) + rect(l13 (-151 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (27010 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-3980 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-22280 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (24709 -291) (2 2)) + rect(l11 (-3852 -2) (2 2)) + rect(l11 (-19202 -102) (2 2)) + rect(l11 (23999 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (-5150 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-22301 -351) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l10 (26250 -800) (500 1500)) + rect(l10 (-4300 -1500) (500 1500)) + rect(l10 (-22600 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4700 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6500 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(8300 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(10100 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11900 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13700 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15500 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(17300 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(19100 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20900 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(24700 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.2 b/testdata/lvs/ringo_simple_io.lvsdb.2 new file mode 100644 index 000000000..b87c0ef7e --- /dev/null +++ b/testdata/lvs/ringo_simple_io.lvsdb.2 @@ -0,0 +1,828 @@ +#%lvsdb-klayout +J( + W(RINGO) + U(0.001) + L(l3 '1/0') + L(l4 '5/0') + L(l8 '8/0') + L(l11 '9/0') + L(l12 '10/0') + L(l13 '11/0') + L(l7) + L(l2) + L(l9) + L(l6) + L(l10) + C(l3 l3 l9) + C(l4 l4 l8) + C(l8 l4 l8 l11 l2 l9 l6 l10) + C(l11 l8 l11 l12) + C(l12 l11 l12 l13) + C(l13 l12 l13) + C(l7 l7) + C(l2 l8 l2) + C(l9 l3 l8 l9) + C(l6 l8 l6) + C(l10 l8 l10) + G(l7 SUBSTRATE) + G(l10 SUBSTRATE) + D(D$PMOS PMOS + T(S + R(l2 (-550 -750) (425 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (450 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) + ) + D(D$PMOS$1 PMOS + T(S + R(l2 (-575 -750) (450 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (425 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) + ) + D(D$PMOS$2 PMOS + T(S + R(l2 (-550 -750) (425 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (425 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) + ) + D(D$NMOS NMOS + T(S + R(l6 (-550 -475) (425 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (450 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) + ) + D(D$NMOS$1 NMOS + T(S + R(l6 (-575 -475) (450 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (425 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) + ) + D(D$NMOS$2 NMOS + T(S + R(l6 (-550 -475) (425 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (425 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) + ) + X(ND2X1 + R((-100 400) (2600 7600)) + N(1 I(VDD) + R(l8 (1110 5160) (180 180)) + R(l8 (-180 920) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l11 (-240 -790) (300 1700)) + R(l11 (-1350 0) (2400 800)) + R(l11 (-1151 -401) (2 2)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + ) + N(2 I(OUT) + R(l8 (1810 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-1580 3760) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (1220 920) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + R(l11 (-110 1390) (300 1400)) + Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + R(l11 (-141 -501) (2 2)) + R(l11 (-1751 1099) (300 1400)) + R(l11 (1100 -1700) (300 300)) + R(l11 (-300 0) (300 1400)) + R(l2 (-375 -1450) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) + ) + N(3 I(VSS) + R(l8 (410 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -1300) (300 1360)) + R(l11 (-650 -2160) (2400 800)) + R(l11 (-1151 -401) (2 2)) + R(l6 (-951 859) (425 950)) + ) + N(4 + R(l3 (-100 4500) (2600 3500)) + ) + N(5 I(B) + R(l4 (1425 2860) (250 1940)) + R(l4 (-345 -950) (300 300)) + R(l4 (-205 650) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-285 1050) (180 180)) + R(l11 (-71 -91) (2 2)) + R(l11 (-171 -151) (300 300)) + ) + N(6 I(A) + R(l4 (725 2860) (250 1940)) + R(l4 (-325 -1850) (300 300)) + R(l4 (-225 1550) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-265 150) (180 180)) + R(l11 (-91 -91) (2 2)) + R(l11 (-151 -151) (300 300)) + ) + N(7 I(SUBSTRATE)) + N(8 + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) + ) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4) + P(5 I(B)) + P(6 I(A)) + P(7 I(SUBSTRATE)) + D(1 D$PMOS + Y(850 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.6375) + E(AD 0.3375) + E(PS 3.85) + E(PD 1.95) + T(S 2) + T(G 6) + T(D 1) + T(B 4) + ) + D(2 D$PMOS$1 + Y(1550 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.3375) + E(AD 0.6375) + E(PS 1.95) + E(PD 3.85) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(3 D$NMOS + Y(850 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.40375) + E(AD 0.21375) + E(PS 2.75) + E(PD 1.4) + T(S 3) + T(G 6) + T(D 8) + T(B 7) + ) + D(4 D$NMOS$1 + Y(1550 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.21375) + E(AD 0.40375) + E(PS 1.4) + E(PD 2.75) + T(S 8) + T(G 5) + T(D 2) + T(B 7) + ) + ) + X(INVX1 + R((-100 400) (2000 7600)) + N(1 I(VDD) + R(l8 (410 6260) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l11 (-240 -240) (300 1400)) + R(l11 (-650 300) (1800 800)) + R(l11 (-1450 -1100) (300 300)) + R(l11 (299 399) (2 2)) + R(l2 (-651 -2151) (425 1500)) + ) + N(2 I(OUT) + R(l8 (1110 5160) (180 180)) + R(l8 (-180 920) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -4120) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -790) (300 4790)) + R(l11 (-151 -2501) (2 2)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) + ) + N(3 I(VSS) + R(l8 (410 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -1300) (300 1360)) + R(l11 (-650 -2160) (1800 800)) + R(l11 (-851 -401) (2 2)) + R(l6 (-651 859) (425 950)) + ) + N(4 + R(l3 (-100 4500) (2000 3500)) + ) + N(5 I(IN) + R(l4 (725 2860) (250 1940)) + R(l4 (-525 -1850) (300 300)) + R(l4 (-25 1550) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-465 150) (180 180)) + R(l11 (-91 -91) (2 2)) + R(l11 (-151 -151) (300 300)) + ) + N(6 I(SUBSTRATE)) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4) + P(5 I(IN)) + P(6 I(SUBSTRATE)) + D(1 D$PMOS$2 + Y(850 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.6375) + E(AD 0.6375) + E(PS 3.85) + E(PD 3.85) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(2 D$NMOS$2 + Y(850 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.40375) + E(AD 0.40375) + E(PS 2.75) + E(PD 2.75) + T(S 3) + T(G 5) + T(D 2) + T(B 6) + ) + ) + X(RINGO + R((0 350) (25800 7650)) + N(1 + R(l11 (4040 2950) (610 300)) + ) + N(2 + R(l11 (5550 2950) (900 300)) + ) + N(3 + R(l11 (7350 2950) (900 300)) + ) + N(4 + R(l11 (9150 2950) (900 300)) + ) + N(5 + R(l11 (10950 2950) (900 300)) + ) + N(6 + R(l11 (12750 2950) (900 300)) + ) + N(7 + R(l11 (14550 2950) (900 300)) + ) + N(8 + R(l11 (16350 2950) (900 300)) + ) + N(9 + R(l11 (18150 2950) (900 300)) + ) + N(10 + R(l11 (19950 2950) (900 300)) + ) + N(11 I(FB) + R(l11 (21750 2950) (900 300)) + R(l11 (-19530 590) (320 320)) + R(l11 (17820 -320) (320 320)) + R(l12 (-18400 -260) (200 200)) + R(l12 (17940 -200) (200 200)) + R(l13 (-18040 -300) (17740 400)) + R(l13 (-17921 -201) (2 2)) + R(l13 (-221 -201) (400 400)) + R(l13 (17740 -400) (400 400)) + ) + N(12 I(VDD) + R(l3 (500 4500) (1400 3500)) + R(l3 (-1900 -3500) (600 3500)) + R(l3 (23300 -3500) (1400 3500)) + R(l3 (-100 -3500) (600 3500)) + R(l8 (-24690 -1240) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (23220 370) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l11 (-21741 859) (2 2)) + R(l11 (-2351 -451) (1200 800)) + R(l11 (-750 -1450) (300 1400)) + R(l11 (-101 -351) (2 2)) + R(l11 (-1251 -401) (600 800)) + R(l11 (23400 -800) (1200 800)) + R(l11 (-750 -1450) (300 1400)) + R(l11 (-101 -351) (2 2)) + R(l11 (549 -401) (600 800)) + R(l9 (-24850 -1500) (500 1500)) + R(l9 (22900 -1500) (500 1500)) + ) + N(13 I(OUT) + R(l11 (23440 3840) (320 320)) + R(l12 (-260 -260) (200 200)) + R(l13 (-101 -101) (2 2)) + R(l13 (-201 -201) (400 400)) + ) + N(14 I(ENABLE) + R(l11 (2440 2940) (320 320)) + R(l12 (-260 -260) (200 200)) + R(l13 (-101 -101) (2 2)) + R(l13 (-201 -201) (400 400)) + ) + N(15 I(VSS) + R(l8 (1110 1610) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (23220 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-21741 -391) (2 2)) + R(l11 (-1901 -401) (300 1400)) + R(l11 (-750 -1450) (1200 800)) + R(l11 (-551 -401) (2 2)) + R(l11 (-1251 -401) (600 800)) + R(l11 (23850 -750) (300 1400)) + R(l11 (-750 -1450) (1200 800)) + R(l11 (-551 -401) (2 2)) + R(l11 (549 -401) (600 800)) + R(l10 (-24850 -800) (500 1500)) + R(l10 (22900 -1500) (500 1500)) + ) + P(11 I(FB)) + P(12 I(VDD)) + P(13 I(OUT)) + P(14 I(ENABLE)) + P(15 I(VSS)) + X(1 ND2X1 Y(1800 0) + P(0 12) + P(1 1) + P(2 15) + P(3 12) + P(4 11) + P(5 14) + P(6 15) + ) + X(2 INVX1 Y(4200 0) + P(0 12) + P(1 2) + P(2 15) + P(3 12) + P(4 1) + P(5 15) + ) + X(3 INVX1 Y(6000 0) + P(0 12) + P(1 3) + P(2 15) + P(3 12) + P(4 2) + P(5 15) + ) + X(4 INVX1 Y(7800 0) + P(0 12) + P(1 4) + P(2 15) + P(3 12) + P(4 3) + P(5 15) + ) + X(5 INVX1 Y(9600 0) + P(0 12) + P(1 5) + P(2 15) + P(3 12) + P(4 4) + P(5 15) + ) + X(6 INVX1 Y(11400 0) + P(0 12) + P(1 6) + P(2 15) + P(3 12) + P(4 5) + P(5 15) + ) + X(7 INVX1 Y(13200 0) + P(0 12) + P(1 7) + P(2 15) + P(3 12) + P(4 6) + P(5 15) + ) + X(8 INVX1 Y(15000 0) + P(0 12) + P(1 8) + P(2 15) + P(3 12) + P(4 7) + P(5 15) + ) + X(9 INVX1 Y(16800 0) + P(0 12) + P(1 9) + P(2 15) + P(3 12) + P(4 8) + P(5 15) + ) + X(10 INVX1 Y(18600 0) + P(0 12) + P(1 10) + P(2 15) + P(3 12) + P(4 9) + P(5 15) + ) + X(11 INVX1 Y(20400 0) + P(0 12) + P(1 11) + P(2 15) + P(3 12) + P(4 10) + P(5 15) + ) + X(12 INVX1 Y(22200 0) + P(0 12) + P(1 13) + P(2 15) + P(3 12) + P(4 11) + P(5 15) + ) + ) +) +H( + X(ND2X1 + N(1 I(VDD)) + N(2 I(OUT)) + N(3 I(VSS)) + N(4 I(NWELL)) + N(5 I(B)) + N(6 I(A)) + N(7 I(BULK)) + N(8 I('1')) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4 I(NWELL)) + P(5 I(B)) + P(6 I(A)) + P(7 I(BULK)) + D(1 PMOS + I($1) + E(L 0.25) + E(W 1.5) + E(AS 0) + E(AD 0) + E(PS 0) + E(PD 0) + T(S 2) + T(G 6) + T(D 1) + T(B 4) + ) + D(2 PMOS + I($2) + E(L 0.25) + E(W 1.5) + E(AS 0) + E(AD 0) + E(PS 0) + E(PD 0) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(3 NMOS + I($3) + E(L 0.25) + E(W 0.95) + E(AS 0) + E(AD 0) + E(PS 0) + E(PD 0) + T(S 3) + T(G 6) + T(D 8) + T(B 7) + ) + D(4 NMOS + I($4) + E(L 0.25) + E(W 0.95) + E(AS 0) + E(AD 0) + E(PS 0) + E(PD 0) + T(S 8) + T(G 5) + T(D 2) + T(B 7) + ) + ) + X(INVX1 + N(1 I(VDD)) + N(2 I(OUT)) + N(3 I(VSS)) + N(4 I(NWELL)) + N(5 I(IN)) + N(6 I(BULK)) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4 I(NWELL)) + P(5 I(IN)) + P(6 I(BULK)) + D(1 PMOS + I($1) + E(L 0.25) + E(W 1.5) + E(AS 0) + E(AD 0) + E(PS 0) + E(PD 0) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(2 NMOS + I($2) + E(L 0.25) + E(W 0.95) + E(AS 0) + E(AD 0) + E(PS 0) + E(PD 0) + T(S 3) + T(G 5) + T(D 2) + T(B 6) + ) + ) + X(RINGO + N(1 I(VSS)) + N(2 I(VDD)) + N(3 I(FB)) + N(4 I(ENABLE)) + N(5 I(OUT)) + N(6 I('1')) + N(7 I('2')) + N(8 I('3')) + N(9 I('4')) + N(10 I('5')) + N(11 I('6')) + N(12 I('7')) + N(13 I('8')) + N(14 I('9')) + N(15 I('10')) + P(1 I(VSS)) + P(2 I(VDD)) + P(3 I(FB)) + P(4 I(ENABLE)) + P(5 I(OUT)) + X(1 ND2X1 I($1) + P(0 2) + P(1 6) + P(2 1) + P(3 2) + P(4 3) + P(5 4) + P(6 1) + ) + X(2 INVX1 I($2) + P(0 2) + P(1 7) + P(2 1) + P(3 2) + P(4 6) + P(5 1) + ) + X(3 INVX1 I($3) + P(0 2) + P(1 8) + P(2 1) + P(3 2) + P(4 7) + P(5 1) + ) + X(4 INVX1 I($4) + P(0 2) + P(1 9) + P(2 1) + P(3 2) + P(4 8) + P(5 1) + ) + X(5 INVX1 I($5) + P(0 2) + P(1 10) + P(2 1) + P(3 2) + P(4 9) + P(5 1) + ) + X(6 INVX1 I($6) + P(0 2) + P(1 11) + P(2 1) + P(3 2) + P(4 10) + P(5 1) + ) + X(7 INVX1 I($7) + P(0 2) + P(1 12) + P(2 1) + P(3 2) + P(4 11) + P(5 1) + ) + X(8 INVX1 I($8) + P(0 2) + P(1 13) + P(2 1) + P(3 2) + P(4 12) + P(5 1) + ) + X(9 INVX1 I($9) + P(0 2) + P(1 14) + P(2 1) + P(3 2) + P(4 13) + P(5 1) + ) + X(10 INVX1 I($10) + P(0 2) + P(1 15) + P(2 1) + P(3 2) + P(4 14) + P(5 1) + ) + X(11 INVX1 I($11) + P(0 2) + P(1 3) + P(2 1) + P(3 2) + P(4 15) + P(5 1) + ) + X(12 INVX1 I($12) + P(0 2) + P(1 5) + P(2 1) + P(3 2) + P(4 3) + P(5 1) + ) + ) +) +Z( + X(INVX1 INVX1 1 + Z( + N(4 4 1) + N(5 5 1) + N(2 2 1) + N(6 6 1) + N(1 1 1) + N(3 3 1) + P(3 3 1) + P(4 4 1) + P(1 1 1) + P(5 5 1) + P(0 0 1) + P(2 2 1) + D(2 2 1) + D(1 1 1) + ) + ) + X(ND2X1 ND2X1 1 + Z( + N(8 8 1) + N(4 4 1) + N(6 6 1) + N(5 5 1) + N(2 2 1) + N(7 7 1) + N(1 1 1) + N(3 3 1) + P(3 3 1) + P(5 5 1) + P(4 4 1) + P(1 1 1) + P(6 6 1) + P(0 0 1) + P(2 2 1) + D(3 3 1) + D(4 4 1) + D(1 1 1) + D(2 2 1) + ) + ) + X(RINGO RINGO 1 + Z( + N(1 6 1) + N(10 15 1) + N(2 7 1) + N(3 8 1) + N(4 9 1) + N(5 10 1) + N(6 11 1) + N(7 12 1) + N(8 13 1) + N(9 14 1) + N(14 4 1) + N(11 3 1) + N(13 5 1) + N(12 2 1) + N(15 1 1) + P(3 3 1) + P(0 2 1) + P(2 4 1) + P(1 1 1) + P(4 0 1) + X(2 2 1) + X(3 3 1) + X(4 4 1) + X(5 5 1) + X(6 6 1) + X(7 7 1) + X(8 8 1) + X(9 9 1) + X(10 10 1) + X(11 11 1) + X(12 12 1) + X(1 1 1) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.2 b/testdata/lvs/ringo_simple_io2.lvsdb.2 new file mode 100644 index 000000000..b585c4ca4 --- /dev/null +++ b/testdata/lvs/ringo_simple_io2.lvsdb.2 @@ -0,0 +1,908 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 new file mode 100644 index 000000000..04e80f7d8 --- /dev/null +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 @@ -0,0 +1,907 @@ +#%lvsdb-klayout + +# Layout +layout( + top(top) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(nd2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INV + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(top + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 nd2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INV location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INV location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INV location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INV location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INV location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INV location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INV location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INV location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INV location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INV location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INV location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INV INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(nd2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(top RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 new file mode 100644 index 000000000..cb34ae9bf --- /dev/null +++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 @@ -0,0 +1,908 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (7350 2950) (900 300)) + ) + net(4 + rect(l11 (9150 2950) (900 300)) + ) + net(5 + rect(l11 (10950 2950) (900 300)) + ) + net(6 + rect(l11 (12750 2950) (900 300)) + ) + net(7 + rect(l11 (14550 2950) (900 300)) + ) + net(8 + rect(l11 (16350 2950) (900 300)) + ) + net(9 + rect(l11 (18150 2950) (900 300)) + ) + net(10 + rect(l11 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l8 (1110 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-21741 -391) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(A)) + net(6 name(B)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(A)) + pin(6 name(B)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 5) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 6) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 5 match) + net(5 6 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 4 match) + pin(4 5 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 new file mode 100644 index 000000000..f244f5156 --- /dev/null +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 @@ -0,0 +1,910 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l5 '5/0') + layer(l14 '8/0') + layer(l17 '9/0') + layer(l18 '10/0') + layer(l19 '11/0') + layer(l8) + layer(l4) + layer(l15) + layer(l9) + layer(l16) + + # Mask layer connectivity + connect(l3 l3 l15) + connect(l5 l5 l14) + connect(l14 l5 l14 l17 l4 l15 l9 l16) + connect(l17 l14 l17 l18) + connect(l18 l17 l18 l19) + connect(l19 l18 l19) + connect(l8 l8) + connect(l4 l14 l4) + connect(l15 l3 l14 l15) + connect(l9 l14 l9) + connect(l16 l14 l16) + + # Global nets and connectivity + global(l8 SUBSTRATE) + global(l16 SUBSTRATE) + + # Device class section + class(PM MOS4) + class(NM MOS4) + class(PMHV MOS4) + class(NMHV MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PM PM + terminal(S + rect(l4 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l4 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PM$1 PM + terminal(S + rect(l4 (-575 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l4 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PM$2 PM + terminal(S + rect(l4 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l4 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NM NM + terminal(S + rect(l9 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l9 (125 -475) (450 950)) + ) + terminal(B + rect(l8 (-125 -475) (250 950)) + ) + ) + device(D$NM$1 NM + terminal(S + rect(l9 (-575 -475) (450 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l9 (125 -475) (425 950)) + ) + terminal(B + rect(l8 (-125 -475) (250 950)) + ) + ) + device(D$NM$2 NM + terminal(S + rect(l9 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l9 (125 -475) (425 950)) + ) + terminal(B + rect(l8 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l14 (1110 5160) (180 180)) + rect(l14 (-180 920) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l17 (-240 -790) (300 1700)) + rect(l17 (-1350 0) (2400 800)) + rect(l17 (-1151 -401) (2 2)) + rect(l4 (-276 -2151) (425 1500)) + rect(l4 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l14 (1810 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-1580 3760) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (1220 920) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + polygon(l17 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l17 (-110 1390) (300 1400)) + polygon(l17 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l17 (-141 -501) (2 2)) + rect(l17 (-1751 1099) (300 1400)) + rect(l17 (1100 -1700) (300 300)) + rect(l17 (-300 0) (300 1400)) + rect(l4 (-375 -1450) (425 1500)) + rect(l4 (-1800 -1500) (425 1500)) + rect(l9 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l14 (410 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -1300) (300 1360)) + rect(l17 (-650 -2160) (2400 800)) + rect(l17 (-1151 -401) (2 2)) + rect(l9 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-285 1050) (180 180)) + rect(l17 (-71 -91) (2 2)) + rect(l17 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-265 150) (180 180)) + rect(l17 (-91 -91) (2 2)) + rect(l17 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l9 (975 1660) (425 950)) + rect(l9 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PM + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PM$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NM + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NM$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l14 (410 6260) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l17 (-240 -240) (300 1400)) + rect(l17 (-650 300) (1800 800)) + rect(l17 (-1450 -1100) (300 300)) + rect(l17 (299 399) (2 2)) + rect(l4 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l14 (1110 5160) (180 180)) + rect(l14 (-180 920) (180 180)) + rect(l14 (-180 -730) (180 180)) + rect(l14 (-180 -4120) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -790) (300 4790)) + rect(l17 (-151 -2501) (2 2)) + rect(l4 (-226 1049) (425 1500)) + rect(l9 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l14 (410 1770) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-240 -1300) (300 1360)) + rect(l17 (-650 -2160) (1800 800)) + rect(l17 (-851 -401) (2 2)) + rect(l9 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l14 (-465 150) (180 180)) + rect(l17 (-91 -91) (2 2)) + rect(l17 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PM$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NM$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l17 (4040 2950) (610 300)) + ) + net(2 + rect(l17 (5550 2950) (900 300)) + ) + net(3 + rect(l17 (7350 2950) (900 300)) + ) + net(4 + rect(l17 (9150 2950) (900 300)) + ) + net(5 + rect(l17 (10950 2950) (900 300)) + ) + net(6 + rect(l17 (12750 2950) (900 300)) + ) + net(7 + rect(l17 (14550 2950) (900 300)) + ) + net(8 + rect(l17 (16350 2950) (900 300)) + ) + net(9 + rect(l17 (18150 2950) (900 300)) + ) + net(10 + rect(l17 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l17 (21750 2950) (900 300)) + rect(l17 (-19530 590) (320 320)) + rect(l17 (17820 -320) (320 320)) + rect(l18 (-18400 -260) (200 200)) + rect(l18 (17940 -200) (200 200)) + rect(l19 (-18040 -300) (17740 400)) + rect(l19 (-17921 -201) (2 2)) + rect(l19 (-221 -201) (400 400)) + rect(l19 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l14 (-24690 -1240) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (23220 370) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l17 (-21741 859) (2 2)) + rect(l17 (-2351 -451) (1200 800)) + rect(l17 (-750 -1450) (300 1400)) + rect(l17 (-101 -351) (2 2)) + rect(l17 (-1251 -401) (600 800)) + rect(l17 (23400 -800) (1200 800)) + rect(l17 (-750 -1450) (300 1400)) + rect(l17 (-101 -351) (2 2)) + rect(l17 (549 -401) (600 800)) + rect(l15 (-24850 -1500) (500 1500)) + rect(l15 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l17 (23440 3840) (320 320)) + rect(l18 (-260 -260) (200 200)) + rect(l19 (-101 -101) (2 2)) + rect(l19 (-201 -201) (400 400)) + ) + net(14 name(ENABLE) + rect(l17 (2440 2940) (320 320)) + rect(l18 (-260 -260) (200 200)) + rect(l19 (-101 -101) (2 2)) + rect(l19 (-201 -201) (400 400)) + ) + net(15 name(VSS) + rect(l14 (1110 1610) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l14 (23220 370) (180 180)) + rect(l14 (-180 -1280) (180 180)) + rect(l14 (-180 370) (180 180)) + rect(l17 (-21741 -391) (2 2)) + rect(l17 (-1901 -401) (300 1400)) + rect(l17 (-750 -1450) (1200 800)) + rect(l17 (-551 -401) (2 2)) + rect(l17 (-1251 -401) (600 800)) + rect(l17 (23850 -750) (300 1400)) + rect(l17 (-750 -1450) (1200 800)) + rect(l17 (-551 -401) (2 2)) + rect(l17 (549 -401) (600 800)) + rect(l16 (-24850 -800) (500 1500)) + rect(l16 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.2 b/testdata/lvs/ringo_simple_simplification.lvsdb.2 new file mode 100644 index 000000000..8ef1094e4 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.2 @@ -0,0 +1,1095 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-225 -1300) (675 450)) + rect(l4 (0 -1100) (250 1950)) + rect(l4 (-1225 -1850) (300 300)) + rect(l4 (675 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-950 -2000) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (450 -5390) (250 1450)) + rect(l4 (-950 -1450) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(2 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-1640 -240) (300 1400)) + rect(l11 (-650 300) (2400 800)) + rect(l11 (-2050 -1100) (300 300)) + rect(l11 (1100 -300) (300 300)) + rect(l11 (-1101 399) (2 2)) + rect(l11 (799 -2101) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + ) + net(3 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(4 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (1220 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-1640 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-650 0) (300 1360)) + rect(l11 (-1101 -1761) (2 2)) + rect(l6 (724 859) (425 950)) + rect(l6 (-1800 -950) (425 950)) + ) + net(5 + rect(l3 (-100 4500) (2600 3500)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(IN)) + pin(2 name(VDD)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 5800) + param(L 0.25) + param(W 3) + param(AS 0.975) + param(AD 0.975) + param(PS 5.8) + param(PD 5.8) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 5) + ) + device(3 D$NMOS + device(D$NMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 2135) + param(L 0.25) + param(W 1.9) + param(AS 0.6175) + param(AD 0.6175) + param(PS 4.15) + param(PD 4.15) + terminal(S 4) + terminal(G 1) + terminal(D 3) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((600 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (18150 2950) (900 300)) + ) + net(4 + rect(l11 (19950 2950) (900 300)) + ) + net(5 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(6 name(VDD) + rect(l3 (1100 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-22341 859) (2 2)) + rect(l11 (-1751 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(7 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(8 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(9 name(VSS) + rect(l8 (1710 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22341 -391) (2 2)) + rect(l11 (-1301 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + net(10 + rect(l11 (7350 2950) (900 300)) + ) + net(11 + rect(l11 (16350 2950) (900 300)) + ) + net(12 + rect(l11 (9150 2950) (900 300)) + ) + net(13 + rect(l11 (10950 2950) (900 300)) + ) + net(14 + rect(l11 (12750 2950) (900 300)) + ) + net(15 + rect(l11 (14550 2950) (900 300)) + ) + + # Outgoing pins and their connections to nets + pin(5 name(FB)) + pin(6 name(VDD)) + pin(7 name(OUT)) + pin(8 name(ENABLE)) + pin(9 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 6) + pin(1 1) + pin(2 9) + pin(3 6) + pin(4 5) + pin(5 8) + pin(6 9) + ) + circuit(2 INVX1 location(4200 0) + pin(0 6) + pin(1 2) + pin(2 9) + pin(3 6) + pin(4 1) + pin(5 9) + ) + circuit(3 INVX1 location(6000 0) + pin(0 6) + pin(1 10) + pin(2 9) + pin(3 6) + pin(4 2) + pin(5 9) + ) + circuit(4 INVX1 location(16800 0) + pin(0 6) + pin(1 3) + pin(2 9) + pin(3 6) + pin(4 11) + pin(5 9) + ) + circuit(5 INVX1 location(18600 0) + pin(0 6) + pin(1 4) + pin(2 9) + pin(3 6) + pin(4 3) + pin(5 9) + ) + circuit(6 INVX1 location(20400 0) + pin(0 6) + pin(1 5) + pin(2 9) + pin(3 6) + pin(4 4) + pin(5 9) + ) + circuit(7 INVX2 location(22200 0) + pin(0 5) + pin(1 6) + pin(2 7) + pin(3 9) + pin(4 6) + pin(5 9) + ) + circuit(17 INVX1 location(7800 0) + pin(0 6) + pin(1 12) + pin(2 9) + pin(3 6) + pin(4 10) + pin(5 9) + ) + circuit(18 INVX1 location(9600 0) + pin(0 6) + pin(1 13) + pin(2 9) + pin(3 6) + pin(4 12) + pin(5 9) + ) + circuit(19 INVX1 location(11400 0) + pin(0 6) + pin(1 14) + pin(2 9) + pin(3 6) + pin(4 13) + pin(5 9) + ) + circuit(20 INVX1 location(13200 0) + pin(0 6) + pin(1 15) + pin(2 9) + pin(3 6) + pin(4 14) + pin(5 9) + ) + circuit(21 INVX1 location(15000 0) + pin(0 6) + pin(1 11) + pin(2 9) + pin(3 6) + pin(4 15) + pin(5 9) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX2 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX2 INVX2 match + xref( + net(5 4 match) + net(1 5 match) + net(3 2 match) + net(6 6 match) + net(2 1 match) + net(4 3 match) + pin(4 3 match) + pin(0 4 match) + pin(2 1 match) + pin(5 5 match) + pin(1 0 match) + pin(3 2 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(4 15 match) + net(2 7 match) + net(10 8 match) + net(12 9 match) + net(13 10 match) + net(14 11 match) + net(15 12 match) + net(11 13 match) + net(3 14 match) + net(8 4 match) + net(5 3 match) + net(7 5 match) + net(6 2 match) + net(9 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(17 4 match) + circuit(18 5 match) + circuit(19 6 match) + circuit(20 7 match) + circuit(21 8 match) + circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 new file mode 100644 index 000000000..03d0da560 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 @@ -0,0 +1,1095 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + rect(l6 (950 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-225 -1300) (675 450)) + rect(l4 (0 -1100) (250 1950)) + rect(l4 (-1225 -1850) (300 300)) + rect(l4 (675 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-950 -2000) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (450 -5390) (250 1450)) + rect(l4 (-950 -1450) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(2 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-1640 -240) (300 1400)) + rect(l11 (-650 300) (2400 800)) + rect(l11 (-2050 -1100) (300 300)) + rect(l11 (1100 -300) (300 300)) + rect(l11 (-1101 399) (2 2)) + rect(l11 (799 -2101) (300 1400)) + rect(l2 (-375 -1450) (425 1500)) + rect(l2 (-1800 -1500) (425 1500)) + ) + net(3 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(4 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (1220 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-1640 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-650 0) (300 1360)) + rect(l11 (-1101 -1761) (2 2)) + rect(l6 (724 859) (425 950)) + rect(l6 (-1800 -950) (425 950)) + ) + net(5 + rect(l3 (-100 4500) (2600 3500)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(IN)) + pin(2 name(VDD)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 5800) + param(L 0.25) + param(W 3) + param(AS 0.975) + param(AD 0.975) + param(PS 5.8) + param(PD 5.8) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 5) + ) + device(3 D$NMOS + device(D$NMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 2135) + param(L 0.25) + param(W 1.9) + param(AS 0.6175) + param(AD 0.6175) + param(PS 4.15) + param(PD 4.15) + terminal(S 4) + terminal(G 1) + terminal(D 3) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((600 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (18150 2950) (900 300)) + ) + net(4 + rect(l11 (19950 2950) (900 300)) + ) + net(5 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(6 name(VDD) + rect(l3 (1100 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-22341 859) (2 2)) + rect(l11 (-1751 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(7 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(8 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(9 name(VSS) + rect(l8 (1710 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22341 -391) (2 2)) + rect(l11 (-1301 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + net(10 + rect(l11 (7350 2950) (900 300)) + ) + net(11 + rect(l11 (16350 2950) (900 300)) + ) + net(12 + rect(l11 (9150 2950) (900 300)) + ) + net(13 + rect(l11 (10950 2950) (900 300)) + ) + net(14 + rect(l11 (12750 2950) (900 300)) + ) + net(15 + rect(l11 (14550 2950) (900 300)) + ) + + # Outgoing pins and their connections to nets + pin(5 name(FB)) + pin(6 name(VDD)) + pin(7 name(OUT)) + pin(8 name(ENABLE)) + pin(9 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 6) + pin(1 1) + pin(2 9) + pin(3 6) + pin(4 5) + pin(5 8) + pin(6 9) + ) + circuit(2 INVX1 location(4200 0) + pin(0 6) + pin(1 2) + pin(2 9) + pin(3 6) + pin(4 1) + pin(5 9) + ) + circuit(3 INVX1 location(6000 0) + pin(0 6) + pin(1 10) + pin(2 9) + pin(3 6) + pin(4 2) + pin(5 9) + ) + circuit(4 INVX1 location(16800 0) + pin(0 6) + pin(1 3) + pin(2 9) + pin(3 6) + pin(4 11) + pin(5 9) + ) + circuit(5 INVX1 location(18600 0) + pin(0 6) + pin(1 4) + pin(2 9) + pin(3 6) + pin(4 3) + pin(5 9) + ) + circuit(6 INVX1 location(20400 0) + pin(0 6) + pin(1 5) + pin(2 9) + pin(3 6) + pin(4 4) + pin(5 9) + ) + circuit(7 INVX2 location(22200 0) + pin(0 5) + pin(1 6) + pin(2 7) + pin(3 9) + pin(4 6) + pin(5 9) + ) + circuit(13 INVX1 location(7800 0) + pin(0 6) + pin(1 12) + pin(2 9) + pin(3 6) + pin(4 10) + pin(5 9) + ) + circuit(14 INVX1 location(9600 0) + pin(0 6) + pin(1 13) + pin(2 9) + pin(3 6) + pin(4 12) + pin(5 9) + ) + circuit(15 INVX1 location(11400 0) + pin(0 6) + pin(1 14) + pin(2 9) + pin(3 6) + pin(4 13) + pin(5 9) + ) + circuit(16 INVX1 location(13200 0) + pin(0 6) + pin(1 15) + pin(2 9) + pin(3 6) + pin(4 14) + pin(5 9) + ) + circuit(17 INVX1 location(15000 0) + pin(0 6) + pin(1 11) + pin(2 9) + pin(3 6) + pin(4 15) + pin(5 9) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX2 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX2 INVX2 match + xref( + net(5 4 match) + net(1 5 match) + net(3 2 match) + net(6 6 match) + net(2 1 match) + net(4 3 match) + pin(4 3 match) + pin(0 4 match) + pin(2 1 match) + pin(5 5 match) + pin(1 0 match) + pin(3 2 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(4 15 match) + net(2 7 match) + net(10 8 match) + net(12 9 match) + net(13 10 match) + net(14 11 match) + net(15 12 match) + net(11 13 match) + net(3 14 match) + net(8 4 match) + net(5 3 match) + net(7 5 match) + net(6 2 match) + net(9 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(13 4 match) + circuit(14 5 match) + circuit(15 6 match) + circuit(16 7 match) + circuit(17 8 match) + circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) + ) + ) +) From fccd78a2229bfc439c238991c6270fd045b1db12 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 10:37:51 +0100 Subject: [PATCH 17/21] Fixed #448 and updated test data --- src/db/db/dbLayoutToNetlistWriter.cc | 12 ++++++------ testdata/algo/l2n_writer_au_2s.txt | 2 ++ testdata/algo/l2n_writer_au_s.txt | 2 ++ testdata/lvs/inv2.lvsdb | 4 ++++ testdata/lvs/invchain_cheat.lvsdb | 4 ++++ testdata/lvs/ringo_simple_io.lvsdb.1 | 4 ++++ testdata/lvs/ringo_simple_io.lvsdb.2 | 4 ++++ testdata/lvs/ringo_simple_io2.l2n.1 | 2 ++ 8 files changed, 28 insertions(+), 6 deletions(-) diff --git a/src/db/db/dbLayoutToNetlistWriter.cc b/src/db/db/dbLayoutToNetlistWriter.cc index 62c9d6116..19ce996e9 100644 --- a/src/db/db/dbLayoutToNetlistWriter.cc +++ b/src/db/db/dbLayoutToNetlistWriter.cc @@ -199,12 +199,12 @@ void std_writer_impl::write (bool nested, std::mapbegin_device_classes () != mp_netlist->end_device_classes () && ! Keys::is_short ()) { *mp_stream << endl << indent << "# Device class section" << endl; - for (db::Netlist::const_device_class_iterator c = mp_netlist->begin_device_classes (); c != mp_netlist->end_device_classes (); ++c) { - db::DeviceClassTemplateBase *temp = db::DeviceClassTemplateBase::is_a (c.operator-> ()); - if (temp) { - *mp_stream << indent << Keys::class_key << "(" << tl::to_word_or_quoted_string (c->name ()) << " " << tl::to_word_or_quoted_string (temp->name ()) << ")" << endl; - m_progress.set (mp_stream->pos ()); - } + } + for (db::Netlist::const_device_class_iterator c = mp_netlist->begin_device_classes (); c != mp_netlist->end_device_classes (); ++c) { + db::DeviceClassTemplateBase *temp = db::DeviceClassTemplateBase::is_a (c.operator-> ()); + if (temp) { + *mp_stream << indent << Keys::class_key << "(" << tl::to_word_or_quoted_string (c->name ()) << " " << tl::to_word_or_quoted_string (temp->name ()) << ")" << endl; + m_progress.set (mp_stream->pos ()); } } diff --git a/testdata/algo/l2n_writer_au_2s.txt b/testdata/algo/l2n_writer_au_2s.txt index e06f526ba..fd1c17892 100644 --- a/testdata/algo/l2n_writer_au_2s.txt +++ b/testdata/algo/l2n_writer_au_2s.txt @@ -32,6 +32,8 @@ C(ptie diff_cont ptie) C(nsd diff_cont nsd) G(rbulk BULK) G(ptie BULK) +K(PMOS MOS4) +K(NMOS MOS4) D(D$PMOS PMOS T(S R(psd (-650 -475) (525 950)) diff --git a/testdata/algo/l2n_writer_au_s.txt b/testdata/algo/l2n_writer_au_s.txt index fe2768a0d..fbe139f9b 100644 --- a/testdata/algo/l2n_writer_au_s.txt +++ b/testdata/algo/l2n_writer_au_s.txt @@ -23,6 +23,8 @@ C(metal2 via1 metal2 metal2_lbl) C(metal2_lbl metal2) C(psd diff_cont psd) C(nsd diff_cont nsd) +K(PMOS MOS3) +K(NMOS MOS3) D(D$PMOS PMOS T(S R(psd (-650 -475) (525 950)) diff --git a/testdata/lvs/inv2.lvsdb b/testdata/lvs/inv2.lvsdb index 782d6282e..5f4e3fee5 100644 --- a/testdata/lvs/inv2.lvsdb +++ b/testdata/lvs/inv2.lvsdb @@ -30,6 +30,8 @@ J( C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) + K(PMOS MOS4) + K(NMOS MOS4) D(D$PMOS PMOS T(S R(l2 (-575 -750) (450 1500)) @@ -146,6 +148,8 @@ J( ) ) H( + K(PMOS MOS4) + K(NMOS MOS4) X(INVERTER_WITH_DIODES N(1 I(VSS)) N(2 I(IN)) diff --git a/testdata/lvs/invchain_cheat.lvsdb b/testdata/lvs/invchain_cheat.lvsdb index a661487b5..67ff6bc68 100644 --- a/testdata/lvs/invchain_cheat.lvsdb +++ b/testdata/lvs/invchain_cheat.lvsdb @@ -27,6 +27,8 @@ J( C(l2 l6 l2) C(l5 l6 l5) G(l14 SUBSTRATE) + K(PMOS MOS3) + K(NMOS MOS3) D(D$PMOS PMOS T(S R(l2 (-900 -475) (775 950)) @@ -265,6 +267,8 @@ J( ) ) H( + K(PMOS MOS3) + K(NMOS MOS3) X(INV N(1 I('1')) N(2 I('2')) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.1 b/testdata/lvs/ringo_simple_io.lvsdb.1 index ab4626e4d..ed998ca98 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io.lvsdb.1 @@ -26,6 +26,8 @@ J( C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) + K(PMOS MOS4) + K(NMOS MOS4) D(D$PMOS PMOS T(S R(l2 (-550 -750) (425 1500)) @@ -518,6 +520,8 @@ J( ) ) H( + K(PMOS MOS4) + K(NMOS MOS4) X(ND2X1 N(1 I(VDD)) N(2 I(OUT)) diff --git a/testdata/lvs/ringo_simple_io.lvsdb.2 b/testdata/lvs/ringo_simple_io.lvsdb.2 index b87c0ef7e..8b7238826 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.2 +++ b/testdata/lvs/ringo_simple_io.lvsdb.2 @@ -26,6 +26,8 @@ J( C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) + K(PMOS MOS4) + K(NMOS MOS4) D(D$PMOS PMOS T(S R(l2 (-550 -750) (425 1500)) @@ -518,6 +520,8 @@ J( ) ) H( + K(PMOS MOS4) + K(NMOS MOS4) X(ND2X1 N(1 I(VDD)) N(2 I(OUT)) diff --git a/testdata/lvs/ringo_simple_io2.l2n.1 b/testdata/lvs/ringo_simple_io2.l2n.1 index ca7ecbc14..7e0cf804b 100644 --- a/testdata/lvs/ringo_simple_io2.l2n.1 +++ b/testdata/lvs/ringo_simple_io2.l2n.1 @@ -25,6 +25,8 @@ C(l6 l8 l6) C(l10 l8 l10) G(l7 SUBSTRATE) G(l10 SUBSTRATE) +K(PMOS MOS4) +K(NMOS MOS4) D(D$PMOS PMOS T(S R(l2 (-550 -750) (425 1500)) From b802220ae9ec9bc774de59ee7cf7f0829d3878cb Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 10:48:11 +0100 Subject: [PATCH 18/21] Updated test data --- testdata/algo/lvs_test1b_au.lvsdb.2 | 646 ++++++++++++++++++++++++++ testdata/algo/lvs_test2b_au.lvsdb.2 | 682 ++++++++++++++++++++++++++++ testdata/lvs/ringo_simple_io2.l2n.2 | 517 +++++++++++++++++++++ 3 files changed, 1845 insertions(+) create mode 100644 testdata/algo/lvs_test1b_au.lvsdb.2 create mode 100644 testdata/algo/lvs_test2b_au.lvsdb.2 create mode 100644 testdata/lvs/ringo_simple_io2.l2n.2 diff --git a/testdata/algo/lvs_test1b_au.lvsdb.2 b/testdata/algo/lvs_test1b_au.lvsdb.2 new file mode 100644 index 000000000..a8c999396 --- /dev/null +++ b/testdata/algo/lvs_test1b_au.lvsdb.2 @@ -0,0 +1,646 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(bulk '1/0') + layer(nwell '1/0') + layer(poly '3/0') + layer(poly_lbl '3/1') + layer(diff_cont '4/0') + layer(poly_cont '5/0') + layer(metal1 '6/0') + layer(metal1_lbl '6/1') + layer(via1 '7/0') + layer(metal2 '8/0') + layer(metal2_lbl '8/1') + layer(ntie) + layer(psd) + layer(ptie) + layer(nsd) + + # Mask layer connectivity + connect(nwell nwell ntie) + connect(poly poly poly_lbl poly_cont) + connect(poly_lbl poly) + connect(diff_cont diff_cont metal1 ntie psd ptie nsd) + connect(poly_cont poly poly_cont metal1) + connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) + connect(metal1_lbl metal1) + connect(via1 metal1 via1 metal2) + connect(metal2 via1 metal2 metal2_lbl) + connect(metal2_lbl metal2) + connect(ntie nwell diff_cont ntie) + connect(psd diff_cont psd) + connect(ptie diff_cont ptie) + connect(nsd diff_cont nsd) + + # Global nets and connectivity + global(bulk BULK) + global(ptie BULK) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(psd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (550 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(psd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (525 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(nsd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (550 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(nsd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (525 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Circuit boundary + rect((-1700 -2440) (3100 7820)) + + # Nets with their geometries + net(1 + rect(nwell (-1400 1800) (2800 3580)) + rect(diff_cont (-1510 -650) (220 220)) + rect(ntie (-510 -450) (800 680)) + ) + net(2 name(IN) + rect(poly (-525 -250) (250 2500)) + rect(poly (-1425 -630) (2100 360)) + rect(poly (-125 -2230) (250 2500)) + rect(poly (-1050 -3850) (250 2400)) + rect(poly (550 1200) (250 2400)) + rect(poly (-250 -6000) (250 2400)) + rect(poly (-1050 1200) (250 2400)) + rect(poly_lbl (-526 -2601) (2 2)) + rect(poly_cont (-831 -111) (220 220)) + ) + net(3 name(OUT) + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (1310 -3710) (360 2220)) + rect(metal1 (-1900 -800) (2220 360)) + rect(metal1 (-2280 -2400) (360 2840)) + rect(metal1 (-360 -3600) (360 1560)) + rect(metal1 (1240 2040) (360 1560)) + rect(metal1 (-360 -5160) (360 1560)) + rect(metal1 (-1960 2040) (360 1560)) + rect(metal1_lbl (1419 -2181) (2 2)) + rect(psd (-1851 524) (525 1750)) + rect(psd (1050 -1750) (525 1750)) + rect(nsd (-2100 -5350) (525 1750)) + rect(nsd (1050 -1750) (525 1750)) + ) + net(4 name(VSS) + rect(diff_cont (-110 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 980) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-290 -290) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -705) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 -1450) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -775) (2800 1700)) + rect(metal2_lbl (-161 -541) (2 2)) + rect(nsd (-1516 -1186) (550 1750)) + ) + net(5 name(VDD) + rect(diff_cont (-110 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -1420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (-290 -1490) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -1505) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -1575) (2800 1700)) + rect(metal2_lbl (-151 -1251) (2 2)) + rect(psd (-1526 -476) (550 1750)) + ) + net(6 name(BULK) + rect(diff_cont (-110 -2160) (220 220)) + rect(ptie (-510 -450) (800 680)) + ) + + # Outgoing pins and their connections to nets + pin(1) + pin(2 name(IN)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5 name(VDD)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 3200) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(2 D$NMOS + device(D$NMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 -400) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Circuit boundary + rect((0 -1640) (5740 7820)) + + # Nets with their geometries + net(1 name(BULK)) + net(2) + net(3) + net(4) + net(5) + net(6) + net(7) + + # Outgoing pins and their connections to nets + pin(1 name(BULK)) + pin(2) + pin(3) + pin(4) + pin(5) + pin(6) + pin(7) + + # Subcircuits and their connections + circuit(1 INV2 location(1700 800) + pin(0 7) + pin(1 5) + pin(2 4) + pin(3 3) + pin(4 2) + pin(5 1) + ) + circuit(2 INV2 location(4340 800) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((-1720 -2440) (26880 7820)) + + # Nets with their geometries + net(1 name(FB) + rect(metal1 (-1700 1620) (360 360)) + rect(via1 (-305 -305) (250 250)) + rect(via1 (23190 -250) (250 250)) + rect(metal2 (-23765 -325) (23840 400)) + rect(metal2_lbl (-22121 -201) (2 2)) + ) + net(2 name(OSC) + rect(via1 (24435 1675) (250 250)) + rect(metal2 (-325 -325) (400 400)) + rect(metal2_lbl (-201 -201) (2 2)) + ) + net(3 name(VDD) + rect(metal1 (-180 3900) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 -2221) (2 2)) + ) + net(4 name(VSS) + rect(metal1 (-180 -2220) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 1099) (2 2)) + ) + net(5) + net(6) + net(7) + net(8) + net(9) + net(10) + net(11) + net(12) + + # Outgoing pins and their connections to nets + pin(1 name(FB)) + pin(2 name(OSC)) + pin(3 name(VDD)) + pin(4 name(VSS)) + + # Subcircuits and their connections + circuit(1 INV2PAIR location(19420 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 10) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR location(-1700 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 8) + pin(4 1) + pin(5 9) + pin(6 3) + ) + circuit(3 INV2PAIR location(3580 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 7) + pin(4 9) + pin(5 12) + pin(6 3) + ) + circuit(4 INV2PAIR location(8860 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 6) + pin(4 12) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR location(14140 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 5) + pin(4 11) + pin(5 10) + pin(6 3) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(2 NMOS + name($3) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($1) + pin(0 7) + pin(1 5) + pin(2 4) + pin(3 3) + pin(4 2) + pin(5 1) + ) + circuit(2 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('6')) + net(6 name('100')) + net(7 name('5')) + net(8 name('101')) + net(9 name('8')) + net(10 name('102')) + net(11 name('7')) + net(12 name('103')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + + # Subcircuits and their connections + circuit(1 INV2PAIR name($1) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 5) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR name($2) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 6) + pin(4 1) + pin(5 7) + pin(6 3) + ) + circuit(3 INV2PAIR name($3) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 8) + pin(4 7) + pin(5 9) + pin(6 3) + ) + circuit(4 INV2PAIR name($4) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 10) + pin(4 9) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR name($5) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 12) + pin(4 11) + pin(5 5) + pin(6 3) + ) + + ) +) + +# Cross reference +xref( + circuit(INV2 INV2 match + xref( + net(1 1 match) + net(6 6 match) + net(2 2 match) + net(3 3 match) + net(5 5 match) + net(4 4 match) + pin(0 0 match) + pin(5 5 match) + pin(1 1 match) + pin(2 2 match) + pin(4 4 match) + pin(3 3 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INV2PAIR INV2PAIR match + xref( + net(2 2 match) + net(3 3 match) + net(4 4 match) + net(5 5 match) + net(6 6 match) + net(7 7 match) + net(1 1 match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) + pin(4 4 match) + pin(5 5 match) + pin(6 6 match) + pin(0 0 match) + circuit(1 1 match) + circuit(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(8 6 match) + net(7 8 match) + net(6 10 match) + net(5 12 match) + net(9 7 match) + net(10 5 match) + net(11 11 match) + net(12 9 match) + net(1 1 match) + net(2 2 match) + net(3 3 match) + net(4 4 match) + pin(0 0 match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) + circuit(1 1 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + ) + ) +) diff --git a/testdata/algo/lvs_test2b_au.lvsdb.2 b/testdata/algo/lvs_test2b_au.lvsdb.2 new file mode 100644 index 000000000..59b791eab --- /dev/null +++ b/testdata/algo/lvs_test2b_au.lvsdb.2 @@ -0,0 +1,682 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(bulk '1/0') + layer(nwell '1/0') + layer(poly '3/0') + layer(poly_lbl '3/1') + layer(diff_cont '4/0') + layer(poly_cont '5/0') + layer(metal1 '6/0') + layer(metal1_lbl '6/1') + layer(via1 '7/0') + layer(metal2 '8/0') + layer(metal2_lbl '8/1') + layer(ntie) + layer(psd) + layer(ptie) + layer(nsd) + + # Mask layer connectivity + connect(nwell nwell ntie) + connect(poly poly poly_lbl poly_cont) + connect(poly_lbl poly) + connect(diff_cont diff_cont metal1 ntie psd ptie nsd) + connect(poly_cont poly poly_cont metal1) + connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1) + connect(metal1_lbl metal1) + connect(via1 metal1 via1 metal2) + connect(metal2 via1 metal2 metal2_lbl) + connect(metal2_lbl metal2) + connect(ntie nwell diff_cont ntie) + connect(psd diff_cont psd) + connect(ptie diff_cont ptie) + connect(nsd diff_cont nsd) + + # Global nets and connectivity + global(bulk BULK) + global(ptie BULK) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(psd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (550 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(psd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(psd (125 -875) (525 1750)) + ) + terminal(B + rect(nwell (-125 -875) (250 1750)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(nsd (-650 -875) (525 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (550 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(nsd (-675 -875) (550 1750)) + ) + terminal(G + rect(poly (-125 -875) (250 1750)) + ) + terminal(D + rect(nsd (125 -875) (525 1750)) + ) + terminal(B + rect(bulk (-125 -875) (250 1750)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Circuit boundary + rect((-1700 -2440) (3100 7820)) + + # Nets with their geometries + net(1 + rect(nwell (-1400 1800) (2800 3580)) + rect(diff_cont (-1510 -650) (220 220)) + rect(ntie (-510 -450) (800 680)) + ) + net(2 name(IN) + rect(poly (-525 -250) (250 2500)) + rect(poly (-1425 -630) (2100 360)) + rect(poly (-125 -2230) (250 2500)) + rect(poly (-1050 -3850) (250 2400)) + rect(poly (550 1200) (250 2400)) + rect(poly (-250 -6000) (250 2400)) + rect(poly (-1050 1200) (250 2400)) + rect(poly_lbl (-526 -2601) (2 2)) + rect(poly_cont (-831 -111) (220 220)) + ) + net(3 name(OUT) + rect(diff_cont (-910 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (1380 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -3820) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-1820 3380) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (1310 -3710) (360 2220)) + rect(metal1 (-1900 -800) (2220 360)) + rect(metal1 (-2280 -2400) (360 2840)) + rect(metal1 (-360 -3600) (360 1560)) + rect(metal1 (1240 2040) (360 1560)) + rect(metal1 (-360 -5160) (360 1560)) + rect(metal1 (-1960 2040) (360 1560)) + rect(metal1_lbl (1419 -2181) (2 2)) + rect(psd (-1851 524) (525 1750)) + rect(psd (1050 -1750) (525 1750)) + rect(nsd (-2100 -5350) (525 1750)) + rect(nsd (1050 -1750) (525 1750)) + ) + net(4 name(VSS) + rect(diff_cont (-110 90) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 980) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(diff_cont (-220 -620) (220 220)) + rect(metal1 (-290 -290) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -705) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 -1450) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -775) (2800 1700)) + rect(metal2_lbl (-161 -541) (2 2)) + rect(nsd (-1516 -1186) (550 1750)) + ) + net(5 name(VDD) + rect(diff_cont (-110 2490) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 -1420) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(diff_cont (-220 180) (220 220)) + rect(metal1 (-290 -1490) (360 1560)) + rect(metal1 (-360 -1560) (360 1560)) + rect(via1 (-305 -1505) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(via1 (-250 150) (250 250)) + rect(metal2 (-1525 -1575) (2800 1700)) + rect(metal2_lbl (-151 -1251) (2 2)) + rect(psd (-1526 -476) (550 1750)) + ) + net(6 name(BULK) + rect(diff_cont (-110 -2160) (220 220)) + rect(ptie (-510 -450) (800 680)) + ) + + # Outgoing pins and their connections to nets + pin(1) + pin(2 name(IN)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5 name(VDD)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 3200) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(2 D$NMOS + device(D$NMOS$1 location(800 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(-400 -400) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Circuit boundary + rect((0 -1640) (5740 7820)) + + # Nets with their geometries + net(1 name(BULK)) + net(2) + net(3) + net(4) + net(5) + net(6) + net(7) + + # Outgoing pins and their connections to nets + pin(1 name(BULK)) + pin(2) + pin(3) + pin(4) + pin(5) + pin(6) + pin(7) + + # Subcircuits and their connections + circuit(1 INV2 location(1700 800) + pin(0 7) + pin(1 5) + pin(2 4) + pin(3 3) + pin(4 2) + pin(5 1) + ) + circuit(2 INV2 location(4340 800) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((-1720 -2440) (26880 7820)) + + # Nets with their geometries + net(1 name(FB) + rect(metal1 (-1700 1620) (360 360)) + rect(via1 (-305 -305) (250 250)) + rect(via1 (23190 -250) (250 250)) + rect(metal2 (-23765 -325) (23840 400)) + rect(metal2_lbl (-22121 -201) (2 2)) + ) + net(2 name(OSC) + rect(via1 (24435 1675) (250 250)) + rect(metal2 (-325 -325) (400 400)) + rect(metal2_lbl (-201 -201) (2 2)) + ) + net(3 name(VDD) + rect(metal1 (-180 3900) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 -2221) (2 2)) + ) + net(4 name(VSS) + rect(metal1 (-180 -2220) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal1 (2280 -1120) (360 1120)) + rect(metal2_lbl (-23941 1099) (2 2)) + ) + net(5) + net(6) + net(7) + net(8) + net(9) + net(10) + net(11) + net(12) + + # Outgoing pins and their connections to nets + pin(1 name(FB)) + pin(2 name(OSC)) + pin(3 name(VDD)) + pin(4 name(VSS)) + + # Subcircuits and their connections + circuit(1 INV2PAIR location(19420 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 10) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR location(-1700 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 8) + pin(4 1) + pin(5 9) + pin(6 3) + ) + circuit(3 INV2PAIR location(3580 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 7) + pin(4 9) + pin(5 12) + pin(6 3) + ) + circuit(4 INV2PAIR location(8860 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 6) + pin(4 12) + pin(5 11) + pin(6 3) + ) + circuit(5 INV2PAIR location(14140 -800) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 5) + pin(4 11) + pin(5 10) + pin(6 3) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(INV2 + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 5) + terminal(B 1) + ) + device(2 NMOS + name($3) + param(L 0.25) + param(W 3.5) + param(AS 1.4) + param(AD 1.4) + param(PS 6.85) + param(PD 6.85) + terminal(S 3) + terminal(G 2) + terminal(D 4) + terminal(B 6) + ) + + ) + circuit(INV2PAIR + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) + circuit(RINGO + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('6')) + net(6 name('5')) + net(7 name('101')) + net(8 name('8')) + net(9 name('102')) + net(10 name('7')) + net(11 name('103')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + + # Subcircuits and their connections + circuit(1 INV2PAIR name($1) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 5) + pin(5 2) + pin(6 3) + ) + circuit(2 INV2PAIR name($2) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 1) + pin(4 1) + pin(5 6) + pin(6 3) + ) + circuit(3 INV2PAIR name($3) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 7) + pin(4 6) + pin(5 8) + pin(6 3) + ) + circuit(4 INV2PAIR name($4) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 9) + pin(4 8) + pin(5 10) + pin(6 3) + ) + circuit(5 INV2PAIR name($5) + pin(0 4) + pin(1 3) + pin(2 4) + pin(3 11) + pin(4 10) + pin(5 5) + pin(6 3) + ) + + ) + circuit(INV2PAIRX + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(() INV2PAIRX mismatch + xref( + ) + ) + circuit(INV2 INV2 match + xref( + net(1 1 match) + net(6 6 match) + net(2 2 match) + net(3 3 match) + net(5 5 match) + net(4 4 match) + pin(0 0 match) + pin(5 5 match) + pin(1 1 match) + pin(2 2 match) + pin(4 4 match) + pin(3 3 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INV2PAIR INV2PAIR nomatch + xref( + net(2 2 mismatch) + net(3 3 mismatch) + net(5 4 match) + net(4 5 mismatch) + net(6 6 match) + net(7 7 mismatch) + net(1 1 mismatch) + pin(1 1 match) + pin(2 2 match) + pin(4 3 match) + pin(3 4 match) + pin(5 5 match) + pin(6 6 match) + pin(0 0 match) + circuit(2 () mismatch) + circuit(1 1 mismatch) + ) + ) + circuit(RINGO RINGO nomatch + xref( + net(() 7 mismatch) + net(() 9 mismatch) + net(() 11 mismatch) + net(() 6 mismatch) + net(() 8 mismatch) + net(5 () mismatch) + net(6 () mismatch) + net(7 () mismatch) + net(9 () mismatch) + net(11 () mismatch) + net(12 () mismatch) + net(10 1 mismatch) + net(8 10 mismatch) + net(1 5 mismatch) + net(2 2 match) + net(3 3 match) + net(4 4 match) + pin(() 0 match) + pin(0 () match) + pin(1 1 match) + pin(2 2 match) + pin(3 3 match) + circuit(() 2 mismatch) + circuit(() 3 mismatch) + circuit(() 4 mismatch) + circuit(() 5 mismatch) + circuit(2 () mismatch) + circuit(3 () mismatch) + circuit(4 () mismatch) + circuit(5 () mismatch) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_io2.l2n.2 b/testdata/lvs/ringo_simple_io2.l2n.2 new file mode 100644 index 000000000..88dcfadc0 --- /dev/null +++ b/testdata/lvs/ringo_simple_io2.l2n.2 @@ -0,0 +1,517 @@ +#%l2n-klayout +W(RINGO) +U(0.001) +L(l3 '1/0') +L(l4 '5/0') +L(l8 '8/0') +L(l11 '9/0') +L(l12 '10/0') +L(l13 '11/0') +L(l7) +L(l2) +L(l9) +L(l6) +L(l10) +C(l3 l3 l9) +C(l4 l4 l8) +C(l8 l4 l8 l11 l2 l9 l6 l10) +C(l11 l8 l11 l12) +C(l12 l11 l12 l13) +C(l13 l12 l13) +C(l7 l7) +C(l2 l8 l2) +C(l9 l3 l8 l9) +C(l6 l8 l6) +C(l10 l8 l10) +G(l7 SUBSTRATE) +G(l10 SUBSTRATE) +D(D$PMOS PMOS + T(S + R(l2 (-550 -750) (425 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (450 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) +) +D(D$PMOS$1 PMOS + T(S + R(l2 (-575 -750) (450 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (425 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) +) +D(D$PMOS$2 PMOS + T(S + R(l2 (-550 -750) (425 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (425 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) +) +D(D$NMOS NMOS + T(S + R(l6 (-550 -475) (425 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (450 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) +) +D(D$NMOS$1 NMOS + T(S + R(l6 (-575 -475) (450 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (425 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) +) +D(D$NMOS$2 NMOS + T(S + R(l6 (-550 -475) (425 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (425 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) +) +X(ND2X1 + R((-100 400) (2600 7600)) + N(1 I(VDD) + R(l8 (1110 5160) (180 180)) + R(l8 (-180 920) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l11 (-240 -790) (300 1700)) + R(l11 (-1350 0) (2400 800)) + R(l11 (-1151 -401) (2 2)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + ) + N(2 I(OUT) + R(l8 (1810 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-1580 3760) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (1220 920) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + R(l11 (-110 1390) (300 1400)) + Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + R(l11 (-141 -501) (2 2)) + R(l11 (-1751 1099) (300 1400)) + R(l11 (1100 -1700) (300 300)) + R(l11 (-300 0) (300 1400)) + R(l2 (-375 -1450) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) + ) + N(3 I(VSS) + R(l8 (410 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -1300) (300 1360)) + R(l11 (-650 -2160) (2400 800)) + R(l11 (-1151 -401) (2 2)) + R(l6 (-951 859) (425 950)) + ) + N(4 + R(l3 (-100 4500) (2600 3500)) + ) + N(5 I(B) + R(l4 (1425 2860) (250 1940)) + R(l4 (-345 -950) (300 300)) + R(l4 (-205 650) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-285 1050) (180 180)) + R(l11 (-71 -91) (2 2)) + R(l11 (-171 -151) (300 300)) + ) + N(6 I(A) + R(l4 (725 2860) (250 1940)) + R(l4 (-325 -1850) (300 300)) + R(l4 (-225 1550) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-265 150) (180 180)) + R(l11 (-91 -91) (2 2)) + R(l11 (-151 -151) (300 300)) + ) + N(7 I(SUBSTRATE)) + N(8 + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) + ) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4) + P(5 I(B)) + P(6 I(A)) + P(7 I(SUBSTRATE)) + D(1 D$PMOS + Y(850 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.6375) + E(AD 0.3375) + E(PS 3.85) + E(PD 1.95) + T(S 2) + T(G 6) + T(D 1) + T(B 4) + ) + D(2 D$PMOS$1 + Y(1550 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.3375) + E(AD 0.6375) + E(PS 1.95) + E(PD 3.85) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(3 D$NMOS + Y(850 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.40375) + E(AD 0.21375) + E(PS 2.75) + E(PD 1.4) + T(S 3) + T(G 6) + T(D 8) + T(B 7) + ) + D(4 D$NMOS$1 + Y(1550 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.21375) + E(AD 0.40375) + E(PS 1.4) + E(PD 2.75) + T(S 8) + T(G 5) + T(D 2) + T(B 7) + ) +) +X(INVX1 + R((-100 400) (2000 7600)) + N(1 I(VDD) + R(l8 (410 6260) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l11 (-240 -240) (300 1400)) + R(l11 (-650 300) (1800 800)) + R(l11 (-1450 -1100) (300 300)) + R(l11 (299 399) (2 2)) + R(l2 (-651 -2151) (425 1500)) + ) + N(2 I(OUT) + R(l8 (1110 5160) (180 180)) + R(l8 (-180 920) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -4120) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -790) (300 4790)) + R(l11 (-151 -2501) (2 2)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) + ) + N(3 I(VSS) + R(l8 (410 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -1300) (300 1360)) + R(l11 (-650 -2160) (1800 800)) + R(l11 (-851 -401) (2 2)) + R(l6 (-651 859) (425 950)) + ) + N(4 + R(l3 (-100 4500) (2000 3500)) + ) + N(5 I(IN) + R(l4 (725 2860) (250 1940)) + R(l4 (-525 -1850) (300 300)) + R(l4 (-25 1550) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-465 150) (180 180)) + R(l11 (-91 -91) (2 2)) + R(l11 (-151 -151) (300 300)) + ) + N(6 I(SUBSTRATE)) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4) + P(5 I(IN)) + P(6 I(SUBSTRATE)) + D(1 D$PMOS$2 + Y(850 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.6375) + E(AD 0.6375) + E(PS 3.85) + E(PD 3.85) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(2 D$NMOS$2 + Y(850 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.40375) + E(AD 0.40375) + E(PS 2.75) + E(PD 2.75) + T(S 3) + T(G 5) + T(D 2) + T(B 6) + ) +) +X(RINGO + R((0 350) (25800 7650)) + N(1 + R(l11 (4040 2950) (610 300)) + ) + N(2 + R(l11 (5550 2950) (900 300)) + ) + N(3 + R(l11 (7350 2950) (900 300)) + ) + N(4 + R(l11 (9150 2950) (900 300)) + ) + N(5 + R(l11 (10950 2950) (900 300)) + ) + N(6 + R(l11 (12750 2950) (900 300)) + ) + N(7 + R(l11 (14550 2950) (900 300)) + ) + N(8 + R(l11 (16350 2950) (900 300)) + ) + N(9 + R(l11 (18150 2950) (900 300)) + ) + N(10 + R(l11 (19950 2950) (900 300)) + ) + N(11 I(FB) + R(l11 (21750 2950) (900 300)) + R(l11 (-19530 590) (320 320)) + R(l11 (17820 -320) (320 320)) + R(l12 (-18400 -260) (200 200)) + R(l12 (17940 -200) (200 200)) + R(l13 (-18040 -300) (17740 400)) + R(l13 (-17921 -201) (2 2)) + R(l13 (-221 -201) (400 400)) + R(l13 (17740 -400) (400 400)) + ) + N(12 I(VDD) + R(l3 (500 4500) (1400 3500)) + R(l3 (-1900 -3500) (600 3500)) + R(l3 (23300 -3500) (1400 3500)) + R(l3 (-100 -3500) (600 3500)) + R(l8 (-24690 -1240) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (23220 370) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l11 (-21741 859) (2 2)) + R(l11 (-2351 -451) (1200 800)) + R(l11 (-750 -1450) (300 1400)) + R(l11 (-101 -351) (2 2)) + R(l11 (-1251 -401) (600 800)) + R(l11 (23400 -800) (1200 800)) + R(l11 (-750 -1450) (300 1400)) + R(l11 (-101 -351) (2 2)) + R(l11 (549 -401) (600 800)) + R(l9 (-24850 -1500) (500 1500)) + R(l9 (22900 -1500) (500 1500)) + ) + N(13 I(OUT) + R(l11 (23440 3840) (320 320)) + R(l12 (-260 -260) (200 200)) + R(l13 (-101 -101) (2 2)) + R(l13 (-201 -201) (400 400)) + ) + N(14 I(ENABLE) + R(l11 (2440 2940) (320 320)) + R(l12 (-260 -260) (200 200)) + R(l13 (-101 -101) (2 2)) + R(l13 (-201 -201) (400 400)) + ) + N(15 I(VSS) + R(l8 (1110 1610) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (23220 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-21741 -391) (2 2)) + R(l11 (-1901 -401) (300 1400)) + R(l11 (-750 -1450) (1200 800)) + R(l11 (-551 -401) (2 2)) + R(l11 (-1251 -401) (600 800)) + R(l11 (23850 -750) (300 1400)) + R(l11 (-750 -1450) (1200 800)) + R(l11 (-551 -401) (2 2)) + R(l11 (549 -401) (600 800)) + R(l10 (-24850 -800) (500 1500)) + R(l10 (22900 -1500) (500 1500)) + ) + P(11 I(FB)) + P(12 I(VDD)) + P(13 I(OUT)) + P(14 I(ENABLE)) + P(15 I(VSS)) + X(1 ND2X1 Y(1800 0) + P(0 12) + P(1 1) + P(2 15) + P(3 12) + P(4 11) + P(5 14) + P(6 15) + ) + X(2 INVX1 Y(4200 0) + P(0 12) + P(1 2) + P(2 15) + P(3 12) + P(4 1) + P(5 15) + ) + X(3 INVX1 Y(6000 0) + P(0 12) + P(1 3) + P(2 15) + P(3 12) + P(4 2) + P(5 15) + ) + X(4 INVX1 Y(7800 0) + P(0 12) + P(1 4) + P(2 15) + P(3 12) + P(4 3) + P(5 15) + ) + X(5 INVX1 Y(9600 0) + P(0 12) + P(1 5) + P(2 15) + P(3 12) + P(4 4) + P(5 15) + ) + X(6 INVX1 Y(11400 0) + P(0 12) + P(1 6) + P(2 15) + P(3 12) + P(4 5) + P(5 15) + ) + X(7 INVX1 Y(13200 0) + P(0 12) + P(1 7) + P(2 15) + P(3 12) + P(4 6) + P(5 15) + ) + X(8 INVX1 Y(15000 0) + P(0 12) + P(1 8) + P(2 15) + P(3 12) + P(4 7) + P(5 15) + ) + X(9 INVX1 Y(16800 0) + P(0 12) + P(1 9) + P(2 15) + P(3 12) + P(4 8) + P(5 15) + ) + X(10 INVX1 Y(18600 0) + P(0 12) + P(1 10) + P(2 15) + P(3 12) + P(4 9) + P(5 15) + ) + X(11 INVX1 Y(20400 0) + P(0 12) + P(1 11) + P(2 15) + P(3 12) + P(4 10) + P(5 15) + ) + X(12 INVX1 Y(22200 0) + P(0 12) + P(1 13) + P(2 15) + P(3 12) + P(4 11) + P(5 15) + ) +) From c9d528dc883c1e402ffd6dccd30a29107ba83548 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 15:46:15 +0100 Subject: [PATCH 19/21] Fixed #447 - CentOS 6 build fixed. --- src/db/db/dbHierNetworkProcessor.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/db/db/dbHierNetworkProcessor.h b/src/db/db/dbHierNetworkProcessor.h index 923c57e78..fda6e07e8 100644 --- a/src/db/db/dbHierNetworkProcessor.h +++ b/src/db/db/dbHierNetworkProcessor.h @@ -739,8 +739,7 @@ inline bool equal_array_delegates (const db::ArrayBase *a, const db::ArrayBase * if ((a == 0) != (b == 0)) { return false; } else if (a) { - static const db::array_base_ptr_cmp_f arr_less; - return ! arr_less (a, b) && ! arr_less (b, a); + return ! db::array_base_ptr_cmp_f () (a, b) && ! db::array_base_ptr_cmp_f () (b, a); } else { return true; } @@ -751,8 +750,7 @@ inline bool less_array_delegates (const db::ArrayBase *a, const db::ArrayBase *b if ((a == 0) != (b == 0)) { return (a == 0) < (b == 0); } else if (a) { - static const db::array_base_ptr_cmp_f arr_less; - return arr_less (a, b); + return db::array_base_ptr_cmp_f () (a, b); } else { return false; } From e0be042e675a0306c5080f45f653b0a56613a087 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 20:48:56 +0100 Subject: [PATCH 20/21] Test data update for CentOS 6 --- .../lvs/ringo_simple_dummy_device.lvsdb.3 | 965 +++++++++++++++ .../lvs/ringo_simple_simplification.lvsdb.3 | 1095 +++++++++++++++++ ...o_simple_simplification_with_align.lvsdb.3 | 1095 +++++++++++++++++ 3 files changed, 3155 insertions(+) create mode 100644 testdata/lvs/ringo_simple_dummy_device.lvsdb.3 create mode 100644 testdata/lvs/ringo_simple_simplification.lvsdb.3 create mode 100644 testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 new file mode 100644 index 000000000..8fc3eac47 --- /dev/null +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 @@ -0,0 +1,965 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS$1 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$2 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (27600 7650)) + + # Nets with their geometries + net(1 + rect(l4 (26050 2800) (525 550)) + rect(l4 (-525 -300) (300 300)) + rect(l4 (-25 -2000) (250 1450)) + rect(l8 (-465 310) (180 180)) + rect(l11 (-240 -240) (300 300)) + ) + net(2 + rect(l11 (4040 2950) (610 300)) + ) + net(3 + rect(l11 (5550 2950) (900 300)) + ) + net(4 + rect(l11 (7350 2950) (900 300)) + ) + net(5 + rect(l11 (9150 2950) (900 300)) + ) + net(6 + rect(l11 (10950 2950) (900 300)) + ) + net(7 + rect(l11 (12750 2950) (900 300)) + ) + net(8 + rect(l11 (14550 2950) (900 300)) + ) + net(9 + rect(l11 (16350 2950) (900 300)) + ) + net(10 + rect(l11 (18150 2950) (900 300)) + ) + net(11 + rect(l11 (19950 2950) (900 300)) + ) + net(12 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(13 name(VDD) + rect(l3 (500 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l3 (0 -3500) (600 3500)) + rect(l8 (-26490 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-21741 859) (2 2)) + rect(l11 (-2351 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l9 (-26650 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(14 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(15 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(16 name(VSS) + rect(l8 (26010 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (520 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-25780 -890) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (1260 -40) (300 1360)) + rect(l11 (400 -1360) (300 1360)) + rect(l11 (-24001 -1711) (2 2)) + rect(l11 (-1901 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l11 (0 -800) (600 800)) + rect(l6 (-1025 400) (425 950)) + rect(l6 (-1100 -950) (425 950)) + rect(l10 (-25375 -2150) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(12 name(FB)) + pin(13 name(VDD)) + pin(14 name(OUT)) + pin(15 name(ENABLE)) + pin(16 name(VSS)) + + # Devices and their connections + device(1 D$NMOS + location(26450 2075) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 16) + terminal(G 1) + terminal(D 16) + terminal(B 16) + ) + + # Subcircuits and their connections + circuit(3 ND2X1 location(1800 0) + pin(0 13) + pin(1 2) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 15) + pin(6 16) + ) + circuit(4 INVX1 location(4200 0) + pin(0 13) + pin(1 3) + pin(2 16) + pin(3 13) + pin(4 2) + pin(5 16) + ) + circuit(5 INVX1 location(6000 0) + pin(0 13) + pin(1 4) + pin(2 16) + pin(3 13) + pin(4 3) + pin(5 16) + ) + circuit(6 INVX1 location(7800 0) + pin(0 13) + pin(1 5) + pin(2 16) + pin(3 13) + pin(4 4) + pin(5 16) + ) + circuit(7 INVX1 location(9600 0) + pin(0 13) + pin(1 6) + pin(2 16) + pin(3 13) + pin(4 5) + pin(5 16) + ) + circuit(8 INVX1 location(11400 0) + pin(0 13) + pin(1 7) + pin(2 16) + pin(3 13) + pin(4 6) + pin(5 16) + ) + circuit(9 INVX1 location(13200 0) + pin(0 13) + pin(1 8) + pin(2 16) + pin(3 13) + pin(4 7) + pin(5 16) + ) + circuit(10 INVX1 location(15000 0) + pin(0 13) + pin(1 9) + pin(2 16) + pin(3 13) + pin(4 8) + pin(5 16) + ) + circuit(11 INVX1 location(16800 0) + pin(0 13) + pin(1 10) + pin(2 16) + pin(3 13) + pin(4 9) + pin(5 16) + ) + circuit(12 INVX1 location(18600 0) + pin(0 13) + pin(1 11) + pin(2 16) + pin(3 13) + pin(4 10) + pin(5 16) + ) + circuit(13 INVX1 location(20400 0) + pin(0 13) + pin(1 12) + pin(2 16) + pin(3 13) + pin(4 11) + pin(5 16) + ) + circuit(14 INVX1 location(22200 0) + pin(0 13) + pin(1 14) + pin(2 16) + pin(3 13) + pin(4 12) + pin(5 16) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(NMOS MOS4) + class(PMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + net(16 name(DUMMY)) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Devices and their connections + device(1 NMOS + name($1) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 16) + terminal(D 1) + terminal(B 1) + ) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(2 6 match) + net(11 15 match) + net(3 7 match) + net(4 8 match) + net(5 9 match) + net(6 10 match) + net(7 11 match) + net(8 12 match) + net(9 13 match) + net(10 14 match) + net(1 16 match) + net(15 4 match) + net(12 3 match) + net(14 5 match) + net(13 2 match) + net(16 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + device(1 1 match) + circuit(4 2 match) + circuit(5 3 match) + circuit(6 4 match) + circuit(7 5 match) + circuit(8 6 match) + circuit(9 7 match) + circuit(10 8 match) + circuit(11 9 match) + circuit(12 10 match) + circuit(13 11 match) + circuit(14 12 match) + circuit(3 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.3 b/testdata/lvs/ringo_simple_simplification.lvsdb.3 new file mode 100644 index 000000000..53ac9099a --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.3 @@ -0,0 +1,1095 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-225 -1300) (675 450)) + rect(l4 (0 -1100) (250 1950)) + rect(l4 (-1225 -1850) (300 300)) + rect(l4 (675 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-950 -2000) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (450 -5390) (250 1450)) + rect(l4 (-950 -1450) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(2 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-1640 -240) (300 1400)) + rect(l11 (-650 300) (2400 800)) + rect(l11 (-2050 -1100) (300 300)) + rect(l11 (1100 -300) (300 300)) + rect(l11 (-1101 399) (2 2)) + rect(l11 (799 -2101) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + ) + net(3 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(4 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (1220 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-1640 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-650 0) (300 1360)) + rect(l11 (-1101 -1761) (2 2)) + rect(l6 (724 859) (425 950)) + rect(l6 (-1800 -950) (425 950)) + ) + net(5 + rect(l3 (-100 4500) (2600 3500)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(IN)) + pin(2 name(VDD)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 5800) + param(L 0.25) + param(W 3) + param(AS 0.975) + param(AD 0.975) + param(PS 5.8) + param(PD 5.8) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 5) + ) + device(3 D$NMOS + device(D$NMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 2135) + param(L 0.25) + param(W 1.9) + param(AS 0.6175) + param(AD 0.6175) + param(PS 4.15) + param(PD 4.15) + terminal(S 4) + terminal(G 1) + terminal(D 3) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((600 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (18150 2950) (900 300)) + ) + net(4 + rect(l11 (19950 2950) (900 300)) + ) + net(5 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(6 name(VDD) + rect(l3 (1100 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-22341 859) (2 2)) + rect(l11 (-1751 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(7 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(8 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(9 name(VSS) + rect(l8 (1710 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22341 -391) (2 2)) + rect(l11 (-1301 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + net(10 + rect(l11 (7350 2950) (900 300)) + ) + net(11 + rect(l11 (16350 2950) (900 300)) + ) + net(12 + rect(l11 (9150 2950) (900 300)) + ) + net(13 + rect(l11 (10950 2950) (900 300)) + ) + net(14 + rect(l11 (12750 2950) (900 300)) + ) + net(15 + rect(l11 (14550 2950) (900 300)) + ) + + # Outgoing pins and their connections to nets + pin(5 name(FB)) + pin(6 name(VDD)) + pin(7 name(OUT)) + pin(8 name(ENABLE)) + pin(9 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 6) + pin(1 1) + pin(2 9) + pin(3 6) + pin(4 5) + pin(5 8) + pin(6 9) + ) + circuit(2 INVX1 location(4200 0) + pin(0 6) + pin(1 2) + pin(2 9) + pin(3 6) + pin(4 1) + pin(5 9) + ) + circuit(3 INVX1 location(6000 0) + pin(0 6) + pin(1 10) + pin(2 9) + pin(3 6) + pin(4 2) + pin(5 9) + ) + circuit(4 INVX1 location(16800 0) + pin(0 6) + pin(1 3) + pin(2 9) + pin(3 6) + pin(4 11) + pin(5 9) + ) + circuit(5 INVX1 location(18600 0) + pin(0 6) + pin(1 4) + pin(2 9) + pin(3 6) + pin(4 3) + pin(5 9) + ) + circuit(6 INVX1 location(20400 0) + pin(0 6) + pin(1 5) + pin(2 9) + pin(3 6) + pin(4 4) + pin(5 9) + ) + circuit(7 INVX2 location(22200 0) + pin(0 5) + pin(1 6) + pin(2 7) + pin(3 9) + pin(4 6) + pin(5 9) + ) + circuit(17 INVX1 location(7800 0) + pin(0 6) + pin(1 12) + pin(2 9) + pin(3 6) + pin(4 10) + pin(5 9) + ) + circuit(18 INVX1 location(9600 0) + pin(0 6) + pin(1 13) + pin(2 9) + pin(3 6) + pin(4 12) + pin(5 9) + ) + circuit(19 INVX1 location(11400 0) + pin(0 6) + pin(1 14) + pin(2 9) + pin(3 6) + pin(4 13) + pin(5 9) + ) + circuit(20 INVX1 location(13200 0) + pin(0 6) + pin(1 15) + pin(2 9) + pin(3 6) + pin(4 14) + pin(5 9) + ) + circuit(21 INVX1 location(15000 0) + pin(0 6) + pin(1 11) + pin(2 9) + pin(3 6) + pin(4 15) + pin(5 9) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX2 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX2 INVX2 match + xref( + net(5 4 match) + net(1 5 match) + net(3 2 match) + net(6 6 match) + net(2 1 match) + net(4 3 match) + pin(4 3 match) + pin(0 4 match) + pin(2 1 match) + pin(5 5 match) + pin(1 0 match) + pin(3 2 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(4 15 match) + net(2 7 match) + net(10 8 match) + net(12 9 match) + net(13 10 match) + net(14 11 match) + net(15 12 match) + net(11 13 match) + net(3 14 match) + net(8 4 match) + net(5 3 match) + net(7 5 match) + net(6 2 match) + net(9 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(17 4 match) + circuit(18 5 match) + circuit(19 6 match) + circuit(20 7 match) + circuit(21 8 match) + circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 new file mode 100644 index 000000000..be1456dd3 --- /dev/null +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 @@ -0,0 +1,1095 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l3 '1/0') + layer(l4 '5/0') + layer(l8 '8/0') + layer(l11 '9/0') + layer(l12 '10/0') + layer(l13 '11/0') + layer(l7) + layer(l2) + layer(l9) + layer(l6) + layer(l10) + + # Mask layer connectivity + connect(l3 l3 l9) + connect(l4 l4 l8) + connect(l8 l4 l8 l11 l2 l9 l6 l10) + connect(l11 l8 l11 l12) + connect(l12 l11 l12 l13) + connect(l13 l12 l13) + connect(l7 l7) + connect(l2 l8 l2) + connect(l9 l3 l8 l9) + connect(l6 l8 l6) + connect(l10 l8 l10) + + # Global nets and connectivity + global(l7 SUBSTRATE) + global(l10 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (450 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l2 (-575 -750) (450 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l2 (-550 -750) (425 1500)) + ) + terminal(G + rect(l4 (-125 -750) (250 1500)) + ) + terminal(D + rect(l2 (125 -750) (425 1500)) + ) + terminal(B + rect(l3 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (450 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l6 (-575 -475) (450 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l6 (-550 -475) (425 950)) + ) + terminal(G + rect(l4 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l7 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -790) (300 1700)) + rect(l11 (-1350 0) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l2 (-276 -2151) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1810 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-1580 3760) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l11 (-110 1390) (300 1400)) + polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l11 (-141 -501) (2 2)) + rect(l11 (-1751 1099) (300 1400)) + rect(l11 (1100 -1700) (300 300)) + rect(l11 (-300 0) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-1151 -401) (2 2)) + rect(l6 (-951 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2600 3500)) + ) + net(5 name(B) + rect(l4 (1425 2860) (250 1940)) + rect(l4 (-345 -950) (300 300)) + rect(l4 (-205 650) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-285 1050) (180 180)) + rect(l11 (-71 -91) (2 2)) + rect(l11 (-171 -151) (300 300)) + ) + net(6 name(A) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-325 -1850) (300 300)) + rect(l4 (-225 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-265 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(7 name(SUBSTRATE)) + net(8 + rect(l6 (975 1660) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.3375) + param(PS 3.85) + param(PD 1.95) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.21375) + param(PS 2.75) + param(PD 1.4) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.21375) + param(AD 0.40375) + param(PS 1.4) + param(PD 2.75) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-240 -240) (300 1400)) + rect(l11 (-650 300) (1800 800)) + rect(l11 (-1450 -1100) (300 300)) + rect(l11 (299 399) (2 2)) + rect(l2 (-651 -2151) (425 1500)) + ) + net(2 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l6 (-425 -4890) (425 950)) + ) + net(3 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -1300) (300 1360)) + rect(l11 (-650 -2160) (1800 800)) + rect(l11 (-851 -401) (2 2)) + rect(l6 (-651 859) (425 950)) + ) + net(4 + rect(l3 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-525 -1850) (300 300)) + rect(l4 (-25 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-250 -5390) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(IN) + rect(l4 (725 2860) (250 1940)) + rect(l4 (-225 -1300) (675 450)) + rect(l4 (0 -1100) (250 1950)) + rect(l4 (-1225 -1850) (300 300)) + rect(l4 (675 1550) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (-950 -2000) (250 2000)) + rect(l4 (-250 -2000) (250 2000)) + rect(l4 (450 -5390) (250 1450)) + rect(l4 (-950 -1450) (250 1450)) + rect(l8 (-465 150) (180 180)) + rect(l11 (-91 -91) (2 2)) + rect(l11 (-151 -151) (300 300)) + ) + net(2 name(VDD) + rect(l8 (410 6260) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (1220 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l11 (-1640 -240) (300 1400)) + rect(l11 (-650 300) (2400 800)) + rect(l11 (-2050 -1100) (300 300)) + rect(l11 (1100 -300) (300 300)) + rect(l11 (-1101 399) (2 2)) + rect(l11 (799 -2101) (300 1400)) + rect(l2 (-1750 -1450) (425 1500)) + rect(l2 (950 -1500) (425 1500)) + ) + net(3 name(OUT) + rect(l8 (1110 5160) (180 180)) + rect(l8 (-180 920) (180 180)) + rect(l8 (-180 -730) (180 180)) + rect(l8 (-180 -4120) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-240 -790) (300 4790)) + rect(l11 (-151 -2501) (2 2)) + rect(l2 (-226 1049) (425 1500)) + rect(l2 (-400 -1500) (425 1500)) + rect(l6 (-450 -4890) (425 950)) + rect(l6 (-400 -950) (425 950)) + ) + net(4 name(VSS) + rect(l8 (410 1770) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (1220 -730) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-1640 -1300) (300 1360)) + rect(l11 (-650 -2160) (2400 800)) + rect(l11 (-650 0) (300 1360)) + rect(l11 (-1101 -1761) (2 2)) + rect(l6 (724 859) (425 950)) + rect(l6 (-1800 -950) (425 950)) + ) + net(5 + rect(l3 (-100 4500) (2600 3500)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(IN)) + pin(2 name(VDD)) + pin(3 name(OUT)) + pin(4 name(VSS)) + pin(5) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + device(D$PMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 5800) + param(L 0.25) + param(W 3) + param(AS 0.975) + param(AD 0.975) + param(PS 5.8) + param(PD 5.8) + terminal(S 2) + terminal(G 1) + terminal(D 3) + terminal(B 5) + ) + device(3 D$NMOS + device(D$NMOS$1 location(700 0)) + connect(0 S S) + connect(1 S D) + connect(0 G G) + connect(1 G G) + connect(0 D D) + connect(1 D S) + connect(0 B B) + connect(1 B B) + location(850 2135) + param(L 0.25) + param(W 1.9) + param(AS 0.6175) + param(AD 0.6175) + param(PS 4.15) + param(PD 4.15) + terminal(S 4) + terminal(G 1) + terminal(D 3) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((600 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l11 (4040 2950) (610 300)) + ) + net(2 + rect(l11 (5550 2950) (900 300)) + ) + net(3 + rect(l11 (18150 2950) (900 300)) + ) + net(4 + rect(l11 (19950 2950) (900 300)) + ) + net(5 name(FB) + rect(l11 (21750 2950) (900 300)) + rect(l11 (-19530 590) (320 320)) + rect(l11 (17820 -320) (320 320)) + rect(l12 (-18400 -260) (200 200)) + rect(l12 (17940 -200) (200 200)) + rect(l13 (-18040 -300) (17740 400)) + rect(l13 (-17921 -201) (2 2)) + rect(l13 (-221 -201) (400 400)) + rect(l13 (17740 -400) (400 400)) + ) + net(6 name(VDD) + rect(l3 (1100 4500) (1400 3500)) + rect(l3 (-1900 -3500) (600 3500)) + rect(l3 (23300 -3500) (1400 3500)) + rect(l3 (-100 -3500) (600 3500)) + rect(l8 (-24690 -1240) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l11 (-22341 859) (2 2)) + rect(l11 (-1751 -451) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23400 -800) (1200 800)) + rect(l11 (-750 -1450) (300 1400)) + rect(l11 (-101 -351) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l9 (-24850 -1500) (500 1500)) + rect(l9 (22900 -1500) (500 1500)) + ) + net(7 name(OUT) + rect(l11 (23440 3840) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(8 name(ENABLE) + rect(l11 (2440 2940) (320 320)) + rect(l12 (-260 -260) (200 200)) + rect(l13 (-101 -101) (2 2)) + rect(l13 (-201 -201) (400 400)) + ) + net(9 name(VSS) + rect(l8 (1710 1610) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l8 (23220 370) (180 180)) + rect(l8 (-180 -1280) (180 180)) + rect(l8 (-180 370) (180 180)) + rect(l11 (-22341 -391) (2 2)) + rect(l11 (-1301 -401) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (-1251 -401) (600 800)) + rect(l11 (23850 -750) (300 1400)) + rect(l11 (-750 -1450) (1200 800)) + rect(l11 (-551 -401) (2 2)) + rect(l11 (549 -401) (600 800)) + rect(l10 (-24850 -800) (500 1500)) + rect(l10 (22900 -1500) (500 1500)) + ) + net(10 + rect(l11 (7350 2950) (900 300)) + ) + net(11 + rect(l11 (16350 2950) (900 300)) + ) + net(12 + rect(l11 (9150 2950) (900 300)) + ) + net(13 + rect(l11 (10950 2950) (900 300)) + ) + net(14 + rect(l11 (12750 2950) (900 300)) + ) + net(15 + rect(l11 (14550 2950) (900 300)) + ) + + # Outgoing pins and their connections to nets + pin(5 name(FB)) + pin(6 name(VDD)) + pin(7 name(OUT)) + pin(8 name(ENABLE)) + pin(9 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 6) + pin(1 1) + pin(2 9) + pin(3 6) + pin(4 5) + pin(5 8) + pin(6 9) + ) + circuit(2 INVX1 location(4200 0) + pin(0 6) + pin(1 2) + pin(2 9) + pin(3 6) + pin(4 1) + pin(5 9) + ) + circuit(3 INVX1 location(6000 0) + pin(0 6) + pin(1 10) + pin(2 9) + pin(3 6) + pin(4 2) + pin(5 9) + ) + circuit(4 INVX1 location(16800 0) + pin(0 6) + pin(1 3) + pin(2 9) + pin(3 6) + pin(4 11) + pin(5 9) + ) + circuit(5 INVX1 location(18600 0) + pin(0 6) + pin(1 4) + pin(2 9) + pin(3 6) + pin(4 3) + pin(5 9) + ) + circuit(6 INVX1 location(20400 0) + pin(0 6) + pin(1 5) + pin(2 9) + pin(3 6) + pin(4 4) + pin(5 9) + ) + circuit(7 INVX2 location(22200 0) + pin(0 5) + pin(1 6) + pin(2 7) + pin(3 9) + pin(4 6) + pin(5 9) + ) + circuit(13 INVX1 location(7800 0) + pin(0 6) + pin(1 12) + pin(2 9) + pin(3 6) + pin(4 10) + pin(5 9) + ) + circuit(14 INVX1 location(9600 0) + pin(0 6) + pin(1 13) + pin(2 9) + pin(3 6) + pin(4 12) + pin(5 9) + ) + circuit(15 INVX1 location(11400 0) + pin(0 6) + pin(1 14) + pin(2 9) + pin(3 6) + pin(4 13) + pin(5 9) + ) + circuit(16 INVX1 location(13200 0) + pin(0 6) + pin(1 15) + pin(2 9) + pin(3 6) + pin(4 14) + pin(5 9) + ) + circuit(17 INVX1 location(15000 0) + pin(0 6) + pin(1 11) + pin(2 9) + pin(3 6) + pin(4 15) + pin(5 9) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 2) + terminal(G 6) + terminal(D 1) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(INVX2 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 3) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 1.9) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX2 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(INVX2 INVX2 match + xref( + net(5 4 match) + net(1 5 match) + net(3 2 match) + net(6 6 match) + net(2 1 match) + net(4 3 match) + pin(4 3 match) + pin(0 4 match) + pin(2 1 match) + pin(5 5 match) + pin(1 0 match) + pin(3 2 match) + device(3 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(8 8 match) + net(4 4 match) + net(6 6 match) + net(5 5 match) + net(2 2 match) + net(7 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(4 15 match) + net(2 7 match) + net(10 8 match) + net(12 9 match) + net(13 10 match) + net(14 11 match) + net(15 12 match) + net(11 13 match) + net(3 14 match) + net(8 4 match) + net(5 3 match) + net(7 5 match) + net(6 2 match) + net(9 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(13 4 match) + circuit(14 5 match) + circuit(15 6 match) + circuit(16 7 match) + circuit(17 8 match) + circuit(4 9 match) + circuit(5 10 match) + circuit(6 11 match) + circuit(7 12 match) + circuit(1 1 match) + ) + ) +) From 3e32ca1adadaaedbeb91ad7d5a943b70bac459d2 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sun, 15 Dec 2019 23:54:17 +0100 Subject: [PATCH 21/21] Updated test data for Windows. --- testdata/algo/l2n_writer_au_p.txt | 2 + testdata/lvs/ringo_simple_io2.l2n.2 | 519 ++++++++++++++++++++++++++++ 2 files changed, 521 insertions(+) create mode 100644 testdata/lvs/ringo_simple_io2.l2n.2 diff --git a/testdata/algo/l2n_writer_au_p.txt b/testdata/algo/l2n_writer_au_p.txt index 46d72db2a..aeefcf946 100644 --- a/testdata/algo/l2n_writer_au_p.txt +++ b/testdata/algo/l2n_writer_au_p.txt @@ -23,6 +23,8 @@ C(metal2 via1 metal2 metal2_lbl) C(metal2_lbl metal2) C(psd diff_cont psd) C(nsd diff_cont nsd) +K(PMOS MOS3) +K(NMOS MOS3) D(D$PMOS PMOS T(S R(psd (-650 -475) (525 950)) diff --git a/testdata/lvs/ringo_simple_io2.l2n.2 b/testdata/lvs/ringo_simple_io2.l2n.2 new file mode 100644 index 000000000..6b6d1f1d7 --- /dev/null +++ b/testdata/lvs/ringo_simple_io2.l2n.2 @@ -0,0 +1,519 @@ +#%l2n-klayout +W(RINGO) +U(0.001) +L(l3 '1/0') +L(l4 '5/0') +L(l8 '8/0') +L(l11 '9/0') +L(l12 '10/0') +L(l13 '11/0') +L(l7) +L(l2) +L(l9) +L(l6) +L(l10) +C(l3 l3 l9) +C(l4 l4 l8) +C(l8 l4 l8 l11 l2 l9 l6 l10) +C(l11 l8 l11 l12) +C(l12 l11 l12 l13) +C(l13 l12 l13) +C(l7 l7) +C(l2 l8 l2) +C(l9 l3 l8 l9) +C(l6 l8 l6) +C(l10 l8 l10) +G(l7 SUBSTRATE) +G(l10 SUBSTRATE) +K(PMOS MOS4) +K(NMOS MOS4) +D(D$PMOS PMOS + T(S + R(l2 (-550 -750) (425 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (450 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) +) +D(D$PMOS$1 PMOS + T(S + R(l2 (-575 -750) (450 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (425 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) +) +D(D$PMOS$2 PMOS + T(S + R(l2 (-550 -750) (425 1500)) + ) + T(G + R(l4 (-125 -750) (250 1500)) + ) + T(D + R(l2 (125 -750) (425 1500)) + ) + T(B + R(l3 (-125 -750) (250 1500)) + ) +) +D(D$NMOS NMOS + T(S + R(l6 (-550 -475) (425 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (450 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) +) +D(D$NMOS$1 NMOS + T(S + R(l6 (-575 -475) (450 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (425 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) +) +D(D$NMOS$2 NMOS + T(S + R(l6 (-550 -475) (425 950)) + ) + T(G + R(l4 (-125 -475) (250 950)) + ) + T(D + R(l6 (125 -475) (425 950)) + ) + T(B + R(l7 (-125 -475) (250 950)) + ) +) +X(ND2X1 + R((-100 400) (2600 7600)) + N(1 I(VDD) + R(l8 (1110 5160) (180 180)) + R(l8 (-180 920) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l11 (-240 -790) (300 1700)) + R(l11 (-1350 0) (2400 800)) + R(l11 (-1151 -401) (2 2)) + R(l2 (-276 -2151) (425 1500)) + R(l2 (-400 -1500) (425 1500)) + ) + N(2 I(OUT) + R(l8 (1810 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-1580 3760) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (1220 920) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + R(l11 (-110 1390) (300 1400)) + Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + R(l11 (-141 -501) (2 2)) + R(l11 (-1751 1099) (300 1400)) + R(l11 (1100 -1700) (300 300)) + R(l11 (-300 0) (300 1400)) + R(l2 (-375 -1450) (425 1500)) + R(l2 (-1800 -1500) (425 1500)) + R(l6 (950 -4890) (425 950)) + ) + N(3 I(VSS) + R(l8 (410 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -1300) (300 1360)) + R(l11 (-650 -2160) (2400 800)) + R(l11 (-1151 -401) (2 2)) + R(l6 (-951 859) (425 950)) + ) + N(4 + R(l3 (-100 4500) (2600 3500)) + ) + N(5 I(B) + R(l4 (1425 2860) (250 1940)) + R(l4 (-345 -950) (300 300)) + R(l4 (-205 650) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-285 1050) (180 180)) + R(l11 (-71 -91) (2 2)) + R(l11 (-171 -151) (300 300)) + ) + N(6 I(A) + R(l4 (725 2860) (250 1940)) + R(l4 (-325 -1850) (300 300)) + R(l4 (-225 1550) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-265 150) (180 180)) + R(l11 (-91 -91) (2 2)) + R(l11 (-151 -151) (300 300)) + ) + N(7 I(SUBSTRATE)) + N(8 + R(l6 (975 1660) (425 950)) + R(l6 (-400 -950) (425 950)) + ) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4) + P(5 I(B)) + P(6 I(A)) + P(7 I(SUBSTRATE)) + D(1 D$PMOS + Y(850 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.6375) + E(AD 0.3375) + E(PS 3.85) + E(PD 1.95) + T(S 2) + T(G 6) + T(D 1) + T(B 4) + ) + D(2 D$PMOS$1 + Y(1550 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.3375) + E(AD 0.6375) + E(PS 1.95) + E(PD 3.85) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(3 D$NMOS + Y(850 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.40375) + E(AD 0.21375) + E(PS 2.75) + E(PD 1.4) + T(S 3) + T(G 6) + T(D 8) + T(B 7) + ) + D(4 D$NMOS$1 + Y(1550 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.21375) + E(AD 0.40375) + E(PS 1.4) + E(PD 2.75) + T(S 8) + T(G 5) + T(D 2) + T(B 7) + ) +) +X(INVX1 + R((-100 400) (2000 7600)) + N(1 I(VDD) + R(l8 (410 6260) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l11 (-240 -240) (300 1400)) + R(l11 (-650 300) (1800 800)) + R(l11 (-1450 -1100) (300 300)) + R(l11 (299 399) (2 2)) + R(l2 (-651 -2151) (425 1500)) + ) + N(2 I(OUT) + R(l8 (1110 5160) (180 180)) + R(l8 (-180 920) (180 180)) + R(l8 (-180 -730) (180 180)) + R(l8 (-180 -4120) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -790) (300 4790)) + R(l11 (-151 -2501) (2 2)) + R(l2 (-226 1049) (425 1500)) + R(l6 (-425 -4890) (425 950)) + ) + N(3 I(VSS) + R(l8 (410 1770) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-240 -1300) (300 1360)) + R(l11 (-650 -2160) (1800 800)) + R(l11 (-851 -401) (2 2)) + R(l6 (-651 859) (425 950)) + ) + N(4 + R(l3 (-100 4500) (2000 3500)) + ) + N(5 I(IN) + R(l4 (725 2860) (250 1940)) + R(l4 (-525 -1850) (300 300)) + R(l4 (-25 1550) (250 2000)) + R(l4 (-250 -2000) (250 2000)) + R(l4 (-250 -5390) (250 1450)) + R(l8 (-465 150) (180 180)) + R(l11 (-91 -91) (2 2)) + R(l11 (-151 -151) (300 300)) + ) + N(6 I(SUBSTRATE)) + P(1 I(VDD)) + P(2 I(OUT)) + P(3 I(VSS)) + P(4) + P(5 I(IN)) + P(6 I(SUBSTRATE)) + D(1 D$PMOS$2 + Y(850 5800) + E(L 0.25) + E(W 1.5) + E(AS 0.6375) + E(AD 0.6375) + E(PS 3.85) + E(PD 3.85) + T(S 1) + T(G 5) + T(D 2) + T(B 4) + ) + D(2 D$NMOS$2 + Y(850 2135) + E(L 0.25) + E(W 0.95) + E(AS 0.40375) + E(AD 0.40375) + E(PS 2.75) + E(PD 2.75) + T(S 3) + T(G 5) + T(D 2) + T(B 6) + ) +) +X(RINGO + R((0 350) (25800 7650)) + N(1 + R(l11 (4040 2950) (610 300)) + ) + N(2 + R(l11 (5550 2950) (900 300)) + ) + N(3 + R(l11 (7350 2950) (900 300)) + ) + N(4 + R(l11 (9150 2950) (900 300)) + ) + N(5 + R(l11 (10950 2950) (900 300)) + ) + N(6 + R(l11 (12750 2950) (900 300)) + ) + N(7 + R(l11 (14550 2950) (900 300)) + ) + N(8 + R(l11 (16350 2950) (900 300)) + ) + N(9 + R(l11 (18150 2950) (900 300)) + ) + N(10 + R(l11 (19950 2950) (900 300)) + ) + N(11 I(FB) + R(l11 (21750 2950) (900 300)) + R(l11 (-19530 590) (320 320)) + R(l11 (17820 -320) (320 320)) + R(l12 (-18400 -260) (200 200)) + R(l12 (17940 -200) (200 200)) + R(l13 (-18040 -300) (17740 400)) + R(l13 (-17921 -201) (2 2)) + R(l13 (-221 -201) (400 400)) + R(l13 (17740 -400) (400 400)) + ) + N(12 I(VDD) + R(l3 (500 4500) (1400 3500)) + R(l3 (-1900 -3500) (600 3500)) + R(l3 (23300 -3500) (1400 3500)) + R(l3 (-100 -3500) (600 3500)) + R(l8 (-24690 -1240) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (23220 370) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l11 (-21741 859) (2 2)) + R(l11 (-2351 -451) (1200 800)) + R(l11 (-750 -1450) (300 1400)) + R(l11 (-101 -351) (2 2)) + R(l11 (-1251 -401) (600 800)) + R(l11 (23400 -800) (1200 800)) + R(l11 (-750 -1450) (300 1400)) + R(l11 (-101 -351) (2 2)) + R(l11 (549 -401) (600 800)) + R(l9 (-24850 -1500) (500 1500)) + R(l9 (22900 -1500) (500 1500)) + ) + N(13 I(OUT) + R(l11 (23440 3840) (320 320)) + R(l12 (-260 -260) (200 200)) + R(l13 (-101 -101) (2 2)) + R(l13 (-201 -201) (400 400)) + ) + N(14 I(ENABLE) + R(l11 (2440 2940) (320 320)) + R(l12 (-260 -260) (200 200)) + R(l13 (-101 -101) (2 2)) + R(l13 (-201 -201) (400 400)) + ) + N(15 I(VSS) + R(l8 (1110 1610) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + R(l8 (23220 370) (180 180)) + R(l8 (-180 -1280) (180 180)) + R(l8 (-180 370) (180 180)) + R(l11 (-21741 -391) (2 2)) + R(l11 (-1901 -401) (300 1400)) + R(l11 (-750 -1450) (1200 800)) + R(l11 (-551 -401) (2 2)) + R(l11 (-1251 -401) (600 800)) + R(l11 (23850 -750) (300 1400)) + R(l11 (-750 -1450) (1200 800)) + R(l11 (-551 -401) (2 2)) + R(l11 (549 -401) (600 800)) + R(l10 (-24850 -800) (500 1500)) + R(l10 (22900 -1500) (500 1500)) + ) + P(11 I(FB)) + P(12 I(VDD)) + P(13 I(OUT)) + P(14 I(ENABLE)) + P(15 I(VSS)) + X(1 ND2X1 Y(1800 0) + P(0 12) + P(1 1) + P(2 15) + P(3 12) + P(4 11) + P(5 14) + P(6 15) + ) + X(2 INVX1 Y(4200 0) + P(0 12) + P(1 2) + P(2 15) + P(3 12) + P(4 1) + P(5 15) + ) + X(3 INVX1 Y(6000 0) + P(0 12) + P(1 3) + P(2 15) + P(3 12) + P(4 2) + P(5 15) + ) + X(4 INVX1 Y(7800 0) + P(0 12) + P(1 4) + P(2 15) + P(3 12) + P(4 3) + P(5 15) + ) + X(5 INVX1 Y(9600 0) + P(0 12) + P(1 5) + P(2 15) + P(3 12) + P(4 4) + P(5 15) + ) + X(6 INVX1 Y(11400 0) + P(0 12) + P(1 6) + P(2 15) + P(3 12) + P(4 5) + P(5 15) + ) + X(7 INVX1 Y(13200 0) + P(0 12) + P(1 7) + P(2 15) + P(3 12) + P(4 6) + P(5 15) + ) + X(8 INVX1 Y(15000 0) + P(0 12) + P(1 8) + P(2 15) + P(3 12) + P(4 7) + P(5 15) + ) + X(9 INVX1 Y(16800 0) + P(0 12) + P(1 9) + P(2 15) + P(3 12) + P(4 8) + P(5 15) + ) + X(10 INVX1 Y(18600 0) + P(0 12) + P(1 10) + P(2 15) + P(3 12) + P(4 9) + P(5 15) + ) + X(11 INVX1 Y(20400 0) + P(0 12) + P(1 11) + P(2 15) + P(3 12) + P(4 10) + P(5 15) + ) + X(12 INVX1 Y(22200 0) + P(0 12) + P(1 13) + P(2 15) + P(3 12) + P(4 11) + P(5 15) + ) +)