From 2360eb41fdcd0459120e7b682408fc2fd8a6b933 Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Mon, 27 May 2024 19:04:06 +0200 Subject: [PATCH] Generated documentation --- src/doc/doc/about/drc_ref_global.xml | 18 ++++++++++++ src/doc/doc/about/drc_ref_netter.xml | 43 ++++++++++++++++++++++++++++ src/doc/doc/about/lvs_ref_netter.xml | 29 +++++++++++++++++++ 3 files changed, 90 insertions(+) diff --git a/src/doc/doc/about/drc_ref_global.xml b/src/doc/doc/about/drc_ref_global.xml index 45b725686..7fe05da4a 100644 --- a/src/doc/doc/about/drc_ref_global.xml +++ b/src/doc/doc/about/drc_ref_global.xml @@ -1175,6 +1175,24 @@ four-terminal MOS transistor. See DeviceExtractorMOS4Transistor for more details about this extractor (non-strict mode applies for 'mos4').

+

"name" - Assigns a name to a layer for reference in the LVS database

+ +

Usage:

+
    +
  • name(layer, name)
    • +
+

+See Netter#name for a description of that function. +

+

"name_prefix" - Specifies the layer name prefix for auto-generated layer names

+ +

Usage:

+
    +
  • name_prefix(prefix)
    • +
+

+See Netter#name_prefix for a description of that function. +

"netlist" - Obtains the extracted netlist from the default Netter

diff --git a/src/doc/doc/about/drc_ref_netter.xml b/src/doc/doc/about/drc_ref_netter.xml index bd82b4fbd..4ffc860eb 100644 --- a/src/doc/doc/about/drc_ref_netter.xml +++ b/src/doc/doc/about/drc_ref_netter.xml @@ -422,6 +422,49 @@ but no error is raised. The LayoutToNetlist object provides access to the internal details of the netter object.

+

"name" - Assigns a name to a layer

+ +

Usage:

+
    +
  • name(layer, name)
    • +
+

+Layer names are listed in the LayoutToNetlist (L2N) or LVS database. They +are used to identify the layers, the net or device terminal geometries are +on. It is usual to have computed layers, so it is necessary to indicate the +purpose of the layer for later reuse of the geometries. +

+It is a good practice to assign names to computed and original layers, +for example: +

+

+poly = input(...)
+poly_resistor = input(...)
+
+poly_wiring = poly - poly_resistor
+name(poly_wiring, "poly_wiring")
+
+

+Names must be assigned before the layers are used for the first time +in connect, soft_connect, connect_global, soft_connect_global and +extract_devices statements. +

+If layers are not named, they will be given a name made from the +name_prefix and an incremental number when the layer is used for the +first time. +

+name can only be used once on a layer and the layer names must be +unique (not taken by another layer). +

+

"name_prefix" - Specifies the name prefix for auto-generated layer names

+ +

Usage:

+
    +
  • name_prefix(prefix)
    • +
+

+See for details. The default prefix is "l". +

"netlist" - Gets the extracted netlist or triggers extraction if not done yet

Usage:

diff --git a/src/doc/doc/about/lvs_ref_netter.xml b/src/doc/doc/about/lvs_ref_netter.xml index 9feef786f..c983b88f0 100644 --- a/src/doc/doc/about/lvs_ref_netter.xml +++ b/src/doc/doc/about/lvs_ref_netter.xml @@ -396,6 +396,9 @@ the schematic netlist for all circuits starting with "INV": same_nets("INV*", "A*")

+A plain "*" for the net pattern forces all (named) nets to be equivalent between layout and schematic. +Unnamed nets from the extracted netlist are not considered - i.e. nets without a label. +

After using this function, the compare algorithm will consider these nets equivalent. Use this method to provide hints for the comparer in cases which are difficult to resolve otherwise. @@ -404,6 +407,16 @@ circuit_a and net_a are for the layout netlist, circuit_b and net_b for the sche Names are case sensitive for layout-derived netlists and case-insensitive for SPICE schematic netlists.

Use this method andwhere in the script before the compare call. +

+Multiple calls of "same_nets" can be used. The calls are effective in the order +the are given. For example, the following sequence specifies equivalence of all +equally named nets, with the exception of "A" and "B" which are equivalent to each other +inside cell "ND2", despite their different name: +

+

+same_nets("*", "*")
+same_nets("ND2", "A", "B")
+

"same_nets!" - Establishes an equivalence between the nets with matching requirement

@@ -416,6 +429,22 @@ Use this method andwhere in the script before the compare

This method is equivalent to same_nets, but requires identity of the given nets. If the specified nets do not match, an error is reported. +

+For example, this global specification requires all named nets from the +layout to have an equivalent net in the schematic and those nets need to be +identical for all circuits: +

+

+same_nets!("*", "*")
+
+

+The following specification requires "A" and "B" to be identical in +circuit "ND2". It is not an error if either "A" does not exist in the +layout or "B" does not exist in the schematic: +

+

+same_nets!("ND2", "A", "B")
+

"schematic" - Gets, sets or reads the reference netlist